src/bsv/bsv_lib/soc_template.bsv

   1 /*
   2 Copyright (c) 2013, IIT Madras
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
   6
   7 *  Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
   8 *  Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
   9 *  Neither the name of IIT Madras  nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
  10
  11 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  12 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  13 */
  14 package Soc;
  15         /*====== Package imports === */
  16         import FIFO::*;
  17         import FIFOF::*;
  18         import SpecialFIFOs::*;
  19         import GetPut::*;
  20         import ClientServer::*;
  21         import Vector::*;
  22         import Connectable::*;
  23         import Clocks::*;
  24         /*========================== */
  25         /*=== Project imports === */
  26         import ConcatReg::*;
  27         import AXI4_Types::*;
  28         import AXI4_Fabric::*;
  29         import defined_types::*;
  30         import MemoryMap                 :: *;
  31         import slow_peripherals::*;
  32         `include "defines.bsv"
  33         `include "instance_defines.bsv"
  34 {8}
  35     /*====== AXI4 slave declarations =======*/
  36 {3}
  37     /*====== AXI4 Master declarations =======*/
  38 {4}
  39
  40
  41                 `ifdef DMA
  42                         import DMA                               :: *;
  43                 `endif
  44                 `ifdef BOOTROM
  45                         import BootRom                  ::*;
  46                 `endif
  47                 `ifdef SDRAM
  48                         import sdr_top                   :: *;
  49     `endif
  50                 `ifdef BRAM
  51                         import Memory_AXI4      ::*;
  52                 `endif
  53                 `ifdef TCMemory
  54                         import TCM::*;
  55                 `endif
  56                 `ifdef Debug
  57                         import jtagdtm::*;
  58                         import DebugModule::*;
  59                 `else
  60                         import core::*;
  61                 `endif
  62 `ifdef  VME
  63                         import vme_top ::*;
  64 `endif
  65
  66 `ifdef VME
  67                         import vme_master::*;
  68 `endif
  69 `ifdef FlexBus
  70             import FlexBus_Types::*;
  71 `endif
  72 {0}
  73
  74         /*========================= */
  75         interface Ifc_Soc;
  76                 interface SP_ios slow_ios;
  77                 (*always_ready,always_enabled*)
  78                 method Action boot_sequence(Bit#(1) bootseq);
  79
  80                   `ifdef SDRAM
  81                         (*always_ready*) interface Ifc_sdram_out sdram_out;
  82                 `endif
  83       `ifdef DDR
  84         (*prefix="M_AXI"*) interface AXI4_Master_IFC#(`PADDR, `Reg_width, `USERSPACE) master;
  85       `endif
  86                 `ifdef HYPER
  87                         (*always_ready,always_enabled*)
  88                    interface Ifc_flash ifc_flash;
  89                 `endif
  90         /*=============================================== */
  91            `ifdef VME
  92                         interface Vme_out  proc_ifc;
  93                         interface Data_bus_inf proc_dbus;
  94                 `endif
  95         `ifdef FlexBus
  96             interface FlexBus_Master_IFC flexbus_out;
  97         `endif
  98 {1}
  99         endinterface
 100         (*synthesize*)
 101         module mkSoc #(Bit#(`VADDR) reset_vector, Clock slow_clock, Reset slow_reset, Clock uart_clock,
 102                  Reset uart_reset, Clock clk0, Clock tck, Reset trst
 103                  `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif )(Ifc_Soc);
 104                 Clock core_clock <-exposeCurrentClock; // slow peripheral clock
 105                 Reset core_reset <-exposeCurrentReset; // slow peripheral reset
 106 {2}
 107       `ifdef Debug
 108                         Ifc_DebugModule core<-mkDebugModule(reset_vector);
 109                 `else
 110                         Ifc_core_AXI4 core <-mkcore_AXI4(reset_vector);
 111                 `endif
 112                 `ifdef BOOTROM
 113                         BootRom_IFC bootrom <-mkBootRom;
 114                 `endif
 115                 `ifdef SDRAM
 116                         Ifc_sdr_slave sdram<- mksdr_axi4_slave(clk0);
 117                 `endif
 118     `ifdef BRAM
 119                         Memory_IFC#(`SDRAMMemBase,`Addr_space)main_memory <-
 120                         mkMemory("code.mem.MSB","code.mem.LSB","MainMEM");
 121                 `endif
 122                 `ifdef TCMemory
 123                         Ifc_TCM                                 tcm                             <- mkTCM;
 124                 `endif
 125                 `ifdef DMA
 126                         DmaC#(7,`NUM_DMACHANNELS) dma   <- mkDMA();
 127                 `endif
 128                         `ifdef VME
 129                         Ifc_vme_top             vme             <-mkvme_top();
 130                         `endif
 131         `ifdef FlexBus
 132             AXI4_Slave_to_FlexBus_Master_Xactor_IFC #(32, 64,0)
 133                             flexbus <- mkAXI4_Slave_to_FlexBus_Master_Xactor;
 134         `endif
 135                 Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals(
 136           core_clock, core_reset, uart_clock,
 137           uart_reset, clocked_by slow_clock , reset_by slow_reset
 138           `ifdef PWM_AXI4Lite , ext_pwm_clock `endif );
 139
 140         // Fabric
 141         AXI4_Fabric_IFC #(Num_Masters, Num_Slaves, `PADDR, `Reg_width,`USERSPACE)
 142                                 fabric <- mkAXI4_Fabric(fn_addr_to_slave_num);
 143
 144         // Connect traffic generators to fabric
 145         mkConnection (core.dmem_master,fabric.v_from_masters
 146                               [fromInteger(valueOf(Dmem_master_num))]);
 147         mkConnection (core.imem_master, fabric.v_from_masters
 148                               [fromInteger(valueOf(Imem_master_num))]);
 149                 `ifdef Debug
 150                         mkConnection (core.debug_master, fabric.v_from_masters
 151                               [fromInteger(valueOf(Debug_master_num))]);
 152                 `endif
 153                 `ifdef DMA
 154          mkConnection (dma.mmu, fabric.v_from_masters
 155                               [fromInteger(valueOf(DMA_master_num))]);
 156                 `endif
 157
 158
 159                 // Connect fabric to memory slaves
 160                         `ifdef Debug
 161                                 mkConnection (fabric.v_to_slaves
 162                               [fromInteger(valueOf(Debug_slave_num))],
 163                               core.debug_slave);
 164                         `endif
 165                         `ifdef SDRAM
 166                                 mkConnection (fabric.v_to_slaves
 167                               [fromInteger(valueOf(Sdram_slave_num))],
 168                               sdram.axi4_slave_sdram); //
 169                         mkConnection (fabric.v_to_slaves
 170                               [fromInteger(valueOf(Sdram_cfg_slave_num))],
 171                               sdram.axi4_slave_cntrl_reg); //
 172       `endif
 173       `ifdef BRAM
 174                                 mkConnection(fabric.v_to_slaves
 175                               [fromInteger(valueOf(Sdram_slave_num))],
 176                               main_memory.axi_slave);
 177                         `endif
 178                         `ifdef BOOTROM
 179                                 mkConnection (fabric.v_to_slaves
 180                               [fromInteger(valueOf(BootRom_slave_num))],
 181                               bootrom.axi_slave);
 182                         `endif
 183                         `ifdef DMA
 184                         mkConnection (fabric.v_to_slaves
 185                               [fromInteger(valueOf(Dma_slave_num))],
 186                               dma.cfg); //DMA slave
 187                         `endif
 188                         `ifdef TCMemory
 189                                 mkConnection (fabric.v_to_slaves
 190                               [fromInteger(valueOf(TCM_slave_num))],
 191                               tcm.axi_slave);
 192                         `endif
 193                         mkConnection(fabric.v_to_slaves
 194                               [fromInteger(valueOf(SlowPeripheral_slave_num))],
 195                               slow_peripherals.axi_slave);
 196                         `ifdef VME
 197                                 mkConnection (fabric.v_to_slaves
 198                               [fromInteger(valueOf(VME_slave_num))],
 199                               vme.slave_axi_vme);
 200                         `endif
 201                         `ifdef FlexBus
 202                                 mkConnection (fabric.v_to_slaves
 203                               [fromInteger(valueOf(FlexBus_slave_num))],
 204                               flexbus.axi_side);
 205                         `endif
 206
 207 // fabric connections
 208 {5}
 209
 210                         `ifdef DMA
 211                         //rule to connect all interrupt lines to the DMA
 212                         //All the interrupt lines to DMA are active HIGH. For peripherals that are not connected, or those which do not
 213                         //generate an interrupt (like TCM), drive a constant 1 on the corresponding interrupt line.
 214 {7}
 215                         `endif
 216
 217
 218                 /*======= Synchornization between the JTAG and the Debug Module ========= */
 219                 `ifdef Debug
 220                         SyncFIFOIfc#(Bit#(40)) sync_request_to_dm <-mkSyncFIFOToCC(1,tck,trst);
 221                         SyncFIFOIfc#(Bit#(34)) sync_response_from_dm <-mkSyncFIFOFromCC(1,tck);
 222                         rule connect_tap_request_to_syncfifo;
 223                                 let x<-tap.request_to_dm;
 224                                 sync_request_to_dm.enq(x);
 225                         endrule
 226                         rule read_synced_request_to_dm;
 227                                 sync_request_to_dm.deq;
 228                                 core.request_from_dtm(sync_request_to_dm.first);
 229                         endrule
 230
 231                         rule connect_debug_response_to_syncfifo;
 232                                 let x<-core.response_to_dtm;
 233                                 sync_response_from_dm.enq(x);
 234                         endrule
 235                         rule read_synced_response_from_dm;
 236                                 sync_response_from_dm.deq;
 237                                 tap.response_from_dm(sync_response_from_dm.first);
 238                         endrule
 239                 `endif
 240                 /*======================================================================= */
 241
 242         `ifdef FlexBus
 243             //rule drive_flexbus_inputs;
 244                //flexbus.flexbus_side.m_TAn(1'b1);
 245                //flexbus.flexbus_side.m_din(32'haaaaaaaa);
 246             //endrule
 247          `endif
 248
 249                 `ifdef CLINT
 250                         SyncBitIfc#(Bit#(1)) clint_mtip_int <-mkSyncBitToCC(slow_clock,slow_reset);
 251                         SyncBitIfc#(Bit#(1)) clint_msip_int <-mkSyncBitToCC(slow_clock,slow_reset);
 252                         Reg#(Bit#(`Reg_width)) clint_mtime_value <-mkSyncRegToCC(0,slow_clock,slow_reset);
 253                         rule synchronize_clint_data;
 254                                 clint_mtip_int.send(slow_peripherals.mtip_int);
 255                                 clint_msip_int.send(slow_peripherals.msip_int);
 256                                 clint_mtime_value<=slow_peripherals.mtime;
 257                         endrule
 258                         rule connect_msip_mtip_from_clint;
 259                                 core.clint_msip(clint_msip_int.read);
 260                                 core.clint_mtip(clint_mtip_int.read);
 261             core.clint_mtime(clint_mtime_value);
 262                         endrule
 263                 `endif
 264                 `ifdef PLIC
 265                         Reg#(Tuple2#(Bool,Bool)) plic_interrupt_note <-mkSyncRegToCC(tuple2(False,False),slow_clock,slow_reset);
 266                         rule synchronize_interrupts;
 267                                 let note <- slow_peripherals.intrpt_note;
 268                                 plic_interrupt_note<=note;
 269                         endrule
 270          rule rl_send_external_interrupt_to_csr;
 271                                 core.set_external_interrupt(plic_interrupt_note);
 272                         endrule
 273                 `endif
 274
 275                 `ifdef VME
 276                         interface  proc_ifc = vme.proc_ifc;
 277                         interface   proc_dbus = vme.proc_dbus;
 278                 `endif
 279                 `ifdef FlexBus
 280             interface flexbus_out = flexbus.flexbus_side;
 281                 `endif
 282       method Action boot_sequence(Bit#(1) bootseq) = core.boot_sequence(bootseq);
 283                 `ifdef SDRAM
 284                         interface sdram_out=sdram.ifc_sdram_out;
 285                 `endif
 286     `ifdef DDR
 287       interface master=fabric.v_to_slaves[fromInteger(valueOf(Sdram_slave_num))];
 288     `endif
 289                 interface slow_ios=slow_peripherals.slow_ios;
 290 {6}
 291         endmodule
 292 endpackage