src/bsv/bsv_lib/soc_template.bsv

   1 /*
   2 Copyright (c) 2013, IIT Madras
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
   6
   7 *  Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
   8 *  Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
   9 *  Neither the name of IIT Madras  nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
  10
  11 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  12 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  13 */
  14 package Soc;
  15         /*====== Package imports === */
  16         import FIFO::*;
  17         import FIFOF::*;
  18         import SpecialFIFOs::*;
  19         import GetPut::*;
  20         import ClientServer::*;
  21         import Vector::*;
  22         import Connectable::*;
  23         import Clocks::*;
  24         /*========================== */
  25         /*=== Project imports === */
  26         import ConcatReg::*;
  27         import AXI4_Types::*;
  28         import AXI4_Fabric::*;
  29         import defined_types::*;
  30         import MemoryMap                 :: *;
  31         import slow_peripherals::*;
  32         `include "defines.bsv"
  33         `include "instance_defines.bsv"
  34
  35                 `ifdef DMA
  36                         import DMA                               :: *;
  37                 `endif
  38                 `ifdef BOOTROM
  39                         import BootRom                  ::*;
  40                 `endif
  41                 `ifdef SDRAM
  42                         import sdr_top                   :: *;
  43     `endif
  44                 `ifdef BRAM
  45                         import Memory_AXI4      ::*;
  46                 `endif
  47                 `ifdef TCMemory
  48                         import TCM::*;
  49                 `endif
  50                 `ifdef Debug
  51                         import jtagdtm::*;
  52                         import DebugModule::*;
  53                 `else
  54                         import core::*;
  55                 `endif
  56 `ifdef  VME
  57                         import vme_top ::*;
  58 `endif
  59
  60 `ifdef VME
  61                         import vme_master::*;
  62 `endif
  63 `ifdef FlexBus
  64             import FlexBus_Types::*;
  65 `endif
  66 {0}
  67
  68         /*========================= */
  69         interface Ifc_Soc;
  70                 interface SP_ios slow_ios;
  71                 (*always_ready,always_enabled*)
  72                 method Action boot_sequence(Bit#(1) bootseq);
  73
  74                   `ifdef SDRAM
  75                         (*always_ready*) interface Ifc_sdram_out sdram_out;
  76                 `endif
  77       `ifdef DDR
  78         (*prefix="M_AXI"*) interface AXI4_Master_IFC#(`PADDR, `Reg_width, `USERSPACE) master;
  79       `endif
  80       `ifdef Debug
  81                         (*always_ready,always_enabled*)
  82                         method Action tms_i(Bit#(1) tms);
  83                         (*always_ready,always_enabled*)
  84                         method Action tdi_i(Bit#(1) tdi);
  85                         (*always_ready,always_enabled*)
  86                         method Action bs_chain_i(Bit#(1) bs_chain);
  87                         (*always_ready,always_enabled*)
  88                         method Bit#(1) shiftBscan2Edge;
  89                         (*always_ready,always_enabled*)
  90                         method Bit#(1) selectJtagInput;
  91                         (*always_ready,always_enabled*)
  92                         method Bit#(1) selectJtagOutput;
  93                         (*always_ready,always_enabled*)
  94                         method Bit#(1) updateBscan;
  95                         (*always_ready,always_enabled*)
  96                         method Bit#(1) bscan_in;
  97                         (*always_ready,always_enabled*)
  98                         method Bit#(1) scan_shift_en;
  99                         (*always_ready,always_enabled*)
 100                         method Bit#(1) tdo;
 101                         (*always_ready,always_enabled*)
 102                         method Bit#(1) tdo_oe;
 103                 `endif
 104                 `ifdef HYPER
 105                         (*always_ready,always_enabled*)
 106                    interface Ifc_flash ifc_flash;
 107                 `endif
 108         /*=============================================== */
 109            `ifdef VME
 110                         interface Vme_out  proc_ifc;
 111                         interface Data_bus_inf proc_dbus;
 112                 `endif
 113         `ifdef FlexBus
 114             interface FlexBus_Master_IFC flexbus_out;
 115         `endif
 116
 117         endinterface
 118         (*synthesize*)
 119         module mkSoc #(Bit#(`VADDR) reset_vector, Clock slow_clock, Reset slow_reset, Clock uart_clock,
 120                  Reset uart_reset, Clock clk0, Clock tck, Reset trst
 121                  `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif )(Ifc_Soc);
 122                 Clock core_clock <-exposeCurrentClock; // slow peripheral clock
 123                 Reset core_reset <-exposeCurrentReset; // slow peripheral reset
 124       `ifdef Debug
 125                         Ifc_jtagdtm tap <-mkjtagdtm(clocked_by tck, reset_by trst);
 126          rule drive_tmp_scan_outs;
 127              tap.scan_out_1_i(1'b0);
 128              tap.scan_out_2_i(1'b0);
 129              tap.scan_out_3_i(1'b0);
 130              tap.scan_out_4_i(1'b0);
 131              tap.scan_out_5_i(1'b0);
 132          endrule
 133                         Ifc_DebugModule core<-mkDebugModule(reset_vector);
 134                 `else
 135                         Ifc_core_AXI4 core <-mkcore_AXI4(reset_vector);
 136                 `endif
 137                 `ifdef BOOTROM
 138                         BootRom_IFC bootrom <-mkBootRom;
 139                 `endif
 140                 `ifdef SDRAM
 141                         Ifc_sdr_slave                   sdram                           <- mksdr_axi4_slave(clk0);
 142                 `endif
 143     `ifdef BRAM
 144                         Memory_IFC#(`SDRAMMemBase,`Addr_space) main_memory <- mkMemory("code.mem.MSB","code.mem.LSB","MainMEM");
 145                 `endif
 146                 `ifdef TCMemory
 147                         Ifc_TCM                                 tcm                             <- mkTCM;
 148                 `endif
 149                 `ifdef DMA
 150                         DmaC#(7,12)                             dma                             <- mkDMA();
 151                 `endif
 152                         `ifdef VME
 153                         Ifc_vme_top             vme             <-mkvme_top();
 154                         `endif
 155         `ifdef FlexBus
 156             AXI4_Slave_to_FlexBus_Master_Xactor_IFC #(32, 64,0)
 157                                             flexbus <- mkAXI4_Slave_to_FlexBus_Master_Xactor;
 158         `endif
 159                 Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals(core_clock, core_reset, uart_clock,
 160           uart_reset, clocked_by slow_clock , reset_by slow_reset
 161           `ifdef PWM_AXI4Lite , ext_pwm_clock `endif );
 162
 163         // Fabric
 164         AXI4_Fabric_IFC #(Num_Masters, Num_Slaves, `PADDR, `Reg_width,`USERSPACE)
 165                                 fabric <- mkAXI4_Fabric(fn_addr_to_slave_num);
 166
 167         // Connect traffic generators to fabric
 168         mkConnection (core.dmem_master, fabric.v_from_masters [fromInteger(valueOf(Dmem_master_num))]);
 169         mkConnection (core.imem_master, fabric.v_from_masters [fromInteger(valueOf(Imem_master_num))]);
 170                 `ifdef Debug
 171                         mkConnection (core.debug_master, fabric.v_from_masters [fromInteger(valueOf(Debug_master_num))]);
 172                 `endif
 173                 `ifdef DMA
 174          mkConnection (dma.mmu, fabric.v_from_masters[fromInteger(valueOf(DMA_master_num))]);
 175                 `endif
 176
 177
 178                 // Connect fabric to memory slaves
 179                         `ifdef Debug
 180                                 mkConnection (fabric.v_to_slaves [fromInteger(valueOf(Debug_slave_num))],core.debug_slave);
 181                         `endif
 182                         `ifdef SDRAM
 183                                 mkConnection (fabric.v_to_slaves [fromInteger(valueOf(Sdram_slave_num))],       sdram.axi4_slave_sdram); //
 184                         mkConnection (fabric.v_to_slaves [fromInteger(valueOf(Sdram_cfg_slave_num))],   sdram.axi4_slave_cntrl_reg); //
 185       `endif
 186       `ifdef BRAM
 187                                 mkConnection(fabric.v_to_slaves[fromInteger(valueOf(Sdram_slave_num))],main_memory.axi_slave);
 188                         `endif
 189                         `ifdef BOOTROM
 190                                 mkConnection (fabric.v_to_slaves [fromInteger(valueOf(BootRom_slave_num))],bootrom.axi_slave);
 191                         `endif
 192                         `ifdef DMA
 193                         mkConnection (fabric.v_to_slaves [fromInteger(valueOf(Dma_slave_num))], dma.cfg); //DMA slave
 194                         `endif
 195                         `ifdef TCMemory
 196                                 mkConnection (fabric.v_to_slaves [fromInteger(valueOf(TCM_slave_num))],tcm.axi_slave);
 197                         `endif
 198                         mkConnection(fabric.v_to_slaves [fromInteger(valueOf(SlowPeripheral_slave_num))],slow_peripherals.axi_slave);
 199                         `ifdef VME
 200                                 mkConnection (fabric.v_to_slaves[fromInteger(valueOf(VME_slave_num))],vme.slave_axi_vme);
 201                         `endif
 202                         `ifdef FlexBus
 203                                 mkConnection (fabric.v_to_slaves[fromInteger(valueOf(FlexBus_slave_num))],flexbus.axi_side);
 204                         `endif
 205                         `ifdef DMA
 206                         //rule to connect all interrupt lines to the DMA
 207                         //All the interrupt lines to DMA are active HIGH. For peripherals that are not connected, or those which do not
 208                         //generate an interrupt (like TCM), drive a constant 1 on the corresponding interrupt line.
 209                                 `ifdef I2C1 SyncBitIfc#(Bit#(1)) i2c1_interrupt <-mkSyncBitToCC(slow_clock,slow_reset); `endif
 210                                 `ifdef I2C0 SyncBitIfc#(Bit#(1)) i2c0_interrupt <-mkSyncBitToCC(slow_clock,slow_reset); `endif
 211                                 `ifdef QSPI1 SyncBitIfc#(Bit#(1)) qspi1_interrupt <-mkSyncBitToCC(slow_clock,slow_reset); `endif
 212                                 `ifdef QSPI0 SyncBitIfc#(Bit#(1)) qspi0_interrupt <-mkSyncBitToCC(slow_clock,slow_reset); `endif
 213                                 `ifdef UART0 SyncBitIfc#(Bit#(1)) uart0_interrupt <-mkSyncBitToCC(uart_clock,uart_reset); `endif
 214                                 rule synchronize_i2c_interrupts;
 215                                         `ifdef I2C1 i2c1_interrupt.send(slow_peripherals.i2c1_isint); `endif
 216                                         `ifdef I2C0 i2c0_interrupt.send(slow_peripherals.i2c0_isint); `endif
 217                                 endrule
 218                                 rule synchronize_qspi_interrupts;
 219                                         `ifdef QSPI0 qspi0_interrupt.send(slow_peripherals.qspi0_isint); `endif
 220                                         `ifdef QSPI1 qspi1_interrupt.send(slow_peripherals.qspi1_isint); `endif
 221                                 endrule
 222                                 rule synchronize_uart0_interrupt;
 223                                         `ifdef UART0 uart0_interrupt.send(slow_peripherals.uart0_intr); `endif
 224                                 endrule
 225                                 rule rl_connect_interrupt_to_DMA;
 226                                         Bit#(12) lv_interrupt_to_DMA= {{'d-1,
 227                                                                                                                         `ifdef I2C1 i2c1_interrupt.read `else 1'b1 `endif ,
 228                                                                                                                         `ifdef I2C0 i2c0_interrupt.read `else 1'b1 `endif ,
 229                                                                                                                         `ifdef QSPI1 qspi1_interrupt.read `else 1'b1 `endif ,
 230                                                                                                                         1'b1,
 231                                                                                                                         `ifdef QSPI0 qspi0_interrupt.read `else 1'b1 `endif ,
 232                                                                                                                         1'b1,1'b0,
 233                                                                                                                         `ifdef UART0 uart0_interrupt.read `else 1'b1 `endif }};
 234                                         dma.interrupt_from_peripherals(lv_interrupt_to_DMA);
 235                                 endrule
 236                         `endif
 237
 238
 239                 /*======= Synchornization between the JTAG and the Debug Module ========= */
 240                 `ifdef Debug
 241                         SyncFIFOIfc#(Bit#(40)) sync_request_to_dm <-mkSyncFIFOToCC(1,tck,trst);
 242                         SyncFIFOIfc#(Bit#(34)) sync_response_from_dm <-mkSyncFIFOFromCC(1,tck);
 243                         rule connect_tap_request_to_syncfifo;
 244                                 let x<-tap.request_to_dm;
 245                                 sync_request_to_dm.enq(x);
 246                         endrule
 247                         rule read_synced_request_to_dm;
 248                                 sync_request_to_dm.deq;
 249                                 core.request_from_dtm(sync_request_to_dm.first);
 250                         endrule
 251
 252                         rule connect_debug_response_to_syncfifo;
 253                                 let x<-core.response_to_dtm;
 254                                 sync_response_from_dm.enq(x);
 255                         endrule
 256                         rule read_synced_response_from_dm;
 257                                 sync_response_from_dm.deq;
 258                                 tap.response_from_dm(sync_response_from_dm.first);
 259                         endrule
 260                 `endif
 261                 /*======================================================================= */
 262
 263         `ifdef FlexBus
 264             //rule drive_flexbus_inputs;
 265                //flexbus.flexbus_side.m_TAn(1'b1);
 266                //flexbus.flexbus_side.m_din(32'haaaaaaaa);
 267             //endrule
 268          `endif
 269
 270                 `ifdef CLINT
 271                         SyncBitIfc#(Bit#(1)) clint_mtip_int <-mkSyncBitToCC(slow_clock,slow_reset);
 272                         SyncBitIfc#(Bit#(1)) clint_msip_int <-mkSyncBitToCC(slow_clock,slow_reset);
 273                         Reg#(Bit#(`Reg_width)) clint_mtime_value <-mkSyncRegToCC(0,slow_clock,slow_reset);
 274                         rule synchronize_clint_data;
 275                                 clint_mtip_int.send(slow_peripherals.mtip_int);
 276                                 clint_msip_int.send(slow_peripherals.msip_int);
 277                                 clint_mtime_value<=slow_peripherals.mtime;
 278                         endrule
 279                         rule connect_msip_mtip_from_clint;
 280                                 core.clint_msip(clint_msip_int.read);
 281                                 core.clint_mtip(clint_mtip_int.read);
 282             core.clint_mtime(clint_mtime_value);
 283                         endrule
 284                 `endif
 285                 `ifdef PLIC
 286                         Reg#(Tuple2#(Bool,Bool)) plic_interrupt_note <-mkSyncRegToCC(tuple2(False,False),slow_clock,slow_reset);
 287                         rule synchronize_interrupts;
 288                                 let note <- slow_peripherals.intrpt_note;
 289                                 plic_interrupt_note<=note;
 290                         endrule
 291          rule rl_send_external_interrupt_to_csr;
 292                                 core.set_external_interrupt(plic_interrupt_note);
 293                         endrule
 294                 `endif
 295
 296                 `ifdef VME
 297                         interface  proc_ifc = vme.proc_ifc;
 298                         interface   proc_dbus = vme.proc_dbus;
 299                 `endif
 300                 `ifdef FlexBus
 301             interface flexbus_out = flexbus.flexbus_side;
 302                 `endif
 303       method Action boot_sequence(Bit#(1) bootseq) = core.boot_sequence(bootseq);
 304                 `ifdef SDRAM
 305                         interface sdram_out=sdram.ifc_sdram_out;
 306                 `endif
 307     `ifdef DDR
 308       interface master=fabric.v_to_slaves[fromInteger(valueOf(Sdram_slave_num))];
 309     `endif
 310                 `ifdef Debug
 311                         method Action tms_i(Bit#(1) tms);
 312                                 tap.tms_i(tms);
 313                         endmethod
 314                         method Action tdi_i(Bit#(1) tdi);
 315                                 tap.tdi_i(tdi);
 316                         endmethod
 317                         method Action bs_chain_i(Bit#(1) bs_chain);
 318                                 tap.bs_chain_i(bs_chain);
 319                         endmethod
 320                         method Bit#(1) shiftBscan2Edge=tap.shiftBscan2Edge;
 321                         method Bit#(1) selectJtagInput=tap.selectJtagInput;
 322                         method Bit#(1) selectJtagOutput=tap.selectJtagOutput;
 323                         method Bit#(1) updateBscan=tap.updateBscan;
 324                         method Bit#(1) bscan_in=tap.bscan_in;
 325             method Bit#(1) scan_shift_en=tap.scan_shift_en;
 326                         method Bit#(1) tdo=tap.tdo;
 327                         method Bit#(1) tdo_oe=tap.tdo_oe;
 328                 `endif
 329                 interface slow_ios=slow_peripherals.slow_ios;
 330
 331         endmodule
 332 endpackage