2 Copyright (c) 2013, IIT Madras
5 Redistribution and use in source and binary forms, with or without
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14 * Neither the name of IIT Madras nor the names of its contributors
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16 without specific prior written permission.
18 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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24 TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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27 NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 -------------------------------------------------------------------
32 /*====== Package imports === */
35 import SpecialFIFOs::*;
37 import ClientServer::*;
39 import Connectable::*;
42 /*=== Project imports === */
46 import AXI4_Fabric::*;
47 import defined_types::*;
48 import MemoryMap :: *;
49 import slow_peripherals::*;
50 import fast_memory_map::*;
51 import slow_memory_map::*;
53 `include "defines.bsv"
55 `include "instance_defines.bsv"
56 `include "core_parameters.bsv"
69 import Memory_AXI4 ::*;
75 import DebugModule::*;
88 /*========================= */
90 interface SP_dedicated_ios slow_ios;
91 interface IOCellSide iocell_side;
92 (*always_ready,always_enabled*)
93 method Action boot_sequence(Bit#(1) bootseq);
96 (*always_ready*) interface Ifc_sdram_out sdram_out;
99 (*prefix="M_AXI"*) interface
100 AXI4_Master_IFC#(`PADDR, `DATA, `USERSPACE) master;
103 (*always_ready,always_enabled*)
104 interface Ifc_flash ifc_flash;
106 /*=============================================== */
108 interface Vme_out proc_ifc;
109 interface Data_bus_inf proc_dbus;
114 //============ mkSoc module =================
117 module mkSoc #(Bit#(`VADDR) reset_vector,
118 Clock slow_clock, Reset slow_reset, Clock uart_clock,
119 Reset uart_reset, Clock clk0, Clock tck, Reset trst
120 `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif )(Ifc_Soc);
121 Clock core_clock <-exposeCurrentClock; // slow peripheral clock
122 Reset core_reset <-exposeCurrentReset; // slow peripheral reset
125 Ifc_DebugModule core<-mkDebugModule(reset_vector);
127 Ifc_core_AXI4 core <-mkcore_AXI4(reset_vector);
130 BootRom_IFC bootrom <-mkBootRom;
133 Ifc_sdr_slave sdram<- mksdr_axi4_slave(clk0);
136 Memory_IFC#(`SDRAMMemBase,`Addr_space)main_memory <-
137 mkMemory("code.mem.MSB","code.mem.LSB","MainMEM");
140 Ifc_TCM tcm <- mkTCM;
143 DmaC#(7,`NUM_DMACHANNELS) dma <- mkDMA();
146 Ifc_vme_top vme <-mkvme_top();
148 Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals(
149 core_clock, core_reset,
150 uart_clock, uart_reset,
151 clocked_by slow_clock, reset_by slow_reset
152 `ifdef PWM_AXI4Lite , ext_pwm_clock `endif );
154 // clock sync mkConnections
158 AXI4_Fabric_IFC #(Num_Masters, Num_Fast_Slaves,
159 `PADDR, `DATA,`USERSPACE)
160 fabric <- mkAXI4_Fabric(fn_addr_to_slave_num);
162 // Connect traffic generators to fabric
163 mkConnection (core.dmem_master,fabric.v_from_masters
164 [fromInteger(valueOf(Dmem_master_num))]);
165 mkConnection (core.imem_master, fabric.v_from_masters
166 [fromInteger(valueOf(Imem_master_num))]);
168 mkConnection (core.debug_master, fabric.v_from_masters
169 [fromInteger(valueOf(Debug_master_num))]);
172 mkConnection (dma.mmu, fabric.v_from_masters
173 [fromInteger(valueOf(DMA_master_num))]);
178 // Connect fabric to memory slaves
180 mkConnection (fabric.v_to_slaves
181 [fromInteger(valueOf(Debug_slave_num))],
185 mkConnection (fabric.v_to_slaves
186 [fromInteger(valueOf(Sdram_slave_num))],
187 sdram.axi4_slave_sdram); //
188 mkConnection (fabric.v_to_slaves
189 [fromInteger(valueOf(Sdram_cfg_slave_num))],
190 sdram.axi4_slave_cntrl_reg); //
193 mkConnection(fabric.v_to_slaves
194 [fromInteger(valueOf(Sdram_slave_num))],
195 main_memory.axi_slave);
198 mkConnection (fabric.v_to_slaves
199 [fromInteger(valueOf(BootRom_slave_num))],
203 mkConnection (fabric.v_to_slaves
204 [fromInteger(valueOf(Dma_slave_num))],
205 dma.cfg); //DMA slave
208 mkConnection (fabric.v_to_slaves
209 [fromInteger(valueOf(TCM_slave_num))],
212 mkConnection(fabric.v_to_slaves
213 [fromInteger(valueOf(SlowPeripheral_slave_num))],
214 slow_peripherals.axi_slave);
216 mkConnection (fabric.v_to_slaves
217 [fromInteger(valueOf(VME_slave_num))],
224 // fabric connections
228 // rule to connect all interrupt lines to the DMA
229 // All the interrupt lines to DMA are active
230 // HIGH. For peripherals that are not connected,
231 // or those which do not
232 // generate an interrupt (like TCM), drive a constant 1
233 // on the corresponding interrupt line.
238 /*==== Synchornization between the JTAG and the Debug Module ===== */
240 SyncFIFOIfc#(Bit#(40)) sync_request_to_dm <-
241 mkSyncFIFOToCC(1,tck,trst);
242 SyncFIFOIfc#(Bit#(34)) sync_response_from_dm <-
243 mkSyncFIFOFromCC(1,tck);
244 rule connect_tap_request_to_syncfifo;
245 let x<-tap.request_to_dm;
246 sync_request_to_dm.enq(x);
248 rule read_synced_request_to_dm;
249 sync_request_to_dm.deq;
250 core.request_from_dtm(sync_request_to_dm.first);
253 rule connect_debug_response_to_syncfifo;
254 let x<-core.response_to_dtm;
255 sync_response_from_dm.enq(x);
257 rule read_synced_response_from_dm;
258 sync_response_from_dm.deq;
259 tap.response_from_dm(sync_response_from_dm.first);
262 /*============================================================ */
265 //rule drive_flexbus_inputs;
266 //flexbus.flexbus_side.m_TAn(1'b1);
267 //flexbus.flexbus_side.m_din(32'haaaaaaaa);
272 SyncBitIfc#(Bit#(1)) clint_mtip_int <-
273 mkSyncBitToCC(slow_clock,slow_reset);
274 SyncBitIfc#(Bit#(1)) clint_msip_int <-
275 mkSyncBitToCC(slow_clock,slow_reset);
276 Reg#(Bit#(`DATA)) clint_mtime_value <-
277 mkSyncRegToCC(0,slow_clock,slow_reset);
278 rule synchronize_clint_data;
279 clint_mtip_int.send(slow_peripherals.mtip_int);
280 clint_msip_int.send(slow_peripherals.msip_int);
281 clint_mtime_value<=slow_peripherals.mtime;
283 rule connect_msip_mtip_from_clint;
284 core.clint_msip(clint_msip_int.read);
285 core.clint_mtip(clint_mtip_int.read);
286 core.clint_mtime(clint_mtime_value);
290 Reg#(Tuple2#(Bool,Bool)) plic_interrupt_note <-
291 mkSyncRegToCC(tuple2(False,False),
292 slow_clock,slow_reset);
293 rule synchronize_interrupts;
294 let note <- slow_peripherals.intrpt_note;
295 plic_interrupt_note<=note;
297 rule rl_send_external_interrupt_to_csr;
298 core.set_external_interrupt(plic_interrupt_note);
303 interface proc_ifc = vme.proc_ifc;
304 interface proc_dbus = vme.proc_dbus;
306 method Action boot_sequence(Bit#(1) bootseq) =
307 core.boot_sequence(bootseq);
309 interface sdram_out=sdram.ifc_sdram_out;
312 interface master=fabric.v_to_slaves
313 [fromInteger(valueOf(Sdram_slave_num))];
315 interface slow_ios = slow_peripherals.slow_ios;
316 interface iocell_side = slow_peripherals.iocell_side;