src/bsv/bsv_lib/soc_template.bsv

   1 /*
   2 Copyright (c) 2013, IIT Madras
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
   6
   7 *  Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
   8 *  Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
   9 *  Neither the name of IIT Madras  nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
  10
  11 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  12 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  13 */
  14 package Soc;
  15         /*====== Package imports === */
  16         import FIFO::*;
  17         import FIFOF::*;
  18         import SpecialFIFOs::*;
  19         import GetPut::*;
  20         import ClientServer::*;
  21         import Vector::*;
  22         import Connectable::*;
  23         import Clocks::*;
  24         /*========================== */
  25         /*=== Project imports === */
  26         import ConcatReg::*;
  27         import AXI4_Types::*;
  28         import AXI4_Fabric::*;
  29         import defined_types::*;
  30         import MemoryMap                 :: *;
  31         import slow_peripherals::*;
  32         `include "defines.bsv"
  33         `include "instance_defines.bsv"
  34 {8}
  35     /*====== AXI4 slave declarations =======*/
  36 {3}
  37     /*====== AXI4 Master declarations =======*/
  38 {4}
  39
  40
  41                 `ifdef DMA
  42                         import DMA                               :: *;
  43                 `endif
  44                 `ifdef BOOTROM
  45                         import BootRom                  ::*;
  46                 `endif
  47                 `ifdef SDRAM
  48                         import sdr_top                   :: *;
  49     `endif
  50                 `ifdef BRAM
  51                         import Memory_AXI4      ::*;
  52                 `endif
  53                 `ifdef TCMemory
  54                         import TCM::*;
  55                 `endif
  56                 `ifdef Debug
  57                         import jtagdtm::*;
  58                         import DebugModule::*;
  59                 `else
  60                         import core::*;
  61                 `endif
  62 `ifdef  VME
  63                         import vme_top ::*;
  64 `endif
  65
  66 `ifdef VME
  67                         import vme_master::*;
  68 `endif
  69 `ifdef FlexBus
  70             import FlexBus_Types::*;
  71 `endif
  72 {0}
  73
  74         /*========================= */
  75         interface Ifc_Soc;
  76                 interface SP_ios slow_ios;
  77                 (*always_ready,always_enabled*)
  78                 method Action boot_sequence(Bit#(1) bootseq);
  79
  80                   `ifdef SDRAM
  81                         (*always_ready*) interface Ifc_sdram_out sdram_out;
  82                 `endif
  83       `ifdef DDR
  84         (*prefix="M_AXI"*) interface AXI4_Master_IFC#(`PADDR, `Reg_width, `USERSPACE) master;
  85       `endif
  86                 `ifdef HYPER
  87                         (*always_ready,always_enabled*)
  88                    interface Ifc_flash ifc_flash;
  89                 `endif
  90         /*=============================================== */
  91            `ifdef VME
  92                         interface Vme_out  proc_ifc;
  93                         interface Data_bus_inf proc_dbus;
  94                 `endif
  95         `ifdef FlexBus
  96             interface FlexBus_Master_IFC flexbus_out;
  97         `endif
  98 {1}
  99         endinterface
 100         (*synthesize*)
 101         module mkSoc #(Bit#(`VADDR) reset_vector, Clock slow_clock, Reset slow_reset, Clock uart_clock,
 102                  Reset uart_reset, Clock clk0, Clock tck, Reset trst
 103                  `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif )(Ifc_Soc);
 104                 Clock core_clock <-exposeCurrentClock; // slow peripheral clock
 105                 Reset core_reset <-exposeCurrentReset; // slow peripheral reset
 106 {2}
 107       `ifdef Debug
 108                         Ifc_DebugModule core<-mkDebugModule(reset_vector);
 109                 `else
 110                         Ifc_core_AXI4 core <-mkcore_AXI4(reset_vector);
 111                 `endif
 112                 `ifdef BOOTROM
 113                         BootRom_IFC bootrom <-mkBootRom;
 114                 `endif
 115                 `ifdef SDRAM
 116                         Ifc_sdr_slave                   sdram                           <- mksdr_axi4_slave(clk0);
 117                 `endif
 118     `ifdef BRAM
 119                         Memory_IFC#(`SDRAMMemBase,`Addr_space) main_memory <- mkMemory("code.mem.MSB","code.mem.LSB","MainMEM");
 120                 `endif
 121                 `ifdef TCMemory
 122                         Ifc_TCM                                 tcm                             <- mkTCM;
 123                 `endif
 124                 `ifdef DMA
 125                         DmaC#(7,`NUM_DMACHANNELS)                               dma                             <- mkDMA();
 126                 `endif
 127                         `ifdef VME
 128                         Ifc_vme_top             vme             <-mkvme_top();
 129                         `endif
 130         `ifdef FlexBus
 131             AXI4_Slave_to_FlexBus_Master_Xactor_IFC #(32, 64,0)
 132                                             flexbus <- mkAXI4_Slave_to_FlexBus_Master_Xactor;
 133         `endif
 134                 Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals(core_clock, core_reset, uart_clock,
 135           uart_reset, clocked_by slow_clock , reset_by slow_reset
 136           `ifdef PWM_AXI4Lite , ext_pwm_clock `endif );
 137
 138         // Fabric
 139         AXI4_Fabric_IFC #(Num_Masters, Num_Slaves, `PADDR, `Reg_width,`USERSPACE)
 140                                 fabric <- mkAXI4_Fabric(fn_addr_to_slave_num);
 141
 142         // Connect traffic generators to fabric
 143         mkConnection (core.dmem_master, fabric.v_from_masters [fromInteger(valueOf(Dmem_master_num))]);
 144         mkConnection (core.imem_master, fabric.v_from_masters [fromInteger(valueOf(Imem_master_num))]);
 145                 `ifdef Debug
 146                         mkConnection (core.debug_master, fabric.v_from_masters [fromInteger(valueOf(Debug_master_num))]);
 147                 `endif
 148                 `ifdef DMA
 149          mkConnection (dma.mmu, fabric.v_from_masters[fromInteger(valueOf(DMA_master_num))]);
 150                 `endif
 151
 152
 153                 // Connect fabric to memory slaves
 154                         `ifdef Debug
 155                                 mkConnection (fabric.v_to_slaves [fromInteger(valueOf(Debug_slave_num))],core.debug_slave);
 156                         `endif
 157                         `ifdef SDRAM
 158                                 mkConnection (fabric.v_to_slaves [fromInteger(valueOf(Sdram_slave_num))],       sdram.axi4_slave_sdram); //
 159                         mkConnection (fabric.v_to_slaves [fromInteger(valueOf(Sdram_cfg_slave_num))],   sdram.axi4_slave_cntrl_reg); //
 160       `endif
 161       `ifdef BRAM
 162                                 mkConnection(fabric.v_to_slaves[fromInteger(valueOf(Sdram_slave_num))],main_memory.axi_slave);
 163                         `endif
 164                         `ifdef BOOTROM
 165                                 mkConnection (fabric.v_to_slaves [fromInteger(valueOf(BootRom_slave_num))],bootrom.axi_slave);
 166                         `endif
 167                         `ifdef DMA
 168                         mkConnection (fabric.v_to_slaves [fromInteger(valueOf(Dma_slave_num))], dma.cfg); //DMA slave
 169                         `endif
 170                         `ifdef TCMemory
 171                                 mkConnection (fabric.v_to_slaves [fromInteger(valueOf(TCM_slave_num))],tcm.axi_slave);
 172                         `endif
 173                         mkConnection(fabric.v_to_slaves [fromInteger(valueOf(SlowPeripheral_slave_num))],slow_peripherals.axi_slave);
 174                         `ifdef VME
 175                                 mkConnection (fabric.v_to_slaves[fromInteger(valueOf(VME_slave_num))],vme.slave_axi_vme);
 176                         `endif
 177                         `ifdef FlexBus
 178                                 mkConnection (fabric.v_to_slaves[fromInteger(valueOf(FlexBus_slave_num))],flexbus.axi_side);
 179                         `endif
 180
 181 // fabric connections
 182 {5}
 183
 184                         `ifdef DMA
 185                         //rule to connect all interrupt lines to the DMA
 186                         //All the interrupt lines to DMA are active HIGH. For peripherals that are not connected, or those which do not
 187                         //generate an interrupt (like TCM), drive a constant 1 on the corresponding interrupt line.
 188                                 `ifdef I2C1 SyncBitIfc#(Bit#(1)) i2c1_interrupt <-mkSyncBitToCC(slow_clock,slow_reset); `endif
 189                                 `ifdef I2C0 SyncBitIfc#(Bit#(1)) i2c0_interrupt <-mkSyncBitToCC(slow_clock,slow_reset); `endif
 190                                 `ifdef QSPI1 SyncBitIfc#(Bit#(1)) qspi1_interrupt <-mkSyncBitToCC(slow_clock,slow_reset); `endif
 191                                 `ifdef QSPI0 SyncBitIfc#(Bit#(1)) qspi0_interrupt <-mkSyncBitToCC(slow_clock,slow_reset); `endif
 192                                 `ifdef UART0 SyncBitIfc#(Bit#(1)) uart0_interrupt <-mkSyncBitToCC(uart_clock,uart_reset); `endif
 193                                 rule synchronize_i2c_interrupts;
 194                                         `ifdef I2C1 i2c1_interrupt.send(slow_peripherals.i2c1_isint); `endif
 195                                         `ifdef I2C0 i2c0_interrupt.send(slow_peripherals.i2c0_isint); `endif
 196                                 endrule
 197                                 rule synchronize_qspi_interrupts;
 198                                         `ifdef QSPI0 qspi0_interrupt.send(slow_peripherals.qspi0_isint); `endif
 199                                         `ifdef QSPI1 qspi1_interrupt.send(slow_peripherals.qspi1_isint); `endif
 200                                 endrule
 201                                 rule synchronize_uart0_interrupt;
 202                                         `ifdef UART0 uart0_interrupt.send(slow_peripherals.uart0_intr); `endif
 203                                 endrule
 204                                 rule rl_connect_interrupt_to_DMA;
 205                                         Bit#(12) lv_interrupt_to_DMA= {{'d-1,
 206                                                                                                                         `ifdef I2C1 i2c1_interrupt.read `else 1'b1 `endif ,
 207                                                                                                                         `ifdef I2C0 i2c0_interrupt.read `else 1'b1 `endif ,
 208                                                                                                                         `ifdef QSPI1 qspi1_interrupt.read `else 1'b1 `endif ,
 209                                                                                                                         1'b1,
 210                                                                                                                         `ifdef QSPI0 qspi0_interrupt.read `else 1'b1 `endif ,
 211                                                                                                                         1'b1,1'b0,
 212                                                                                                                         `ifdef UART0 uart0_interrupt.read `else 1'b1 `endif }};
 213                                         dma.interrupt_from_peripherals(lv_interrupt_to_DMA);
 214                                 endrule
 215 {7}
 216                         `endif
 217
 218
 219                 /*======= Synchornization between the JTAG and the Debug Module ========= */
 220                 `ifdef Debug
 221                         SyncFIFOIfc#(Bit#(40)) sync_request_to_dm <-mkSyncFIFOToCC(1,tck,trst);
 222                         SyncFIFOIfc#(Bit#(34)) sync_response_from_dm <-mkSyncFIFOFromCC(1,tck);
 223                         rule connect_tap_request_to_syncfifo;
 224                                 let x<-tap.request_to_dm;
 225                                 sync_request_to_dm.enq(x);
 226                         endrule
 227                         rule read_synced_request_to_dm;
 228                                 sync_request_to_dm.deq;
 229                                 core.request_from_dtm(sync_request_to_dm.first);
 230                         endrule
 231
 232                         rule connect_debug_response_to_syncfifo;
 233                                 let x<-core.response_to_dtm;
 234                                 sync_response_from_dm.enq(x);
 235                         endrule
 236                         rule read_synced_response_from_dm;
 237                                 sync_response_from_dm.deq;
 238                                 tap.response_from_dm(sync_response_from_dm.first);
 239                         endrule
 240                 `endif
 241                 /*======================================================================= */
 242
 243         `ifdef FlexBus
 244             //rule drive_flexbus_inputs;
 245                //flexbus.flexbus_side.m_TAn(1'b1);
 246                //flexbus.flexbus_side.m_din(32'haaaaaaaa);
 247             //endrule
 248          `endif
 249
 250                 `ifdef CLINT
 251                         SyncBitIfc#(Bit#(1)) clint_mtip_int <-mkSyncBitToCC(slow_clock,slow_reset);
 252                         SyncBitIfc#(Bit#(1)) clint_msip_int <-mkSyncBitToCC(slow_clock,slow_reset);
 253                         Reg#(Bit#(`Reg_width)) clint_mtime_value <-mkSyncRegToCC(0,slow_clock,slow_reset);
 254                         rule synchronize_clint_data;
 255                                 clint_mtip_int.send(slow_peripherals.mtip_int);
 256                                 clint_msip_int.send(slow_peripherals.msip_int);
 257                                 clint_mtime_value<=slow_peripherals.mtime;
 258                         endrule
 259                         rule connect_msip_mtip_from_clint;
 260                                 core.clint_msip(clint_msip_int.read);
 261                                 core.clint_mtip(clint_mtip_int.read);
 262             core.clint_mtime(clint_mtime_value);
 263                         endrule
 264                 `endif
 265                 `ifdef PLIC
 266                         Reg#(Tuple2#(Bool,Bool)) plic_interrupt_note <-mkSyncRegToCC(tuple2(False,False),slow_clock,slow_reset);
 267                         rule synchronize_interrupts;
 268                                 let note <- slow_peripherals.intrpt_note;
 269                                 plic_interrupt_note<=note;
 270                         endrule
 271          rule rl_send_external_interrupt_to_csr;
 272                                 core.set_external_interrupt(plic_interrupt_note);
 273                         endrule
 274                 `endif
 275
 276                 `ifdef VME
 277                         interface  proc_ifc = vme.proc_ifc;
 278                         interface   proc_dbus = vme.proc_dbus;
 279                 `endif
 280                 `ifdef FlexBus
 281             interface flexbus_out = flexbus.flexbus_side;
 282                 `endif
 283       method Action boot_sequence(Bit#(1) bootseq) = core.boot_sequence(bootseq);
 284                 `ifdef SDRAM
 285                         interface sdram_out=sdram.ifc_sdram_out;
 286                 `endif
 287     `ifdef DDR
 288       interface master=fabric.v_to_slaves[fromInteger(valueOf(Sdram_slave_num))];
 289     `endif
 290                 interface slow_ios=slow_peripherals.slow_ios;
 291 {6}
 292         endmodule
 293 endpackage