src/bsv/bsv_lib/soc_template.bsv

   1 /*
   2 Copyright (c) 2013, IIT Madras
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without
   6 modification, are permitted provided that the following conditions
   7 are met:
   8
   9 *  Redistributions of source code must retain the above copyright notice,
  10    this list of conditions and the following disclaimer.
  11 *  Redistributions in binary form must reproduce the above copyright
  12    notice, this list of conditions and the following disclaimer in the
  13    documentation and/or other materials provided with the distribution.
  14 *  Neither the name of IIT Madras  nor the names of its contributors
  15    may be used to endorse or promote products derived from this software
  16    without specific prior written permission.
  17
  18 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  19 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  20 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  21 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  22 HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  23 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
  24 TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  25 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  26 LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  27 NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  28 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29 -------------------------------------------------------------------
  30 */
  31 package Soc;
  32     /*====== Package imports === */
  33     import FIFO::*;
  34     import FIFOF::*;
  35     import SpecialFIFOs::*;
  36     import GetPut::*;
  37     import ClientServer::*;
  38     import Vector::*;
  39     import Connectable::*;
  40     import Clocks::*;
  41     /*========================== */
  42     /*=== Project imports === */
  43     import ConcatReg::*;
  44     import AXI4_Types::*;
  45     import AXI4_Fabric::*;
  46     import defined_types::*;
  47     import MemoryMap             :: *;
  48     import slow_peripherals::*;
  49     `include "defines.bsv"
  50     `include "instance_defines.bsv"
  51 {8}
  52     /*====== AXI4 slave declarations =======*/
  53 {3}
  54     /*====== AXI4 Master declarations =======*/
  55 {4}
  56
  57
  58     `ifdef DMA
  59         import DMA                               :: *;
  60     `endif
  61     `ifdef BOOTROM
  62         import BootRom                  ::*;
  63     `endif
  64     `ifdef SDRAM
  65         import sdr_top                   :: *;
  66     `endif
  67     `ifdef BRAM
  68         import Memory_AXI4      ::*;
  69     `endif
  70     `ifdef TCMemory
  71         import TCM::*;
  72     `endif
  73     `ifdef Debug
  74         import DebugModule::*;
  75     `else
  76         import core::*;
  77     `endif
  78     `ifdef  VME
  79         import vme_top ::*;
  80     `endif
  81
  82     `ifdef VME
  83         import vme_master::*;
  84     `endif
  85     `ifdef FlexBus
  86         import FlexBus_Types::*;
  87     `endif
  88 {0}
  89
  90     /*========================= */
  91     interface Ifc_Soc;
  92         interface SP_ios slow_ios;
  93         (*always_ready,always_enabled*)
  94         method Action boot_sequence(Bit#(1) bootseq);
  95
  96         `ifdef SDRAM
  97             (*always_ready*) interface Ifc_sdram_out sdram_out;
  98         `endif
  99         ifdef DDR
 100             (*prefix="M_AXI"*) interface
 101                    AXI4_Master_IFC#(`PADDR, `Reg_width, `USERSPACE) master;
 102         `endif
 103         `ifdef HYPER
 104              (*always_ready,always_enabled*)
 105              interface Ifc_flash ifc_flash;
 106         `endif
 107         /*=============================================== */
 108         `ifdef VME
 109              interface Vme_out  proc_ifc;
 110              interface Data_bus_inf proc_dbus;
 111         `endif
 112 {1}
 113     endinterface
 114
 115     (*synthesize*)
 116     module mkSoc #(Bit#(`VADDR) reset_vector,
 117                  Clock slow_clock, Reset slow_reset, Clock uart_clock,
 118                  Reset uart_reset, Clock clk0, Clock tck, Reset trst
 119                  `ifdef PWM_AXI4Lite ,Clock ext_pwm_clock `endif )(Ifc_Soc);
 120         Clock core_clock <-exposeCurrentClock; // slow peripheral clock
 121         Reset core_reset <-exposeCurrentReset; // slow peripheral reset
 122 {2}
 123         `ifdef Debug
 124             Ifc_DebugModule core<-mkDebugModule(reset_vector);
 125         `else
 126             Ifc_core_AXI4 core <-mkcore_AXI4(reset_vector);
 127         `endif
 128         `ifdef BOOTROM
 129             BootRom_IFC bootrom <-mkBootRom;
 130         `endif
 131         `ifdef SDRAM
 132             Ifc_sdr_slave sdram<- mksdr_axi4_slave(clk0);
 133         `endif
 134         `ifdef BRAM
 135             Memory_IFC#(`SDRAMMemBase,`Addr_space)main_memory <-
 136                         mkMemory("code.mem.MSB","code.mem.LSB","MainMEM");
 137         `endif
 138         `ifdef TCMemory
 139             Ifc_TCM                                     tcm                             <- mkTCM;
 140         `endif
 141         `ifdef DMA
 142             DmaC#(7,`NUM_DMACHANNELS) dma       <- mkDMA();
 143         `endif
 144             `ifdef VME
 145             Ifc_vme_top             vme             <-mkvme_top();
 146             `endif
 147         Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals(
 148                           core_clock, core_reset, uart_clock,
 149                           uart_reset, clocked_by slow_clock ,
 150                           reset_by slow_reset
 151                           `ifdef PWM_AXI4Lite , ext_pwm_clock `endif );
 152
 153         // Fabric
 154         AXI4_Fabric_IFC #(Num_Masters, Num_Slaves,
 155                           `PADDR, `Reg_width,`USERSPACE)
 156                         fabric <- mkAXI4_Fabric(fn_addr_to_slave_num);
 157
 158         // Connect traffic generators to fabric
 159         mkConnection (core.dmem_master,fabric.v_from_masters
 160                               [fromInteger(valueOf(Dmem_master_num))]);
 161         mkConnection (core.imem_master, fabric.v_from_masters
 162                               [fromInteger(valueOf(Imem_master_num))]);
 163         `ifdef Debug
 164             mkConnection (core.debug_master, fabric.v_from_masters
 165                               [fromInteger(valueOf(Debug_master_num))]);
 166         `endif
 167         `ifdef DMA
 168          mkConnection (dma.mmu, fabric.v_from_masters
 169                               [fromInteger(valueOf(DMA_master_num))]);
 170         `endif
 171
 172
 173         // Connect fabric to memory slaves
 174             `ifdef Debug
 175                 mkConnection (fabric.v_to_slaves
 176                               [fromInteger(valueOf(Debug_slave_num))],
 177                               core.debug_slave);
 178             `endif
 179             `ifdef SDRAM
 180                 mkConnection (fabric.v_to_slaves
 181                               [fromInteger(valueOf(Sdram_slave_num))],
 182                               sdram.axi4_slave_sdram); //
 183             mkConnection (fabric.v_to_slaves
 184                               [fromInteger(valueOf(Sdram_cfg_slave_num))],
 185                               sdram.axi4_slave_cntrl_reg); //
 186       `endif
 187       `ifdef BRAM
 188                 mkConnection(fabric.v_to_slaves
 189                               [fromInteger(valueOf(Sdram_slave_num))],
 190                               main_memory.axi_slave);
 191             `endif
 192             `ifdef BOOTROM
 193                 mkConnection (fabric.v_to_slaves
 194                               [fromInteger(valueOf(BootRom_slave_num))],
 195                               bootrom.axi_slave);
 196             `endif
 197             `ifdef DMA
 198             mkConnection (fabric.v_to_slaves
 199                               [fromInteger(valueOf(Dma_slave_num))],
 200                               dma.cfg); //DMA slave
 201             `endif
 202             `ifdef TCMemory
 203                 mkConnection (fabric.v_to_slaves
 204                               [fromInteger(valueOf(TCM_slave_num))],
 205                               tcm.axi_slave);
 206             `endif
 207             mkConnection(fabric.v_to_slaves
 208                               [fromInteger(valueOf(SlowPeripheral_slave_num))],
 209                               slow_peripherals.axi_slave);
 210             `ifdef VME
 211                 mkConnection (fabric.v_to_slaves
 212                               [fromInteger(valueOf(VME_slave_num))],
 213                               vme.slave_axi_vme);
 214             `endif
 215
 216             // fabric connections
 217 {5}
 218
 219             `ifdef DMA
 220             // rule to connect all interrupt lines to the DMA
 221             // All the interrupt lines to DMA are active
 222             // HIGH. For peripherals that are not connected,
 223             // or those which do not
 224             // generate an interrupt (like TCM), drive a constant 1
 225             // on the corresponding interrupt line.
 226 {7}
 227             `endif
 228
 229
 230         /*==== Synchornization between the JTAG and the Debug Module ===== */
 231         `ifdef Debug
 232             SyncFIFOIfc#(Bit#(40)) sync_request_to_dm <-
 233                                         mkSyncFIFOToCC(1,tck,trst);
 234             SyncFIFOIfc#(Bit#(34)) sync_response_from_dm <-
 235                                         mkSyncFIFOFromCC(1,tck);
 236             rule connect_tap_request_to_syncfifo;
 237                 let x<-tap.request_to_dm;
 238                 sync_request_to_dm.enq(x);
 239             endrule
 240             rule read_synced_request_to_dm;
 241                 sync_request_to_dm.deq;
 242                 core.request_from_dtm(sync_request_to_dm.first);
 243             endrule
 244
 245             rule connect_debug_response_to_syncfifo;
 246                 let x<-core.response_to_dtm;
 247                 sync_response_from_dm.enq(x);
 248             endrule
 249             rule read_synced_response_from_dm;
 250                 sync_response_from_dm.deq;
 251                 tap.response_from_dm(sync_response_from_dm.first);
 252             endrule
 253         `endif
 254         /*============================================================ */
 255
 256         `ifdef FlexBus
 257             //rule drive_flexbus_inputs;
 258                //flexbus.flexbus_side.m_TAn(1'b1);
 259                //flexbus.flexbus_side.m_din(32'haaaaaaaa);
 260             //endrule
 261          `endif
 262
 263         `ifdef CLINT
 264             SyncBitIfc#(Bit#(1)) clint_mtip_int <-
 265                                         mkSyncBitToCC(slow_clock,slow_reset);
 266             SyncBitIfc#(Bit#(1)) clint_msip_int <-
 267                                         mkSyncBitToCC(slow_clock,slow_reset);
 268             Reg#(Bit#(`Reg_width)) clint_mtime_value <-
 269                                         mkSyncRegToCC(0,slow_clock,slow_reset);
 270             rule synchronize_clint_data;
 271                 clint_mtip_int.send(slow_peripherals.mtip_int);
 272                 clint_msip_int.send(slow_peripherals.msip_int);
 273                 clint_mtime_value<=slow_peripherals.mtime;
 274             endrule
 275             rule connect_msip_mtip_from_clint;
 276                 core.clint_msip(clint_msip_int.read);
 277                 core.clint_mtip(clint_mtip_int.read);
 278             core.clint_mtime(clint_mtime_value);
 279             endrule
 280         `endif
 281         `ifdef PLIC
 282             Reg#(Tuple2#(Bool,Bool)) plic_interrupt_note <-
 283                                         mkSyncRegToCC(tuple2(False,False),
 284                                                       slow_clock,slow_reset);
 285             rule synchronize_interrupts;
 286                 let note <- slow_peripherals.intrpt_note;
 287                 plic_interrupt_note<=note;
 288             endrule
 289             rule rl_send_external_interrupt_to_csr;
 290                 core.set_external_interrupt(plic_interrupt_note);
 291             endrule
 292         `endif
 293
 294         `ifdef VME
 295             interface  proc_ifc = vme.proc_ifc;
 296             interface   proc_dbus = vme.proc_dbus;
 297         `endif
 298          method Action boot_sequence(Bit#(1) bootseq) =
 299                             core.boot_sequence(bootseq);
 300         `ifdef SDRAM
 301             interface sdram_out=sdram.ifc_sdram_out;
 302         `endif
 303         `ifdef DDR
 304           interface master=fabric.v_to_slaves
 305                                 [fromInteger(valueOf(Sdram_slave_num))];
 306         `endif
 307         interface slow_ios=slow_peripherals.slow_ios;
 308 {6}
 309     endmodule
 310 endpackage