fix sdmmc interface
[pinmux.git] / src / bsv / interface_decl.py
1 import os.path
2
3 try:
4 from UserDict import UserDict
5 except ImportError:
6 from collections import UserDict
7
8 from bsv.wire_def import generic_io # special case
9 from bsv.wire_def import muxwire # special case
10 from ifacebase import InterfacesBase
11 from bsv.peripheral_gen import PeripheralIface
12 from bsv.peripheral_gen import PeripheralInterfaces
13
14
15 class Pin(object):
16 """ pin interface declaration.
17 * name is the name of the pin
18 * ready, enabled and io all create a (* .... *) prefix
19 * action changes it to an "in" if true
20 """
21
22 def __init__(self, name,
23 name_=None,
24 idx=None,
25 ready=True,
26 enabled=True,
27 io=False,
28 action=False,
29 bitspec=None,
30 outenmode=False):
31 self.name = name
32 self.name_ = name_
33 self.idx = idx
34 self.ready = ready
35 self.enabled = enabled
36 self.io = io
37 self.action = action
38 self.bitspec = bitspec if bitspec else 'Bit#(1)'
39 self.outenmode = outenmode
40
41 # bsv will look like this (method declaration):
42 """
43 (*always_ready,always_enabled*) method Bit#(1) io0_cell_outen;
44 (*always_ready,always_enabled,result="io"*) method
45 Action io0_inputval (Bit#(1) in);
46 """
47
48 def ifacepfmt(self, fmtfn):
49 res = ' '
50 status = []
51 res += "interface "
52 name = fmtfn(self.name_)
53 if self.action:
54 res += "Put"
55 else:
56 res += "Get"
57 res += "#(%s) %s;" % (self.bitspec, name)
58 return res
59
60 def ifacefmt(self, fmtfn):
61 res = ' '
62 status = []
63 if self.ready:
64 status.append('always_ready')
65 if self.enabled:
66 status.append('always_enabled')
67 if self.io:
68 status.append('result="io"')
69 if status:
70 res += '(*'
71 res += ','.join(status)
72 res += '*)'
73 res += " method "
74 if self.io:
75 res += "\n "
76 name = fmtfn(self.name)
77 if self.action:
78 res += " Action "
79 res += name
80 res += ' (%s in)' % self.bitspec
81 else:
82 res += " %s " % self.bitspec
83 res += name
84 res += ";"
85 return res
86
87 def ifacedef(self, fmtoutfn, fmtinfn, fmtdecfn):
88 res = ' method '
89 if self.action:
90 fmtname = fmtinfn(self.name)
91 res += "Action "
92 res += fmtdecfn(self.name)
93 res += '(%s in);\n' % self.bitspec
94 res += ' %s<=in;\n' % fmtname
95 res += ' endmethod'
96 else:
97 fmtname = fmtoutfn(self.name)
98 res += "%s=%s;" % (self.name, fmtname)
99 return res
100 # sample bsv method definition :
101 """
102 method Action cell0_mux(Bit#(2) in);
103 wrcell0_mux<=in;
104 endmethod
105 """
106
107 # sample bsv wire (wire definiton):
108 """
109 Wire#(Bit#(2)) wrcell0_mux<-mkDWire(0);
110 """
111
112 def wirefmt(self, fmtoutfn, fmtinfn, fmtdecfn):
113 res = ' Wire#(%s) ' % self.bitspec
114 if self.action:
115 res += '%s' % fmtinfn(self.name)
116 else:
117 res += '%s' % fmtoutfn(self.name)
118 res += "<-mkDWire(0);"
119 return res
120
121 def ifacedef2(self, fmtoutfn, fmtinfn, fmtdecfn):
122 if self.action:
123 fmtname = fmtinfn(self.name)
124 res = " interface %s = interface Put\n" % self.name_
125 res += ' method '
126 res += "Action put"
127 #res += fmtdecfn(self.name)
128 res += '(%s in);\n' % self.bitspec
129 res += ' %s<=in;\n' % fmtname
130 res += ' endmethod\n'
131 res += ' endinterface;'
132 else:
133 fmtname = fmtoutfn(self.name)
134 res = " interface %s = interface Get\n" % self.name_
135 res += ' method ActionValue#'
136 res += '(%s) get;\n' % self.bitspec
137 res += " return %s;\n" % (fmtname)
138 res += ' endmethod\n'
139 res += ' endinterface;'
140 return res
141
142 def ifacedef3(self, idx, fmtoutfn, fmtinfn, fmtdecfn):
143 if self.action:
144 fmtname = fmtinfn(self.name)
145 if self.name.endswith('outen'):
146 name = "tputen"
147 else:
148 name = "tput"
149 res = " %s <= in[%d];" % (fmtname, idx)
150 else:
151 fmtname = fmtoutfn(self.name)
152 res = " tget[%d] = %s;" % (idx, fmtname)
153 name = 'tget'
154 return (name, res)
155
156
157 class InterfaceFmt(object):
158
159 def ifacepfmtdecpin(self, pin):
160 return pin.ifacepfmt(self.ifacepfmtdecfn)
161
162 def ifacepfmtdecfn(self, name):
163 return name
164
165 def ifacefmtoutfn(self, name):
166 return "wr%s" % name # like wruart
167
168 def ifacefmtdecfn2(self, name):
169 return name # like: uart
170
171 def ifacefmtdecfn3(self, name):
172 """ HACK! """
173 return "%s_outen" % name # like uart_outen
174
175 def ifacefmtinfn(self, name):
176 return "wr%s" % name
177
178 def ifacedef2pin(self, pin):
179 decfn = self.ifacefmtdecfn2
180 outfn = self.ifacefmtoutfn
181 # print pin, pin.outenmode
182 if pin.outenmode:
183 decfn = self.ifacefmtdecfn3
184 outfn = self.ifacefmtoutenfn
185 return pin.ifacedef2(outfn, self.ifacefmtinfn,
186 decfn)
187
188 def vectorifacedef2(self, pins, count, names, bitfmt, *args):
189 tput = []
190 tget = []
191 tputen = []
192 if len(pins) == 0:
193 return ''
194 # XXX HACK! assume in, out and inout, create set of indices
195 # that are repeated three times.
196 plens = []
197 # ARG even worse hack for LCD *sigh*...
198 if names[1] is None and names[2] is None:
199 plens = range(len(pins))
200 else:
201 for i in range(0, len(pins), 3):
202 plens += [i / 3, i / 3, i / 3]
203 for (typ, txt) in map(self.ifacedef3pin, plens, pins):
204 if typ == 'tput':
205 tput.append(txt)
206 elif typ == 'tget':
207 tget.append(txt)
208 elif typ == 'tputen':
209 tputen.append(txt)
210 tput = '\n'.join(tput).format(*args)
211 tget = '\n'.join(tget).format(*args)
212 tputen = '\n'.join(tputen).format(*args)
213 bitfmt = bitfmt.format(count)
214 template = ["""\
215 interface {3} = interface Put#({0})
216 method Action put({2} in);
217 {1}
218 endmethod
219 endinterface;
220 """,
221 """\
222 interface {3} = interface Put#({0})
223 method Action put({2} in);
224 {1}
225 endmethod
226 endinterface;
227 """,
228 """\
229 interface {3} = interface Get#({0})
230 method ActionValue#({2}) get;
231 {2} tget;
232 {1}
233 return tget;
234 endmethod
235 endinterface;
236 """]
237 res = ''
238 tlist = [tput, tputen, tget]
239 for i, n in enumerate(names):
240 if n:
241 res += template[i].format(count, tlist[i], bitfmt, n)
242 return '\n' + res + '\n'
243
244
245 class Interface(PeripheralIface, InterfaceFmt):
246 """ create an interface from a list of pinspecs.
247 each pinspec is a dictionary, see Pin class arguments
248 single indicates that there is only one of these, and
249 so the name must *not* be extended numerically (see pname)
250 """
251 # sample interface object:
252 """
253 twiinterface_decl = Interface('twi',
254 [{'name': 'sda', 'outen': True},
255 {'name': 'scl', 'outen': True},
256 ])
257 """
258
259 def __init__(self, ifacename, pinspecs, ganged=None, single=False):
260 PeripheralIface.__init__(self, ifacename)
261 InterfaceFmt.__init__(self)
262 self.ifacename = ifacename
263 self.ganged = ganged or {}
264 self.pins = [] # a list of instances of class Pin
265 self.pinspecs = pinspecs # a list of dictionary
266 self.single = single
267
268 for idx, p in enumerate(pinspecs):
269 _p = {}
270 _p.update(p)
271 if 'type' in _p:
272 del _p['type']
273 if p.get('outen') is True: # special case, generate 3 pins
274 del _p['outen']
275 for psuffix in ['out', 'outen', 'in']:
276 # changing the name (like sda) to (twi_sda_out)
277 _p['name_'] = "%s_%s" % (p['name'], psuffix)
278 _p['name'] = "%s_%s" % (self.pname(p['name']), psuffix)
279 _p['action'] = psuffix != 'in'
280 _p['idx'] = idx
281 self.pins.append(Pin(**_p))
282 # will look like {'name': 'twi_sda_out', 'action': True}
283 # {'name': 'twi_sda_outen', 'action': True}
284 #{'name': 'twi_sda_in', 'action': False}
285 # NOTice - outen key is removed
286 else:
287 name = p['name']
288 if name.isdigit(): # HACK! deals with EINT case
289 name = self.pname(name)
290 _p['name_'] = name
291 _p['idx'] = idx
292 _p['name'] = self.pname(p['name'])
293 self.pins.append(Pin(**_p))
294
295 # sample interface object:
296 """
297 uartinterface_decl = Interface('uart',
298 [{'name': 'rx'},
299 {'name': 'tx', 'action': True},
300 ])
301 """
302 """
303 getifacetype is called multiple times in actual_pinmux.py
304 x = ifaces.getifacetype(temp), where temp is uart_rx, spi_mosi
305 Purpose is to identify is function : input/output/inout
306 """
307
308 def getifacetype(self, name):
309 for p in self.pinspecs:
310 fname = "%s_%s" % (self.ifacename, p['name'])
311 # print "search", self.ifacename, name, fname
312 if fname == name:
313 if p.get('action'):
314 return 'out'
315 elif p.get('outen'):
316 return 'inout'
317 return 'input'
318 return None
319
320 def iname(self):
321 """ generates the interface spec e.g. flexbus_ale
322 if there is only one flexbus interface, or
323 sd{0}_cmd if there are several. string format
324 function turns this into sd0_cmd, sd1_cmd as
325 appropriate. single mode stops the numerical extension.
326 """
327 if self.single:
328 return self.ifacename
329 return '%s{0}' % self.ifacename
330
331 def pname(self, name):
332 """ generates the interface spec e.g. flexbus_ale
333 if there is only one flexbus interface, or
334 sd{0}_cmd if there are several. string format
335 function turns this into sd0_cmd, sd1_cmd as
336 appropriate. single mode stops the numerical extension.
337 """
338 return "%s_%s" % (self.iname(), name)
339
340 def busfmt(self, *args):
341 """ this function creates a bus "ganging" system based
342 on input from the {interfacename}.txt file.
343 only inout pins that are under the control of the
344 interface may be "ganged" together.
345 """
346 if not self.ganged:
347 return '' # when self.ganged is None
348 # print self.ganged
349 res = []
350 for (k, pnames) in self.ganged.items():
351 name = self.pname('%senable' % k).format(*args)
352 decl = 'Bit#(1) %s = 0;' % name
353 res.append(decl)
354 ganged = []
355 for p in self.pinspecs:
356 if p['name'] not in pnames:
357 continue
358 pname = self.pname(p['name']).format(*args)
359 if p.get('outen') is True:
360 outname = self.ifacefmtoutfn(pname)
361 ganged.append("%s_outen" % outname) # match wirefmt
362
363 gangedfmt = '{%s} = duplicate(%s);'
364 res.append(gangedfmt % (',\n '.join(ganged), name))
365 return '\n'.join(res) + '\n\n'
366
367 def wirefmt(self, *args):
368 res = '\n'.join(map(self.wirefmtpin, self.pins)).format(*args)
369 res += '\n'
370 return '\n' + res
371
372 def ifacepfmt(self, *args):
373 res = '\n'.join(map(self.ifacepfmtdecpin, self.pins)).format(*args)
374 return '\n' + res # pins is a list
375
376 def ifacefmt(self, *args):
377 res = '\n'.join(map(self.ifacefmtdecpin, self.pins)).format(*args)
378 return '\n' + res # pins is a list
379
380 def ifacefmtdecfn(self, name):
381 return name # like: uart
382
383 def wirefmtpin(self, pin):
384 return pin.wirefmt(self.ifacefmtoutfn, self.ifacefmtinfn,
385 self.ifacefmtdecfn2)
386
387 def ifacefmtdecpin(self, pin):
388 return pin.ifacefmt(self.ifacefmtdecfn)
389
390 def ifacefmtpin(self, pin):
391 decfn = self.ifacefmtdecfn2
392 outfn = self.ifacefmtoutfn
393 # print pin, pin.outenmode
394 if pin.outenmode:
395 decfn = self.ifacefmtdecfn3
396 outfn = self.ifacefmtoutenfn
397 return pin.ifacedef(outfn, self.ifacefmtinfn,
398 decfn)
399
400 def ifacedef(self, *args):
401 res = '\n'.join(map(self.ifacefmtpin, self.pins))
402 res = res.format(*args)
403 return '\n' + res + '\n'
404
405 def ifacedef2(self, *args):
406 res = '\n'.join(map(self.ifacedef2pin, self.pins))
407 res = res.format(*args)
408 return '\n' + res + '\n'
409
410
411 class MuxInterface(Interface):
412
413 def wirefmt(self, *args):
414 return muxwire.format(*args)
415
416
417 class IOInterface(Interface):
418
419 def ifacefmtoutenfn(self, name):
420 return "cell{0}_mux_outen"
421
422 def ifacefmtoutfn(self, name):
423 """ for now strip off io{0}_ part """
424 return "cell{0}_mux_out"
425
426 def ifacefmtinfn(self, name):
427 return "cell{0}_mux_in"
428
429 def wirefmt(self, *args):
430 return generic_io.format(*args)
431
432
433 class InterfaceBus(InterfaceFmt):
434
435 def __init__(self, pins, is_inout, namelist, bitspec, filterbus):
436 InterfaceFmt.__init__(self)
437 self.namelist = namelist
438 self.bitspec = bitspec
439 self.fbus = filterbus # filter identifying which are bus pins
440 self.pins_ = pins
441 self.is_inout = is_inout
442 self.buspins = filter(lambda x: x.name_.startswith(self.fbus),
443 self.pins_)
444 self.nonbuspins = filter(lambda x: not x.name_.startswith(self.fbus),
445 self.pins_)
446
447 def get_nonbuspins(self):
448 return self.nonbuspins
449
450 def get_buspins(self):
451 return self.buspins
452
453 def get_n_iopinsdiv(self):
454 return 3 if self.is_inout else 1
455
456 def ifacepfmt(self, *args):
457 pins = self.get_nonbuspins()
458 res = '\n'.join(map(self.ifacepfmtdecpin, pins)).format(*args)
459 res = res.format(*args)
460
461 pins = self.get_buspins()
462 plen = len(pins) / self.get_n_iopinsdiv()
463
464 res += '\n'
465 template = " interface {1}#(%s) {2};\n" % self.bitspec
466 for i, n in enumerate(self.namelist):
467 if not n:
468 continue
469 ftype = 'Get' if i == 2 else "Put"
470 res += template.format(plen, ftype, n)
471
472 return "\n" + res
473
474 def ifacedef2(self, *args):
475 pins = self.get_nonbuspins()
476 res = '\n'.join(map(self.ifacedef2pin, pins))
477 res = res.format(*args)
478
479 pins = self.get_buspins()
480 plen = len(pins) / self.get_n_iopinsdiv()
481 for pin in pins:
482 print "ifbus pins", pin.name_, plen
483 bitspec = self.bitspec.format(plen)
484 return '\n' + res + self.vectorifacedef2(
485 pins, plen, self.namelist, bitspec, *args)
486
487 def ifacedef3pin(self, idx, pin):
488 decfn = self.ifacefmtdecfn2
489 outfn = self.ifacefmtoutfn
490 # print pin, pin.outenmode
491 if pin.outenmode:
492 decfn = self.ifacefmtdecfn3
493 outfn = self.ifacefmtoutenfn
494 return pin.ifacedef3(idx, outfn, self.ifacefmtinfn,
495 decfn)
496
497
498 class InterfaceMultiBus(object):
499
500 def __init__(self, pins):
501 self.multibus_specs = []
502 self.nonbuspins = pins
503 self.nonb = self.add_bus(False, [], '', "xxxxxxxnofilter")
504
505 def add_bus(self, is_inout, namelist, bitspec, filterbus):
506 pins = self.nonbuspins
507 buspins = filter(lambda x: x.name_.startswith(filterbus), pins)
508 nbuspins = filter(lambda x: not x.name_.startswith(filterbus), pins)
509 self.nonbuspins = nbuspins
510 b = InterfaceBus(buspins, is_inout,
511 namelist, bitspec, filterbus)
512 print "add bus", is_inout, namelist, filterbus, \
513 map(lambda x:x.name_, buspins), \
514 map(lambda x:x.name_, nbuspins)
515 self.multibus_specs.append(b)
516 self.multibus_specs[0].pins_ = nbuspins
517 self.multibus_specs[0].nonbuspins = nbuspins
518 #self.nonbuspins = nbuspins
519
520 def ifacepfmt(self, *args):
521 res = ''
522 #res = Interface.ifacepfmt(self, *args)
523 for b in self.multibus_specs:
524 res += b.ifacepfmt(*args)
525 return res
526
527 def ifacedef2(self, *args):
528 res = ''
529 #res = Interface.ifacedef2(self, *args)
530 for b in self.multibus_specs:
531 res += b.ifacedef2(*args)
532 return res
533
534
535 class InterfaceLCD(InterfaceBus, Interface):
536
537 def __init__(self, *args):
538 Interface.__init__(self, *args)
539 InterfaceBus.__init__(self, self.pins, False, ['data_out', None, None],
540 "Bit#({0})", "out")
541
542
543 class InterfaceSDRAM(InterfaceMultiBus, Interface):
544
545 def __init__(self, ifacename, pinspecs, ganged=None, single=False):
546 Interface.__init__(self, ifacename, pinspecs, ganged, single)
547 InterfaceMultiBus.__init__(self, self.pins)
548 self.add_bus(False, ['dqm', None, None],
549 "Bit#({0})", "sdrdqm")
550 self.add_bus(True, ['d_out', 'd_out_en', 'd_in'],
551 "Bit#({0})", "sdrd")
552 self.add_bus(False, ['ad', None, None],
553 "Bit#({0})", "sdrad")
554 self.add_bus(False, ['ba', None, None],
555 "Bit#({0})", "sdrba")
556
557 def ifacedef2(self, *args):
558 return InterfaceMultiBus.ifacedef2(self, *args)
559
560
561 class InterfaceFlexBus(InterfaceMultiBus, Interface):
562
563 def __init__(self, ifacename, pinspecs, ganged=None, single=False):
564 Interface.__init__(self, ifacename, pinspecs, ganged, single)
565 InterfaceMultiBus.__init__(self, self.pins)
566 self.add_bus(True, ['ad_out', 'ad_out_en', 'ad_in'],
567 "Bit#({0})", "ad")
568 self.add_bus(False, ['bwe', None, None],
569 "Bit#({0})", "bwe")
570 self.add_bus(False, ['tsiz', None, None],
571 "Bit#({0})", "tsiz")
572 self.add_bus(False, ['cs', None, None],
573 "Bit#({0})", "cs")
574
575 def ifacedef2(self, *args):
576 return InterfaceMultiBus.ifacedef2(self, *args)
577
578
579 class InterfaceSD(InterfaceMultiBus, Interface):
580
581 def __init__(self, ifacename, pinspecs, ganged=None, single=False):
582 Interface.__init__(self, ifacename, pinspecs, ganged, single)
583 InterfaceMultiBus.__init__(self, self.pins)
584 self.add_bus(True, ['out', 'out_en', 'in'],
585 "Bit#({0})", "d")
586
587 def ifacedef2(self, *args):
588 return InterfaceMultiBus.ifacedef2(self, *args)
589
590 class InterfaceNSPI(InterfaceBus, Interface):
591
592 def __init__(self, *args):
593 Interface.__init__(self, *args)
594 InterfaceBus.__init__(self, self.pins, True,
595 ['io_out', 'io_out_en', 'io_in'],
596 "Bit#({0})", "io")
597
598
599 class InterfaceEINT(Interface):
600 """ uses old-style (non-get/put) for now
601 """
602
603 def ifacepfmt(self, *args):
604 res = '\n'.join(map(self.ifacefmtdecpin, self.pins)).format(*args)
605 return '\n' + res # pins is a list
606
607 def ifacedef2(self, *args):
608 return self.ifacedef(*args)
609
610
611 class InterfaceGPIO(InterfaceBus, Interface):
612 """ note: the busfilter cuts out everything as the entire set of pins
613 is a bus, but it's less code. get_nonbuspins returns empty list.
614 """
615
616 def __init__(self, ifacename, pinspecs, ganged=None, single=False):
617 Interface.__init__(self, ifacename, pinspecs, ganged, single)
618 InterfaceBus.__init__(self, self.pins, True, ['out', 'out_en', 'in'],
619 "Vector#({0},Bit#(1))", ifacename[-1])
620
621
622 class Interfaces(InterfacesBase, PeripheralInterfaces):
623 """ contains a list of interface definitions
624 """
625
626 def __init__(self, pth=None):
627 InterfacesBase.__init__(self, Interface, pth,
628 {'gpio': InterfaceGPIO,
629 'spi': InterfaceNSPI,
630 'mspi': InterfaceNSPI,
631 'lcd': InterfaceLCD,
632 'mmc': InterfaceSD,
633 'fb': InterfaceFlexBus,
634 'sdr': InterfaceSDRAM,
635 'qspi': InterfaceNSPI,
636 'mqspi': InterfaceNSPI,
637 'eint': InterfaceEINT})
638 PeripheralInterfaces.__init__(self)
639
640 def ifacedef(self, f, *args):
641 for (name, count) in self.ifacecount:
642 for i in range(count):
643 f.write(self.data[name].ifacedef(i))
644
645 def ifacedef2(self, f, *args):
646 c = " interface {0} = interface PeripheralSide{1}"
647 for (name, count) in self.ifacecount:
648 for i in range(count):
649 iname = self.data[name].iname().format(i)
650 f.write(c.format(iname, name.upper()))
651 f.write(self.data[name].ifacedef2(i))
652 f.write(" endinterface;\n\n")
653
654 def busfmt(self, f, *args):
655 f.write("import BUtils::*;\n\n")
656 for (name, count) in self.ifacecount:
657 for i in range(count):
658 bf = self.data[name].busfmt(i)
659 f.write(bf)
660
661 def ifacepfmt(self, f, *args):
662 comment = '''
663 // interface declaration between {0} and pinmux
664 (*always_ready,always_enabled*)
665 interface PeripheralSide{0};'''
666 for (name, count) in self.ifacecount:
667 f.write(comment.format(name.upper()))
668 f.write(self.data[name].ifacepfmt(0))
669 f.write("\n endinterface\n")
670
671 def ifacefmt(self, f, *args):
672 comment = '''
673 // interface declaration between %s-{0} and pinmux'''
674 for (name, count) in self.ifacecount:
675 for i in range(count):
676 c = comment % name.upper()
677 f.write(c.format(i))
678 f.write(self.data[name].ifacefmt(i))
679
680 def ifacefmt2(self, f, *args):
681 comment = '''
682 interface PeripheralSide{0} {1};'''
683 for (name, count) in self.ifacecount:
684 for i in range(count):
685 iname = self.data[name].iname().format(i)
686 f.write(comment.format(name.upper(), iname))
687
688 def wirefmt(self, f, *args):
689 comment = '\n // following wires capture signals ' \
690 'to IO CELL if %s-{0} is\n' \
691 ' // allotted to it'
692 for (name, count) in self.ifacecount:
693 for i in range(count):
694 c = comment % name
695 f.write(c.format(i))
696 f.write(self.data[name].wirefmt(i))
697
698
699 # ========= Interface declarations ================ #
700
701 mux_interface = MuxInterface('cell',
702 [{'name': 'mux', 'ready': False, 'enabled': False,
703 'bitspec': '{1}', 'action': True}])
704
705 io_interface = IOInterface(
706 'io',
707 [{'name': 'cell_out', 'enabled': True, },
708 {'name': 'cell_outen', 'enabled': True, 'outenmode': True, },
709 {'name': 'cell_in', 'action': True, 'io': True}, ])
710
711 # == Peripheral Interface definitions == #
712 # these are the interface of the peripherals to the pin mux
713 # Outputs from the peripherals will be inputs to the pinmux
714 # module. Hence the change in direction for most pins
715
716 # ======================================= #
717
718 # basic test
719 if __name__ == '__main__':
720
721 uartinterface_decl = Interface('uart',
722 [{'name': 'rx'},
723 {'name': 'tx', 'action': True},
724 ])
725
726 twiinterface_decl = Interface('twi',
727 [{'name': 'sda', 'outen': True},
728 {'name': 'scl', 'outen': True},
729 ])
730
731 def _pinmunge(p, sep, repl, dedupe=True):
732 """ munges the text so it's easier to compare.
733 splits by separator, strips out blanks, re-joins.
734 """
735 p = p.strip()
736 p = p.split(sep)
737 if dedupe:
738 p = filter(lambda x: x, p) # filter out blanks
739 return repl.join(p)
740
741 def pinmunge(p):
742 """ munges the text so it's easier to compare.
743 """
744 # first join lines by semicolons, strip out returns
745 p = p.split(";")
746 p = map(lambda x: x.replace('\n', ''), p)
747 p = '\n'.join(p)
748 # now split first by brackets, then spaces (deduping on spaces)
749 p = _pinmunge(p, "(", " ( ", False)
750 p = _pinmunge(p, ")", " ) ", False)
751 p = _pinmunge(p, " ", " ")
752 return p
753
754 def zipcmp(l1, l2):
755 l1 = l1.split("\n")
756 l2 = l2.split("\n")
757 for p1, p2 in zip(l1, l2):
758 print (repr(p1))
759 print (repr(p2))
760 print ()
761 assert p1 == p2
762
763 ifaces = Interfaces()
764
765 ifaceuart = ifaces['uart']
766 print (ifaceuart.ifacedef(0))
767 print (uartinterface_decl.ifacedef(0))
768 assert ifaceuart.ifacedef(0) == uartinterface_decl.ifacedef(0)
769
770 ifacetwi = ifaces['twi']
771 print (ifacetwi.ifacedef(0))
772 print (twiinterface_decl.ifacedef(0))
773 assert ifacetwi.ifacedef(0) == twiinterface_decl.ifacedef(0)