4 from UserDict
import UserDict
6 from collections
import UserDict
8 from bsv
.wire_def
import generic_io
# special case
9 from bsv
.wire_def
import muxwire
# special case
13 """ pin interface declaration.
14 * name is the name of the pin
15 * ready, enabled and io all create a (* .... *) prefix
16 * action changes it to an "in" if true
19 def __init__(self
, name
,
27 self
.enabled
= enabled
30 self
.bitspec
= bitspec
if bitspec
else 'Bit#(1)'
32 def ifacefmt(self
, fmtfn
=None):
36 status
.append('always_ready')
38 status
.append('always_enabled')
40 status
.append('result="io"')
43 res
+= ','.join(status
)
48 name
= fmtfn(self
.name
)
52 res
+= ' (%s in)' % self
.bitspec
54 res
+= " %s " % self
.bitspec
59 def ifacedef(self
, fmtoutfn
=None, fmtinfn
=None, fmtdecfn
=None):
62 fmtname
= fmtinfn(self
.name
)
64 res
+= fmtdecfn(self
.name
)
65 res
+= '(%s in);\n' % self
.bitspec
66 res
+= ' %s<=in;\n' % fmtname
69 fmtname
= fmtoutfn(self
.name
)
70 res
+= "%s=%s;" % (self
.name
, fmtname
)
73 def wirefmt(self
, fmtoutfn
=None, fmtinfn
=None, fmtdecfn
=None):
74 res
= ' Wire#(%s) ' % self
.bitspec
76 res
+= '%s' % fmtinfn(self
.name
)
78 res
+= '%s' % fmtoutfn(self
.name
)
79 res
+= "<-mkDWire(0);"
83 class Interface(object):
84 """ create an interface from a list of pinspecs.
85 each pinspec is a dictionary, see Pin class arguments
86 single indicates that there is only one of these, and
87 so the name must *not* be extended numerically (see pname)
90 def __init__(self
, ifacename
, pinspecs
, single
=False):
91 self
.ifacename
= ifacename
93 self
.pinspecs
= pinspecs
98 if p
.get('outen') is True: # special case, generate 3 pins
100 for psuffix
in ['out', 'outen', 'in']:
101 _p
['name'] = "%s_%s" % (self
.pname(p
['name']), psuffix
)
102 _p
['action'] = psuffix
!= 'in'
103 self
.pins
.append(Pin(**_p
))
105 _p
['name'] = self
.pname(p
['name'])
106 self
.pins
.append(Pin(**_p
))
108 def getifacetype(self
, name
):
109 for p
in self
.pinspecs
:
110 fname
= "%s_%s" % (self
.ifacename
, p
['name'])
111 #print "search", self.ifacename, name, fname
120 def pname(self
, name
):
121 """ generates the interface spec e.g. flexbus_ale
122 if there is only one flexbus interface, or
123 sd{0}_cmd if there are several. string format
124 function turns this into sd0_cmd, sd1_cmd as
125 appropriate. single mode stops the numerical extension.
128 return '%s_%s' % (self
.ifacename
, name
)
129 return '%s{0}_%s' % (self
.ifacename
, name
)
131 def wirefmt(self
, *args
):
132 res
= '\n'.join(map(self
.wirefmtpin
, self
.pins
)).format(*args
)
134 for p
in self
.pinspecs
:
135 name
= self
.pname(p
['name']).format(*args
)
136 res
+= " GenericIOType %s_io = GenericIOType{\n" % name
138 if p
.get('outen') is True:
139 outname
= self
.ifacefmtoutfn(name
)
140 params
.append('outputval:%s_out,' % outname
)
141 params
.append('output_en:%s_outen,' % outname
)
142 params
.append('input_en:~%s_outen,' % outname
)
143 elif p
.get('action'):
144 outname
= self
.ifacefmtoutfn(name
)
145 params
.append('outputval:%s,' % outname
)
146 params
.append('output_en:1,')
147 params
.append('input_en:0,')
149 params
.append('outputval:0,')
150 params
.append('output_en:0,')
151 params
.append('input_en:1,')
152 params
+= ['pullup_en:0,', 'pulldown_en:0,',
153 'pushpull_en:0,', 'drivestrength:0,',
156 res
+= ' %s\n' % param
160 def ifacefmt(self
, *args
):
161 res
= '\n'.join(map(self
.ifacefmtdecpin
, self
.pins
)).format(*args
)
164 def ifacefmtdecfn(self
, name
):
167 def ifacefmtdecfn2(self
, name
):
170 def ifacefmtoutfn(self
, name
):
173 def ifacefmtinfn(self
, name
):
176 def wirefmtpin(self
, pin
):
177 return pin
.wirefmt(self
.ifacefmtoutfn
, self
.ifacefmtinfn
,
180 def ifacefmtdecpin(self
, pin
):
181 return pin
.ifacefmt(self
.ifacefmtdecfn
)
183 def ifacefmtpin(self
, pin
):
184 return pin
.ifacedef(self
.ifacefmtoutfn
, self
.ifacefmtinfn
,
187 def ifacedef(self
, *args
):
188 res
= '\n'.join(map(self
.ifacefmtpin
, self
.pins
))
189 res
= res
.format(*args
)
190 return '\n' + res
+ '\n'
193 class MuxInterface(Interface
):
195 def wirefmt(self
, *args
):
196 return muxwire
.format(*args
)
199 class IOInterface(Interface
):
201 def ifacefmtoutfn(self
, name
):
202 """ for now strip off io{0}_ part """
203 return "cell{0}_mux_out"
205 def ifacefmtinfn(self
, name
):
206 return "cell{0}_mux_in"
208 def wirefmt(self
, *args
):
209 return generic_io
.format(*args
)
212 class Interfaces(UserDict
):
213 """ contains a list of interface definitions
216 def __init__(self
, pth
):
219 UserDict
.__init
__(self
, {})
220 ift
= 'interfaces.txt'
222 ift
= os
.path
.join(pth
, ift
)
223 with
open(ift
, 'r') as ifile
:
224 for ln
in ifile
.readlines():
229 spec
= self
.read_spec(pth
, name
)
230 self
.ifaceadd(name
, count
, Interface(name
, spec
, count
== 1))
232 def getifacetype(self
, fname
):
233 # finds the interface type, e.g sd_d0 returns "inout"
234 for iface
in self
.values():
235 typ
= iface
.getifacetype(fname
)
240 def ifaceadd(self
, name
, count
, iface
, at
=None):
242 at
= len(self
.ifacecount
)
243 self
.ifacecount
.insert(at
, (name
, count
))
246 def read_spec(self
, pth
, name
):
248 fname
= '%s.txt' % name
250 ift
= os
.path
.join(pth
, fname
)
251 with
open(ift
, 'r') as sfile
:
252 for ln
in sfile
.readlines():
258 elif ln
[1] == 'inout':
263 def ifacedef(self
, f
, *args
):
264 for (name
, count
) in self
.ifacecount
:
265 for i
in range(count
):
266 f
.write(self
.data
[name
].ifacedef(i
))
268 def ifacefmt(self
, f
, *args
):
270 // interface declaration between %s-{0} and pinmux'''
271 for (name
, count
) in self
.ifacecount
:
272 for i
in range(count
):
273 c
= comment
% name
.upper()
275 f
.write(self
.data
[name
].ifacefmt(i
))
277 def wirefmt(self
, f
, *args
):
278 comment
= '\n // following wires capture signals ' \
279 'to IO CELL if %s-{0} is\n' \
281 for (name
, count
) in self
.ifacecount
:
282 for i
in range(count
):
285 f
.write(self
.data
[name
].wirefmt(i
))
288 # ========= Interface declarations ================ #
290 mux_interface
= MuxInterface('cell', [{'name': 'mux', 'ready': False,
292 'bitspec': '{1}', 'action': True}])
294 io_interface
= IOInterface(
296 [{'name': 'cell', 'enabled': False, 'bitspec': 'GenericIOType'},
297 {'name': 'inputval', 'action': True, 'io': True}, ])
299 # == Peripheral Interface definitions == #
300 # these are the interface of the peripherals to the pin mux
301 # Outputs from the peripherals will be inputs to the pinmux
302 # module. Hence the change in direction for most pins
304 # ======================================= #
307 if __name__
== '__main__':
309 uartinterface_decl
= Interface('uart',
311 {'name': 'tx', 'action': True},
314 twiinterface_decl
= Interface('twi',
315 [{'name': 'sda', 'outen': True},
316 {'name': 'scl', 'outen': True},
319 def _pinmunge(p
, sep
, repl
, dedupe
=True):
320 """ munges the text so it's easier to compare.
321 splits by separator, strips out blanks, re-joins.
326 p
= filter(lambda x
: x
, p
) # filter out blanks
330 """ munges the text so it's easier to compare.
332 # first join lines by semicolons, strip out returns
334 p
= map(lambda x
: x
.replace('\n', ''), p
)
336 # now split first by brackets, then spaces (deduping on spaces)
337 p
= _pinmunge(p
, "(", " ( ", False)
338 p
= _pinmunge(p
, ")", " ) ", False)
339 p
= _pinmunge(p
, " ", " ")
345 for p1
, p2
in zip(l1
, l2
):
351 ifaces
= Interfaces()
353 ifaceuart
= ifaces
['uart']
354 print (ifaceuart
.ifacedef(0))
355 print (uartinterface_decl
.ifacedef(0))
356 assert ifaceuart
.ifacedef(0) == uartinterface_decl
.ifacedef(0)
358 ifacetwi
= ifaces
['twi']
359 print (ifacetwi
.ifacedef(0))
360 print (twiinterface_decl
.ifacedef(0))
361 assert ifacetwi
.ifacedef(0) == twiinterface_decl
.ifacedef(0)