4 from UserDict
import UserDict
6 from collections
import UserDict
8 from bsv
.wire_def
import generic_io
# special case
9 from bsv
.wire_def
import muxwire
# special case
13 """ pin interface declaration.
14 * name is the name of the pin
15 * ready, enabled and io all create a (* .... *) prefix
16 * action changes it to an "in" if true
19 def __init__(self
, name
,
28 self
.enabled
= enabled
31 self
.bitspec
= bitspec
if bitspec
else 'Bit#(1)'
32 self
.outenmode
= outenmode
34 # bsv will look like this (method declaration):
36 (*always_ready,always_enabled*) method Bit#(1) io0_cell_outen;
37 (*always_ready,always_enabled,result="io"*) method
38 Action io0_inputval (Bit#(1) in);
41 def ifacefmt(self
, fmtfn
):
45 status
.append('always_ready')
47 status
.append('always_enabled')
49 status
.append('result="io"')
52 res
+= ','.join(status
)
57 name
= fmtfn(self
.name
)
61 res
+= ' (%s in)' % self
.bitspec
63 res
+= " %s " % self
.bitspec
68 # sample bsv method definition :
70 method Action cell0_mux(Bit#(2) in);
75 def ifacedef(self
, fmtoutfn
, fmtinfn
, fmtdecfn
):
78 fmtname
= fmtinfn(self
.name
)
80 res
+= fmtdecfn(self
.name
)
81 res
+= '(%s in);\n' % self
.bitspec
82 res
+= ' %s<=in;\n' % fmtname
85 fmtname
= fmtoutfn(self
.name
)
86 res
+= "%s=%s;" % (self
.name
, fmtname
)
88 # sample bsv wire (wire definiton):
90 Wire#(Bit#(2)) wrcell0_mux<-mkDWire(0);
93 def wirefmt(self
, fmtoutfn
, fmtinfn
, fmtdecfn
):
94 res
= ' Wire#(%s) ' % self
.bitspec
96 res
+= '%s' % fmtinfn(self
.name
)
98 res
+= '%s' % fmtoutfn(self
.name
)
99 res
+= "<-mkDWire(0);"
103 class Interface(object):
104 """ create an interface from a list of pinspecs.
105 each pinspec is a dictionary, see Pin class arguments
106 single indicates that there is only one of these, and
107 so the name must *not* be extended numerically (see pname)
109 # sample interface object:
111 twiinterface_decl = Interface('twi',
112 [{'name': 'sda', 'outen': True},
113 {'name': 'scl', 'outen': True},
117 def __init__(self
, ifacename
, pinspecs
, ganged
=None, single
=False):
118 self
.ifacename
= ifacename
119 self
.ganged
= ganged
or {}
120 self
.pins
= [] # a list of instances of class Pin
121 self
.pinspecs
= pinspecs
# a list of dictionary
126 if p
.get('outen') is True: # special case, generate 3 pins
128 for psuffix
in ['out', 'outen', 'in']:
129 # changing the name (like sda) to (twi_sda_out)
130 _p
['name'] = "%s_%s" % (self
.pname(p
['name']), psuffix
)
131 _p
['action'] = psuffix
!= 'in'
132 self
.pins
.append(Pin(**_p
))
133 # will look like {'name': 'twi_sda_out', 'action': True}
134 # {'name': 'twi_sda_outen', 'action': True}
135 #{'name': 'twi_sda_in', 'action': False}
136 # NOTice - outen key is removed
138 _p
['name'] = self
.pname(p
['name'])
139 self
.pins
.append(Pin(**_p
))
141 # sample interface object:
143 uartinterface_decl = Interface('uart',
145 {'name': 'tx', 'action': True},
149 getifacetype is called multiple times in actual_pinmux.py
150 x = ifaces.getifacetype(temp), where temp is uart_rx, spi_mosi
151 Purpose is to identify is function : input/output/inout
154 def getifacetype(self
, name
):
155 for p
in self
.pinspecs
:
156 fname
= "%s_%s" % (self
.ifacename
, p
['name'])
157 #print "search", self.ifacename, name, fname
166 def pname(self
, name
):
167 """ generates the interface spec e.g. flexbus_ale
168 if there is only one flexbus interface, or
169 sd{0}_cmd if there are several. string format
170 function turns this into sd0_cmd, sd1_cmd as
171 appropriate. single mode stops the numerical extension.
174 return '%s_%s' % (self
.ifacename
, name
)
175 return '%s{0}_%s' % (self
.ifacename
, name
)
177 def busfmt(self
, *args
):
178 """ this function creates a bus "ganging" system based
179 on input from the {interfacename}.txt file.
180 only inout pins that are under the control of the
181 interface may be "ganged" together.
184 return '' # when self.ganged is None
187 for (k
, pnames
) in self
.ganged
.items():
188 name
= self
.pname('%senable' % k
).format(*args
)
189 decl
= 'Bit#(1) %s = 0;' % name
192 for p
in self
.pinspecs
:
193 if p
['name'] not in pnames
:
195 pname
= self
.pname(p
['name']).format(*args
)
196 if p
.get('outen') is True:
197 outname
= self
.ifacefmtoutfn(pname
)
198 ganged
.append("%s_outen" % outname
) # match wirefmt
200 gangedfmt
= '{%s} = duplicate(%s);'
201 res
.append(gangedfmt
% (',\n '.join(ganged
), name
))
202 return '\n'.join(res
) + '\n\n'
204 def wirefmt(self
, *args
):
205 res
= '\n'.join(map(self
.wirefmtpin
, self
.pins
)).format(*args
)
209 def ifacefmt(self
, *args
):
210 res
= '\n'.join(map(self
.ifacefmtdecpin
, self
.pins
)).format(*args
)
211 return '\n' + res
# pins is a list
213 def ifacefmtdecfn(self
, name
):
214 return name
# like: uart
216 def ifacefmtdecfn2(self
, name
):
217 return name
# like: uart
219 def ifacefmtdecfn3(self
, name
):
221 return "%s_outen" % name
# like uart_outen
223 def ifacefmtoutfn(self
, name
):
224 return "wr%s" % name
# like wruart
226 def ifacefmtinfn(self
, name
):
229 def wirefmtpin(self
, pin
):
230 return pin
.wirefmt(self
.ifacefmtoutfn
, self
.ifacefmtinfn
,
233 def ifacefmtdecpin(self
, pin
):
234 return pin
.ifacefmt(self
.ifacefmtdecfn
)
236 def ifacefmtpin(self
, pin
):
237 decfn
= self
.ifacefmtdecfn2
238 outfn
= self
.ifacefmtoutfn
239 #print pin, pin.outenmode
241 decfn
= self
.ifacefmtdecfn3
242 outfn
= self
.ifacefmtoutenfn
243 return pin
.ifacedef(outfn
, self
.ifacefmtinfn
,
246 def ifacedef(self
, *args
):
247 res
= '\n'.join(map(self
.ifacefmtpin
, self
.pins
))
248 res
= res
.format(*args
)
249 return '\n' + res
+ '\n'
252 class MuxInterface(Interface
):
254 def wirefmt(self
, *args
):
255 return muxwire
.format(*args
)
258 class IOInterface(Interface
):
260 def ifacefmtoutenfn(self
, name
):
261 return "cell{0}_mux_outen"
263 def ifacefmtoutfn(self
, name
):
264 """ for now strip off io{0}_ part """
265 return "cell{0}_mux_out"
267 def ifacefmtinfn(self
, name
):
268 return "cell{0}_mux_in"
270 def wirefmt(self
, *args
):
271 return generic_io
.format(*args
)
274 class Interfaces(UserDict
):
275 """ contains a list of interface definitions
278 def __init__(self
, pth
=None):
281 UserDict
.__init
__(self
, {})
284 ift
= 'interfaces.txt'
286 ift
= os
.path
.join(pth
, ift
)
287 with
open(ift
, 'r') as ifile
:
288 for ln
in ifile
.readlines():
291 name
= ln
[0] # will have uart
292 count
= int(ln
[1]) # will have count of uart
293 # spec looks like this:
295 [{'name': 'sda', 'outen': True},
296 {'name': 'scl', 'outen': True},
299 spec
, ganged
= self
.read_spec(pth
, name
)
300 iface
= Interface(name
, spec
, ganged
, count
== 1)
301 self
.ifaceadd(name
, count
, iface
)
303 def getifacetype(self
, fname
):
304 # finds the interface type, e.g sd_d0 returns "inout"
305 for iface
in self
.values():
306 typ
= iface
.getifacetype(fname
)
311 def ifaceadd(self
, name
, count
, iface
, at
=None):
313 at
= len(self
.ifacecount
) # ifacecount is a list
314 self
.ifacecount
.insert(at
, (name
, count
)) # appends the list
315 # with (name,count) *at* times
319 will check specific files of kind peripheral.txt like spi.txt,
320 uart.txt in test directory
323 def read_spec(self
, pth
, name
):
326 fname
= '%s.txt' % name
328 ift
= os
.path
.join(pth
, fname
)
329 with
open(ift
, 'r') as sfile
:
330 for ln
in sfile
.readlines():
334 d
= {'name': name
} # here we start to make the dictionary
336 d
['action'] = True # adding element to the dict
337 elif ln
[1] == 'inout':
341 if bus
not in ganged
:
343 ganged
[bus
].append(name
)
347 def ifacedef(self
, f
, *args
):
348 for (name
, count
) in self
.ifacecount
:
349 for i
in range(count
):
350 f
.write(self
.data
[name
].ifacedef(i
))
352 def busfmt(self
, f
, *args
):
353 f
.write("import BUtils::*;\n\n")
354 for (name
, count
) in self
.ifacecount
:
355 for i
in range(count
):
356 bf
= self
.data
[name
].busfmt(i
)
359 def ifacefmt(self
, f
, *args
):
361 // interface declaration between %s-{0} and pinmux'''
362 for (name
, count
) in self
.ifacecount
:
363 for i
in range(count
):
364 c
= comment
% name
.upper()
366 f
.write(self
.data
[name
].ifacefmt(i
))
368 def wirefmt(self
, f
, *args
):
369 comment
= '\n // following wires capture signals ' \
370 'to IO CELL if %s-{0} is\n' \
372 for (name
, count
) in self
.ifacecount
:
373 for i
in range(count
):
376 f
.write(self
.data
[name
].wirefmt(i
))
379 # ========= Interface declarations ================ #
381 mux_interface
= MuxInterface('cell', [{'name': 'mux', 'ready': False,
383 'bitspec': '{1}', 'action': True}])
385 io_interface
= IOInterface(
387 [{'name': 'cell_out', 'enabled': True, },
388 {'name': 'cell_outen', 'enabled': True, 'outenmode': True, },
389 {'name': 'cell_in', 'action': True, 'io': True}, ])
391 # == Peripheral Interface definitions == #
392 # these are the interface of the peripherals to the pin mux
393 # Outputs from the peripherals will be inputs to the pinmux
394 # module. Hence the change in direction for most pins
396 # ======================================= #
399 if __name__
== '__main__':
401 uartinterface_decl
= Interface('uart',
403 {'name': 'tx', 'action': True},
406 twiinterface_decl
= Interface('twi',
407 [{'name': 'sda', 'outen': True},
408 {'name': 'scl', 'outen': True},
411 def _pinmunge(p
, sep
, repl
, dedupe
=True):
412 """ munges the text so it's easier to compare.
413 splits by separator, strips out blanks, re-joins.
418 p
= filter(lambda x
: x
, p
) # filter out blanks
422 """ munges the text so it's easier to compare.
424 # first join lines by semicolons, strip out returns
426 p
= map(lambda x
: x
.replace('\n', ''), p
)
428 # now split first by brackets, then spaces (deduping on spaces)
429 p
= _pinmunge(p
, "(", " ( ", False)
430 p
= _pinmunge(p
, ")", " ) ", False)
431 p
= _pinmunge(p
, " ", " ")
437 for p1
, p2
in zip(l1
, l2
):
443 ifaces
= Interfaces()
445 ifaceuart
= ifaces
['uart']
446 print (ifaceuart
.ifacedef(0))
447 print (uartinterface_decl
.ifacedef(0))
448 assert ifaceuart
.ifacedef(0) == uartinterface_decl
.ifacedef(0)
450 ifacetwi
= ifaces
['twi']
451 print (ifacetwi
.ifacedef(0))
452 print (twiinterface_decl
.ifacedef(0))
453 assert ifacetwi
.ifacedef(0) == twiinterface_decl
.ifacedef(0)