src/bsv/peripheral_gen/base.py

   1 import types
   2
   3
   4 def li(txt, indent):
   5     indent = ' ' * indent
   6     istxt = False
   7     if isinstance(txt, str):
   8         istxt = True
   9         txt = txt.split('\n')
  10     res = []
  11     for line in txt:
  12         line = line.split('\n')
  13         res += line
  14     txt = res
  15     res = []
  16     for line in txt:
  17         res.append(indent + line)
  18     if istxt:
  19         res = '\n'.join(res)
  20     return res
  21
  22
  23 class PBase(object):
  24     def __init__(self, name):
  25         self.name = name
  26
  27     def extifdecl(self, name, count):
  28         sname = self.get_iname(count)
  29         return "interface PeripheralSide%s %s;" % (name.upper(), sname)
  30
  31     def has_axi_master(self):
  32         return False
  33
  34     def irq_name(self):
  35         return ""
  36
  37     def mk_dma_irq(self, name, count):
  38         if not self.irq_name():
  39             return ''
  40         sname = self.get_iname(count)
  41         return "{0}_interrupt".format(sname)
  42
  43     def mk_dma_rule(self, name, count):
  44         irqname = self.mk_dma_irq(name, count)
  45         if not irqname:
  46             return ''
  47         pirqname = self.irq_name().format(count)
  48         template = "   {0}_interrupt.send(\n" + \
  49                    "           slow_peripherals.{1});"
  50         return template.format(irqname, pirqname)
  51
  52     def get_clock_reset(self, name, count):
  53         return "slow_clock,slow_reset"
  54
  55     def mk_dma_sync(self, name, count):
  56         irqname = self.mk_dma_irq(name, count)
  57         if not irqname:
  58             return ''
  59         sname = self.peripheral.iname().format(count)
  60         template = "SyncBitIfc#(Bit#(1)) {0} <-\n" + \
  61                    "           <-mkSyncBitToCC({1});"
  62         return template.format(irqname, self.get_clock_reset(name, count))
  63
  64     def mk_dma_connect(self, name, count):
  65         irqname = self.mk_dma_irq(name, count)
  66         if not irqname:
  67             return ''
  68         return "{0}.read".format(irqname)
  69
  70     def fastifdecl(self, name, count):
  71         return ''
  72
  73     def slowifdeclmux(self, name, count):
  74         return ''
  75
  76     def slowimport(self):
  77         return ''
  78
  79     def num_axi_regs32(self):
  80         return 0
  81
  82     def slowifdecl(self):
  83         return ''
  84
  85     def get_iname(self, inum):
  86         return "{0}{1}".format(self.name, self.mksuffix(self.name, inum))
  87
  88     def axibase(self, name, ifacenum):
  89         name = name.upper()
  90         return "%(name)s%(ifacenum)dBase" % locals()
  91
  92     def axiend(self, name, ifacenum):
  93         name = name.upper()
  94         return "%(name)s%(ifacenum)dEnd" % locals()
  95
  96     def axi_reg_def(self, start, name, ifacenum):
  97         name = name.upper()
  98         offs = self.num_axi_regs32() * 4 * 16
  99         if offs == 0:
 100             return ('', 0)
 101         end = start + offs - 1
 102         bname = self.axibase(name, ifacenum)
 103         bend = self.axiend(name, ifacenum)
 104         comment = "%d 32-bit regs" % self.num_axi_regs32()
 105         return ("    `define %(bname)s 'h%(start)08X\n"
 106                 "    `define %(bend)s  'h%(end)08X // %(comment)s" % locals(),
 107                 offs)
 108
 109     def axi_master_name(self, name, ifacenum, typ=''):
 110         name = name.upper()
 111         return "{0}{1}_master_num".format(name, ifacenum)
 112
 113     def axi_slave_name(self, name, ifacenum, typ=''):
 114         name = name.upper()
 115         return "{0}{1}_{2}slave_num".format(name, ifacenum, typ)
 116
 117     def axi_master_idx(self, idx, name, ifacenum, typ):
 118         name = self.axi_master_name(name, ifacenum, typ)
 119         return ("typedef {0} {1};".format(idx, name), 1)
 120
 121     def axi_slave_idx(self, idx, name, ifacenum, typ):
 122         name = self.axi_slave_name(name, ifacenum, typ)
 123         return ("typedef {0} {1};".format(idx, name), 1)
 124
 125     def axi_fastaddr_map(self, name, ifacenum):
 126         return self.axi_addr_map(name, ifacenum, 'fast')
 127
 128     def axi_addr_map(self, name, ifacenum, typ=""):
 129         bname = self.axibase(name, ifacenum)
 130         bend = self.axiend(name, ifacenum)
 131         name = self.axi_slave_name(name, ifacenum, typ)
 132         template = """\
 133 if(addr>=`{0} && addr<=`{1})
 134     return tuple2(True,fromInteger(valueOf({2})));
 135 else"""
 136         return template.format(bname, bend, name)
 137
 138     def mk_pincon(self, name, count):
 139         # TODO: really should be using bsv.interface_decl.Interfaces
 140         # pin-naming rules.... logic here is hard-coded to duplicate
 141         # it (see Interface.__init__ outen)
 142         ret = []
 143         for p in self.peripheral.pinspecs:
 144             typ = p['type']
 145             pname = p['name']
 146             #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
 147             n = name  # "{0}{1}".format(self.name, self.mksuffix(name, count))
 148             ret.append("//%s %s" % (n, str(p)))
 149             sname = self.peripheral.iname().format(count)
 150             sname = "{0}.{1}".format(sname, pname)
 151             ps = "pinmux.peripheral_side.%s" % sname
 152             if typ == 'out' or typ == 'inout':
 153                 fname = self.pinname_out(pname)
 154                 if not n.startswith('gpio'):  # XXX EURGH! horrible hack
 155                     n_ = "{0}{1}".format(n, count)
 156                 else:
 157                     n_ = n
 158                 if fname:
 159                     if p.get('outen'):
 160                         ps_ = ps + '_out'
 161                     else:
 162                         ps_ = ps
 163                     ret.append("mkConnection({0},\n\t\t\t{1}.{2});"
 164                                .format(ps_, n_, fname))
 165                 fname = None
 166                 if p.get('outen'):
 167                     fname = self.pinname_outen(pname)
 168                 if fname:
 169                     if isinstance(fname, str):
 170                         fname = "{0}.{1}".format(n_, fname)
 171                     fname = self.pinname_tweak(pname, 'outen', fname)
 172                     ret.append("mkConnection({0}_outen,\n\t\t\t{1});"
 173                                .format(ps, fname))
 174             if typ == 'in' or typ == 'inout':
 175                 fname = self.pinname_in(pname)
 176                 if fname:
 177                     if p.get('outen'):
 178                         ps_ = ps + '_in'
 179                     else:
 180                         ps_ = ps
 181                     n_ = "{0}{1}".format(n, count)
 182                     n_ = '{0}.{1}'.format(n_, fname)
 183                     n_ = self.ifname_tweak(pname, 'in', n_)
 184                     ret.append(
 185                         "mkConnection({1},\n\t\t\t{0});".format(
 186                             ps_, n_))
 187         return '\n'.join(ret)
 188
 189     def mk_cellconn(self, *args):
 190         return ''
 191
 192     def mkfast_peripheral(self, size=0):
 193         return ''
 194
 195     def mkslow_peripheral(self, size=0):
 196         return ''
 197
 198     def mksuffix(self, name, i):
 199         return i
 200
 201     def __mk_connection(self, con, aname, fabricname):
 202         txt = "mkConnection ({2}.v_to_slaves\n" + \
 203               "            [fromInteger(valueOf({1}))],\n" + \
 204               "            {0});"
 205
 206         print "PBase __mk_connection", self.name, aname
 207         if not con:
 208             return ''
 209         return txt.format(con, aname, fabricname)
 210
 211     def __mk_master_connection(self, con, aname):
 212         txt = "mkConnection (slow_fabric.v_to_slaves\n" + \
 213               "            [fromInteger(valueOf({1}))],\n" + \
 214               "            {0});"
 215
 216         print "PBase __mk_connection", self.name, aname
 217         if not con:
 218             return ''
 219         return txt.format(con, aname)
 220
 221     def mk_connection(self, count, fabricname, typ, name=None):
 222         if name is None:
 223             name = self.name
 224         print "PBase mk_conn", self.name, count
 225         aname = self.axi_slave_name(name, count, typ)
 226         #dname = self.mksuffix(name, count)
 227         #dname = "{0}{1}".format(name, dname)
 228         con = self._mk_connection(name, count).format(count, aname)
 229         return self.__mk_connection(con, aname, fabricname)
 230
 231     def _mk_connection(self, name=None, count=0):
 232         return ''
 233
 234     def pinname_out(self, pname):
 235         return ''
 236
 237     def pinname_in(self, pname):
 238         return ''
 239
 240     def pinname_outen(self, pname):
 241         return ''
 242
 243     def ifname_tweak(self, pname, typ, txt):
 244         return txt
 245
 246     def pinname_tweak(self, pname, typ, txt):
 247         return txt
 248
 249     def num_irqs(self):
 250         return 0
 251
 252     def mk_plic(self, inum, irq_offs):
 253         res = []
 254         print "mk_plic", self.name, inum, irq_offs
 255         niq = self.num_irqs()
 256         if niq == 0:
 257             return ('', irq_offs)
 258         name = self.get_iname(inum)
 259         res.append("// PLIC rules for {0}".format(name))
 260         for idx in range(niq):
 261             plic_obj = self.plic_object(name, idx)
 262             print "plic_obj", name, idx, plic_obj
 263             plic = mkplic_rule.format(name, plic_obj, irq_offs)
 264             res.append(plic)
 265             irq_offs += 1  # increment to next irq
 266         return ('\n'.join(res), irq_offs)
 267
 268     def mk_ext_ifacedef(self, iname, inum):
 269         return ''
 270
 271     def extfastifinstance(self, name, count):
 272         return ''
 273
 274     def _extifinstance(self, name, count, suffix, prefix, samename=False,
 275                        ifsuffix=None):
 276         if ifsuffix is None:
 277             ifsuffix = ''
 278         pname = self.get_iname(count)
 279         if samename:
 280             sname = pname
 281         else:
 282             sname = self.peripheral.iname().format(count)
 283         template = "interface {0}{3} = {2}{1}{4};"
 284         return template.format(pname, sname, prefix, suffix, ifsuffix)
 285
 286     def extifinstance2(self, name, count):
 287         return ''
 288
 289     def extifinstance(self, name, count):
 290         return self._extifinstance(name, count, "",
 291                                    "pinmux.peripheral_side.")
 292
 293
 294 mkplic_rule = """\
 295 rule rl_connect_{0}_to_plic_{2};
 296    if({1} == 1'b1) begin
 297        ff_gateway_queue[{2}].enq(1);
 298        plic.ifc_external_irq[{2}].irq_frm_gateway(True);
 299    end
 300 endrule
 301 """
 302
 303 axi_master_declarations = """\
 304 typedef 0 Dmem_master_num;
 305 typedef 1 Imem_master_num;
 306 {0}
 307 typedef TAdd#(LastGen_master_num, `ifdef Debug 1 `else 0 `endif )
 308                 Debug_master_num;
 309 typedef TAdd#(Debug_master_num, `ifdef DMA 1 `else 0 `endif )
 310                 DMA_master_num;
 311 typedef TAdd#(DMA_master_num,1)
 312                 Num_Masters;
 313 """
 314
 315 axi_fastslave_declarations = """\
 316 {0}
 317 typedef  TAdd#(LastGen_fastslave_num,1)      Sdram_slave_num;
 318 typedef  TAdd#(Sdram_slave_num   ,`ifdef SDRAM      1 `else 0 `endif )
 319                       Sdram_cfg_slave_num;
 320 typedef TAdd#(Sdram_cfg_slave_num,`ifdef BOOTROM    1 `else 0 `endif )
 321                 BootRom_slave_num   ;
 322 typedef TAdd#(BootRom_slave_num  ,`ifdef Debug      1 `else 0 `endif )
 323                 Debug_slave_num ;
 324 typedef  TAdd#(Debug_slave_num   , `ifdef TCMemory  1 `else 0 `endif )
 325                 TCM_slave_num;
 326 typedef  TAdd#(TCM_slave_num     ,`ifdef DMA        1 `else 0 `endif )
 327                 Dma_slave_num;
 328 typedef  TAdd#(Dma_slave_num      ,1 )      SlowPeripheral_slave_num;
 329 typedef  TAdd#(SlowPeripheral_slave_num,`ifdef VME  1 `else 0 `endif )
 330                 VME_slave_num;
 331 typedef TAdd#(VME_slave_num,1) Num_Fast_Slaves;
 332 """
 333
 334 axi_slave_declarations = """\
 335 typedef  0  SlowMaster;
 336 {0}
 337 typedef  TAdd#(LastGen_slave_num,`ifdef CLINT       1 `else 0 `endif )
 338               CLINT_slave_num;
 339 typedef  TAdd#(CLINT_slave_num  ,`ifdef PLIC        1 `else 0 `endif )
 340               Plic_slave_num;
 341 typedef  TAdd#(Plic_slave_num   ,`ifdef AXIEXP      1 `else 0 `endif )
 342               AxiExp1_slave_num;
 343 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
 344 """
 345
 346 pinmux_cellrule = """\
 347 rule connect_select_lines_pinmux;
 348 {0}
 349 endrule
 350 """
 351
 352
 353 class CallFn(object):
 354     def __init__(self, peripheral, name):
 355         self.peripheral = peripheral
 356         self.name = name
 357
 358     def __call__(self, *args):
 359         #print "__call__", self.name, self.peripheral.slow, args
 360         if not self.peripheral.slow:
 361             return ''
 362         return getattr(self.peripheral.slow, self.name)(*args[1:])
 363
 364
 365 class PeripheralIface(object):
 366     def __init__(self, ifacename):
 367         self.slow = None
 368         slow = slowfactory.getcls(ifacename)
 369         print "Iface", ifacename, slow
 370         if slow:
 371             self.slow = slow(ifacename)
 372             self.slow.peripheral = self
 373         for fname in ['slowimport',
 374                       'extfastifinstance',
 375                       'extifinstance2', 'extifinstance', 'extifdecl',
 376                       'slowifdecl', 'slowifdeclmux',
 377                       'fastifdecl',
 378                       'mkslow_peripheral',
 379                       'mk_dma_sync', 'mk_dma_connect', 'mk_dma_rule',
 380                       'mkfast_peripheral',
 381                       'mk_plic', 'mk_ext_ifacedef',
 382                       'mk_connection', 'mk_cellconn', 'mk_pincon']:
 383             fn = CallFn(self, fname)
 384             setattr(self, fname, types.MethodType(fn, self))
 385
 386         #print "PeripheralIface"
 387         #print dir(self)
 388
 389     def mksuffix(self, name, i):
 390         if self.slow is None:
 391             return i
 392         return self.slow.mksuffix(name, i)
 393
 394     def axi_reg_def(self, start, count):
 395         if not self.slow:
 396             return ('', 0)
 397         return self.slow.axi_reg_def(start, self.ifacename, count)
 398
 399     def axi_master_idx(self, start, count, typ):
 400         if not self.slow or not self.slow.has_axi_master():
 401             return ('', 0)
 402         return self.slow.axi_master_idx(start, self.ifacename, count, typ)
 403
 404     def axi_slave_idx(self, start, count, typ):
 405         if not self.slow:
 406             return ('', 0)
 407         return self.slow.axi_slave_idx(start, self.ifacename, count, typ)
 408
 409     def axi_fastaddr_map(self, count):
 410         if not self.slow:
 411             return ''
 412         return self.slow.axi_fastaddr_map(self.ifacename, count)
 413
 414     def axi_addr_map(self, count):
 415         if not self.slow:
 416             return ''
 417         return self.slow.axi_addr_map(self.ifacename, count)
 418
 419
 420 class PeripheralInterfaces(object):
 421     def __init__(self):
 422         self.fastbusmode = False
 423
 424     def slowimport(self, *args):
 425         ret = []
 426         for (name, count) in self.ifacecount:
 427             #print "slowimport", name, self.data[name].slowimport
 428             ret.append(self.data[name].slowimport())
 429         return '\n'.join(li(list(filter(None, ret)), 4))
 430
 431     def extfastifinstance(self, *args):
 432         ret = []
 433         for (name, count) in self.ifacecount:
 434             for i in range(count):
 435                 iname = self.data[name].iname().format(i)
 436                 print "extfast", iname, self.is_on_fastbus(name, i)
 437                 if self.is_on_fastbus(name, i):
 438                     continue
 439                 ret.append(self.data[name].extfastifinstance(name, i))
 440         return '\n'.join(li(list(filter(None, ret)), 8))
 441
 442     def extifinstance2(self, *args):
 443         ret = []
 444         for (name, count) in self.ifacecount:
 445             for i in range(count):
 446                 iname = self.data[name].iname().format(i)
 447                 ret.append(self.data[name].extifinstance2(name, i))
 448         return '\n'.join(li(list(filter(None, ret)), 8))
 449
 450     def extifinstance(self, *args):
 451         ret = []
 452         for (name, count) in self.ifacecount:
 453             for i in range(count):
 454                 iname = self.data[name].iname().format(i)
 455                 if not self.is_on_fastbus(name, i):
 456                     continue
 457                 ret.append(self.data[name].extifinstance(name, i))
 458         return '\n'.join(li(list(filter(None, ret)), 8))
 459
 460     def extifdecl(self, *args):
 461         ret = []
 462         for (name, count) in self.ifacecount:
 463             for i in range(count):
 464                 if not self.is_on_fastbus(name, i):
 465                     continue
 466                 ret.append(self.data[name].extifdecl(name, i))
 467         return '\n'.join(li(list(filter(None, ret)), 8))
 468
 469     def slowifdeclmux(self, *args):
 470         ret = []
 471         for (name, count) in self.ifacecount:
 472             for i in range(count):
 473                 ret.append(self.data[name].slowifdeclmux(name, i))
 474         return '\n'.join(li(list(filter(None, ret)), 8))
 475
 476     def fastifdecl(self, *args):
 477         ret = []
 478         for (name, count) in self.ifacecount:
 479             for i in range(count):
 480                 print "fastifdecl", name, i, self.is_on_fastbus(name, i)
 481                 if self.is_on_fastbus(name, i):
 482                     continue
 483                 ret.append(self.data[name].fastifdecl(name, i))
 484         return '\n'.join(li(list(filter(None, ret)), 4))
 485
 486     def slowifdecl(self, *args):
 487         ret = []
 488         for (name, count) in self.ifacecount:
 489             for i in range(count):
 490                 if self.is_on_fastbus(name, i):
 491                     continue
 492                 ret.append(self.data[name].slowifdecl().format(i, name))
 493         return '\n'.join(list(filter(None, ret)))
 494
 495     def axi_fastmem_def(self, *args):
 496         return self._axi_reg_def(0x50000000, *args)
 497
 498     def axi_reg_def(self, *args):
 499         return self._axi_reg_def(0x00011100, *args)
 500
 501     def _axi_reg_def(self, start, *args):
 502         ret = []
 503         for (name, count) in self.ifacecount:
 504             for i in range(count):
 505                 if self.is_on_fastbus(name, i):
 506                     continue
 507                 x = self.data[name].axi_reg_def(start, i)
 508                 #print ("ifc", name, x)
 509                 (rdef, offs) = x
 510                 ret.append(rdef)
 511                 start += offs
 512         return '\n'.join(list(filter(None, ret)))
 513
 514     def _axi_num_idx(self, start, template, typ, idxtype, *args):
 515         ret = []
 516         for (name, count) in self.ifacecount:
 517             for i in range(count):
 518                 if self.is_on_fastbus(name, i):
 519                     continue
 520                 if typ == 'master':
 521                     fn = self.data[name].axi_master_idx
 522                 else:
 523                     fn = self.data[name].axi_slave_idx
 524                 (rdef, offs) = fn(start, i, idxtype)
 525                 #print ("ifc", name, rdef, offs)
 526                 ret.append(rdef)
 527                 start += offs
 528         ret.append("typedef %d LastGen_%s_num;" % (start - 1, typ))
 529         decls = '\n'.join(list(filter(None, ret)))
 530         return template.format(decls)
 531
 532     def axi_slave_idx(self, *args):
 533         return self._axi_num_idx(0, axi_slave_declarations, 'slave',
 534                                  '', *args)
 535
 536     def axi_fastslave_idx(self, *args):
 537         return self._axi_num_idx(0, axi_fastslave_declarations, 'fastslave',
 538                                  'fast', *args)
 539
 540     def axi_master_idx(self, *args):
 541         return self._axi_num_idx(2, axi_master_declarations, 'master',
 542                                  'master', *args)
 543
 544     def axi_fastslave_idx(self, *args):
 545         return self._axi_num_idx(0, axi_fastslave_declarations, 'fastslave',
 546                                  'fast', *args)
 547
 548     def axi_fastaddr_map(self, *args):
 549         ret = []
 550         for (name, count) in self.ifacecount:
 551             for i in range(count):
 552                 if self.is_on_fastbus(name, i):
 553                     continue
 554                 ret.append(self.data[name].axi_fastaddr_map(i))
 555         return '\n'.join(li(list(filter(None, ret)), 8))
 556
 557     def axi_addr_map(self, *args):
 558         ret = []
 559         for (name, count) in self.ifacecount:
 560             for i in range(count):
 561                 if self.is_on_fastbus(name, i):
 562                     continue
 563                 ret.append(self.data[name].axi_addr_map(i))
 564         return '\n'.join(li(list(filter(None, ret)), 8))
 565
 566     def mkfast_peripheral(self, *args):
 567         ret = []
 568         for (name, count) in self.ifacecount:
 569             for i in range(count):
 570                 if self.is_on_fastbus(name, i):
 571                     continue
 572                 #print "mkfast", name, count
 573                 x = self.data[name].mkfast_peripheral()
 574                 print name, count, x
 575                 suffix = self.data[name].mksuffix(name, i)
 576                 ret.append(x.format(suffix))
 577         return '\n'.join(li(list(filter(None, ret)), 8))
 578
 579     def mkslow_peripheral(self, *args):
 580         ret = []
 581         for (name, count) in self.ifacecount:
 582             for i in range(count):
 583                 if self.is_on_fastbus(name, i):
 584                     continue
 585                 #print "mkslow", name, count
 586                 x = self.data[name].mkslow_peripheral()
 587                 print name, count, x
 588                 suffix = self.data[name].mksuffix(name, i)
 589                 ret.append(x.format(suffix))
 590         return '\n'.join(li(list(filter(None, ret)), 8))
 591
 592     def mk_fast_connection(self, *args):
 593         ret = []
 594         for (name, count) in self.ifacecount:
 595             for i in range(count):
 596                 if self.is_on_fastbus(name, i):
 597                     continue
 598                 txt = self.data[name].mk_connection(i, "fabric", "fast")
 599                 if name == 'gpioa':
 600                     print "txt", txt
 601                     print self.data[name].mk_connection
 602                 ret.append(txt)
 603         return '\n'.join(li(list(filter(None, ret)), 12))
 604
 605     def mk_connection(self, *args):
 606         ret = []
 607         for (name, count) in self.ifacecount:
 608             for i in range(count):
 609                 if self.is_on_fastbus(name, i):
 610                     continue
 611                 txt = self.data[name].mk_connection(i, "slow_fabric", "")
 612                 if name == 'gpioa':
 613                     print "txt", txt
 614                     print self.data[name].mk_connection
 615                 ret.append(txt)
 616         return '\n'.join(li(list(filter(None, ret)), 8))
 617
 618     def mk_cellconn(self):
 619         ret = []
 620         cellcount = 0
 621         for (name, count) in self.ifacecount:
 622             for i in range(count):
 623                 if self.is_on_fastbus(name, i):
 624                     continue
 625                 res = self.data[name].mk_cellconn(cellcount, name, i)
 626                 if not res:
 627                     continue
 628                 (txt, cellcount) = res
 629                 ret.append(txt)
 630         ret = li('\n'.join(list(filter(None, ret))), 4)
 631         return li(pinmux_cellrule.format(ret), 4)
 632
 633     def mk_pincon(self):
 634         ret = []
 635         for (name, count) in self.ifacecount:
 636             for i in range(count):
 637                 if self.is_on_fastbus(name, i):
 638                     continue
 639                 txt = self.data[name].mk_pincon(name, i)
 640                 ret.append(txt)
 641         return '\n'.join(li(list(filter(None, ret)), 4))
 642
 643     def mk_dma_irq(self):
 644         ret = []
 645         sync = []
 646         rules = []
 647         cnct = []
 648
 649         self.dma_count = 0
 650
 651         for (name, count) in self.ifacecount:
 652             ifacerules = []
 653             for i in range(count):
 654                 if not self.is_on_fastbus(name, i):
 655                     continue
 656                 txt = self.data[name].mk_dma_sync(name, i)
 657                 if txt:
 658                     self.dma_count += 1
 659                 sync.append(txt)
 660                 txt = self.data[name].mk_dma_rule(name, i)
 661                 ifacerules.append(txt)
 662                 txt = self.data[name].mk_dma_connect(name, i)
 663                 cnct.append(txt)
 664             ifacerules = list(filter(None, ifacerules))
 665             if ifacerules:
 666                 txt = "rule synchronize_%s_interrupts;" % name
 667                 rules.append(txt)
 668                 rules += ifacerules
 669                 rules.append("endrule")
 670
 671         cnct = list(filter(None, cnct))
 672         ct = self.dma_count
 673         _cnct = ["rule rl_connect_interrupt_to_DMA;",
 674                  "  Bit #(%d) lv_interrupt_to_DMA={" % ct]
 675         spc = "                      "
 676         spcsep = ",\n" + spc
 677         cnct = _cnct + [spc + spcsep.join(cnct)]
 678         cnct.append("   };")
 679         cnct.append("   dma.interrupt_from_peripherals(\n" +
 680                     "       lv_interrupt_to_DMA);")
 681         cnct.append("endrule;")
 682
 683         ret = list(filter(None, sync + rules + cnct))
 684         ret = li(ret, 15)
 685         return '\n'.join(ret)
 686
 687     def num_dmachannels(self):
 688         return "`define NUM_DMACHANNELS {0}".format(self.dma_count)
 689
 690     def mk_ext_ifacedef(self):
 691         ret = []
 692         for (name, count) in self.ifacecount:
 693             for i in range(count):
 694                 if self.is_on_fastbus(name, i):
 695                     continue
 696                 txt = self.data[name].mk_ext_ifacedef(name, i)
 697                 ret.append(txt)
 698         return '\n'.join(li(list(filter(None, ret)), 8))
 699
 700     def mk_plic(self):
 701         ret = []
 702         irq_offs = 8  # XXX: DMA scovers 0-7?
 703         for (name, count) in self.ifacecount:
 704             for i in range(count):
 705                 if self.is_on_fastbus(name, i):
 706                     continue
 707                 res = self.data[name].mk_plic(i, irq_offs)
 708                 if not res:
 709                     continue
 710                 (txt, irq_offs) = res
 711                 ret.append(txt)
 712         self.num_slow_irqs = irq_offs
 713         return '\n'.join(li(list(filter(None, ret)), 4))
 714
 715     def mk_sloirqsdef(self):
 716         return "    `define NUM_SLOW_IRQS {0}".format(self.num_slow_irqs)
 717
 718     def is_on_fastbus(self, name, i):
 719         #print "fastbus mode", self.fastbusmode, name, i
 720         iname = self.data[name].iname().format(i)
 721         if self.fastbusmode:
 722             return iname not in self.fastbus
 723         return iname in self.fastbus
 724
 725
 726 class PFactory(object):
 727     def getcls(self, name):
 728         from uart import uart
 729         from quart import quart
 730         from sdmmc import sdmmc
 731         from pwm import pwm
 732         from eint import eint
 733         from rs232 import rs232
 734         from twi import twi
 735         from eint import eint
 736         from jtag import jtag
 737         from spi import spi, mspi
 738         from qspi import qspi, mqspi
 739         from gpio import gpio
 740         from rgbttl import rgbttl
 741         from flexbus import flexbus
 742
 743         for k, v in {'uart': uart,
 744                      'rs232': rs232,
 745                      'twi': twi,
 746                      'quart': quart,
 747                      'mqspi': mqspi,
 748                      'mspi': mspi,
 749                      'qspi': qspi,
 750                      'spi': spi,
 751                      'pwm': pwm,
 752                      'eint': eint,
 753                      'sd': sdmmc,
 754                      'jtag': jtag,
 755                      'lcd': rgbttl,
 756                      'fb': flexbus,
 757                      'gpio': gpio
 758                      }.items():
 759             if name.startswith(k):
 760                 return v
 761         return None
 762
 763
 764 slowfactory = PFactory()
 765
 766 if __name__ == '__main__':
 767     p = uart('uart')
 768     print p.slowimport()
 769     print p.slowifdecl()
 770     i = PeripheralIface('uart')
 771     print i, i.slow
 772     i = PeripheralIface('gpioa')
 773     print i, i.slow