refactor peripheral_gen, split out interface classes
[pinmux.git] / src / bsv / peripheral_gen / eint.py
1 from bsv.peripheral_gen.base import PBase
2
3 class eint(PBase):
4
5 def slowimport(self):
6 size = len(self.peripheral.pinspecs)
7 return " `define NUM_EINTS %d" % size
8
9 def mkslow_peripheral(self, size=0):
10 size = len(self.peripheral.pinspecs)
11 return " Wire#(Bit#(%d)) wr_interrupt <- mkWire();" % size
12
13 def axi_slave_name(self, name, ifacenum):
14 return ''
15
16 def axi_slave_idx(self, idx, name, ifacenum):
17 return ('', 0)
18
19 def axi_addr_map(self, name, ifacenum):
20 return ''
21
22 def ifname_tweak(self, pname, typ, txt):
23 if typ != 'in':
24 return txt
25 print "ifnameweak", pname, typ, txt
26 return "wr_interrupt[{0}] <= ".format(pname)
27
28 def mk_pincon(self, name, count):
29 ret = [PBase.mk_pincon(self, name, count)]
30 size = len(self.peripheral.pinspecs)
31 ret.append(eint_pincon_template.format(size))
32 ret.append(" rule con_%s%d_io_in;" % (name, count))
33 ret.append(" wr_interrupt <= ({")
34 for idx, p in enumerate(self.peripheral.pinspecs):
35 pname = p['name']
36 sname = self.peripheral.pname(pname).format(count)
37 ps = "pinmux.peripheral_side.%s" % sname
38 comma = '' if idx == size - 1 else ','
39 ret.append(" {0}{1}".format(ps, comma))
40 ret.append(" });")
41 ret.append(" endrule")
42
43 return '\n'.join(ret)
44
45
46 eint_pincon_template = '''\
47 // EINT is offset at end of other peripheral interrupts
48 `ifdef PLIC
49 for(Integer i=0;i<{0};i=i+ 1)begin
50 rule connect_int_to_plic(wr_interrupt[i]==1);
51 ff_gateway_queue[i+`NUM_SLOW_IRQS].enq(1);
52 plic.ifc_external_irq[i+`NUM_SLOW_IRQS].irq_frm_gateway(True);
53 endrule
54 end
55 `endif
56 '''