src/bsv/peripheral_gen/quart.py

   1 from bsv.peripheral_gen.base import PBase
   2
   3
   4 class quart(PBase):
   5
   6     def slowimport(self):
   7         return "    import Uart16550         :: *;"
   8
   9     def irq_name(self):
  10         return "quart{0}_intr"
  11
  12     def slowifdecl(self):
  13         return "            interface RS232_PHY_Ifc quart{0}_coe;\n" + \
  14                "            method Bit#(1) %s;" % self.irq_name()
  15
  16     def get_clock_reset(self, name, count):
  17         return "slow_clock,slow_reset" # XXX TODO: change to uart_clock/reset
  18
  19     def num_axi_regs32(self):
  20         return 8
  21
  22     def mkslow_peripheral(self, size=0):
  23         return "        // XXX XXX TODO: change to uart_clock/reset" + \
  24                "        Uart16550_AXI4_Lite_Ifc quart{0} <- \n" + \
  25                "                mkUart16550(clocked_by sp_clock,\n" + \
  26                "                    reset_by sp_reset, sp_clock, sp_reset);"
  27
  28     def _mk_connection(self, name=None, count=0):
  29         return "quart{0}.slave_axi_uart"
  30
  31     def pinname_out(self, pname):
  32         return {'tx': 'coe_rs232.stx_out',
  33                 'rts': 'coe_rs232.rts_out',
  34                 }.get(pname, '')
  35
  36     def pinname_in(self, pname):
  37         return {'rx': 'coe_rs232.srx_in',
  38                 'cts': 'coe_rs232.cts_in'
  39                 }.get(pname, '')
  40
  41     def __disabled_mk_pincon(self, name, count):
  42         ret = [PBase.mk_pincon(self, name, count)]
  43         ret.append("    rule con_%s%d_io_in;" % (name, count))
  44         ret.append("       {0}{1}.coe_rs232.modem_input(".format(name, count))
  45         for idx, pname in enumerate(['rx', 'cts']):
  46             sname = self.peripheral.pname(pname).format(count)
  47             ps = "pinmux.peripheral_side.%s" % sname
  48             ret.append("            {0},".format(ps))
  49         ret.append("            1'b1,1'b0,1'b1")
  50         ret.append("        );")
  51         ret.append("    endrule")
  52
  53         return '\n'.join(ret)
  54
  55     def num_irqs(self):
  56         return 1
  57
  58     def plic_object(self, pname, idx):
  59         return "{0}_interrupt.read".format(pname)
  60
  61     def mk_plic(self, inum, irq_offs):
  62         name = self.get_iname(inum)
  63         ret = [uart_plic_template.format(name, irq_offs)]
  64         (ret2, irq_offs) = PBase.mk_plic(self, inum, irq_offs)
  65         ret.append(ret2)
  66         return ('\n'.join(ret), irq_offs)
  67
  68     def mk_ext_ifacedef(self, iname, inum):
  69         name = self.get_iname(inum)
  70         return "        method {0}_intr = {0}.irq;".format(name)
  71
  72     def slowifdeclmux(self, name, count):
  73         sname = self.peripheral.iname().format(count)
  74         return "        method Bit#(1) %s_intr;" % sname
  75
  76
  77 uart_plic_template = """\
  78      // PLIC {0} synchronisation with irq {1}
  79      SyncBitIfc#(Bit#(1)) {0}_interrupt <-
  80                                 mkSyncBitToCC(sp_clock, uart_reset);
  81      rule plic_synchronize_{0}_interrupt_{1};
  82          {0}_interrupt.send({0}.irq);
  83      endrule
  84 """