1 from bsv
.peripheral_gen
.base
import PBase
7 return "import sdr_top::*;"
9 def num_axi_regs32(self
):
10 return [0x400000, # defines an entire memory range (hack...)
11 12] # defines the number of configuration regs
13 def extfastifinstance(self
, name
, count
):
14 return "// TODO" + self
._extifinstance
(name
, count
, "_out", "", True,
17 def fastifdecl(self
, name
, count
):
18 return "// (*always_ready*) interface " + \
19 "Ifc_sdram_out sdr{0}_out;".format(count
)
21 def get_clock_reset(self
, name
, count
):
22 return "slow_clock, slow_reset"
24 def mkfast_peripheral(self
):
25 return "Ifc_sdr_slave sdr{0} <- mksdr_axi4_slave(clk0);"
27 def _mk_connection(self
, name
=None, count
=0):
28 return ["sdr{0}.axi4_slave_sdram",
29 "sdr{0}.axi4_slave_cntrl_reg"]
31 def pinname_out(self
, pname
):
32 return {'sdrwen': 'ifc_sdram_out.osdr_we_n',
33 'sdrcsn0': 'ifc_sdram_out.osdr_cs_n',
34 'sdrcke': 'ifc_sdram_out.osdr_cke',
35 'sdrrasn': 'ifc_sdram_out.osdr_ras_n',
36 'sdrcasn': 'ifc_sdram_out.osdr_cas_n',
39 def _mk_clk_con(self
, name
, count
, ctype
):
40 ret
= [PBase
._mk
_clk
_con
(self
, name
, count
, ctype
)]
41 for pname
, sz
, ptype
in [
45 ('ad_out', 32, 'out'),
47 ('ad_out_en', 32, 'out'),
49 bitspec
= "Bit#(%d)" % sz
50 txt
= self
._mk
_clk
_vcon
(name
, count
, ctype
, ptype
, pname
, bitspec
)
54 def _mk_pincon(self
, name
, count
, typ
):
55 ret
= [PBase
._mk
_pincon
(self
, name
, count
, typ
)]
56 assert typ
== 'fast' # TODO slow?
57 for pname
, stype
, ptype
in [
58 ('sdrdqm', 'osdr_dqm', 'out'),
59 ('sdrba', 'osdr_ba', 'out'),
60 ('sdrad', 'osdr_addr', 'out'),
61 ('sdrd_out', 'osdr_dout', 'out'),
62 ('sdrd_in', 'ipad_sdr_din', 'in'),
63 ('sdrd_out_en', 'osdr_den_n', 'out'),
65 ret
.append(self
._mk
_vpincon
(name
, count
, typ
, ptype
, pname
,
66 "ifc_sdram_out.{0}".format(stype
)))