src/bsv/peripheral_gen.py

   1 import types
   2 from copy import deepcopy
   3
   4
   5 class PBase(object):
   6     def __init__(self, name):
   7         self.name = name
   8
   9     def slowifdeclmux(self):
  10         return ''
  11
  12     def slowimport(self):
  13         return ''
  14
  15     def num_axi_regs32(self):
  16         return 0
  17
  18     def slowifdecl(self):
  19         return ''
  20
  21     def axibase(self, name, ifacenum):
  22         name = name.upper()
  23         return "%(name)s%(ifacenum)dBase" % locals()
  24
  25     def axiend(self, name, ifacenum):
  26         name = name.upper()
  27         return "%(name)s%(ifacenum)dEnd" % locals()
  28
  29     def axi_reg_def(self, start, name, ifacenum):
  30         name = name.upper()
  31         offs = self.num_axi_regs32() * 4 * 16
  32         if offs == 0:
  33             return ('', 0)
  34         end = start + offs - 1
  35         bname = self.axibase(name, ifacenum)
  36         bend = self.axiend(name, ifacenum)
  37         comment = "%d 32-bit regs" % self.num_axi_regs32()
  38         return ("    `define %(bname)s 'h%(start)08X\n"
  39                 "    `define %(bend)s  'h%(end)08X // %(comment)s" % locals(),
  40                 offs)
  41
  42     def axi_slave_name(self, name, ifacenum):
  43         name = name.upper()
  44         return "{0}{1}_slave_num".format(name, ifacenum)
  45
  46     def axi_slave_idx(self, idx, name, ifacenum):
  47         name = self.axi_slave_name(name, ifacenum)
  48         return ("typedef {0} {1};".format(idx, name), 1)
  49
  50     def axi_addr_map(self, name, ifacenum):
  51         bname = self.axibase(name, ifacenum)
  52         bend = self.axiend(name, ifacenum)
  53         name = self.axi_slave_name(name, ifacenum)
  54         return """\
  55         if(addr>=`{0} && addr<=`{1})
  56             return tuple2(True,fromInteger(valueOf({2})));
  57         else""".format(bname, bend, name)
  58
  59     def mk_pincon(self, name, count):
  60         # TODO: really should be using bsv.interface_decl.Interfaces
  61         # pin-naming rules.... logic here is hard-coded to duplicate
  62         # it (see Interface.__init__ outen)
  63         ret = []
  64         for p in self.peripheral.pinspecs:
  65             typ = p['type']
  66             pname = p['name']
  67             #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
  68             n = name  # "{0}{1}".format(self.name, self.mksuffix(name, count))
  69             ret.append("    //%s %s" % (n, str(p)))
  70             sname = self.peripheral.pname(pname).format(count)
  71             ps = "pinmux.peripheral_side.%s" % sname
  72             if typ == 'out' or typ == 'inout':
  73                 ret.append("    rule con_%s%d_%s_out;" % (name, count, pname))
  74                 fname = self.pinname_out(pname)
  75                 if not n.startswith('gpio'):  # XXX EURGH! horrible hack
  76                     n_ = "{0}{1}".format(n, count)
  77                 else:
  78                     n_ = n
  79                 if fname:
  80                     if p.get('outen'):
  81                         ps_ = ps + '_out'
  82                     else:
  83                         ps_ = ps
  84                     ret.append("      {0}({1}.{2});".format(ps_, n_, fname))
  85                 fname = None
  86                 if p.get('outen'):
  87                     fname = self.pinname_outen(pname)
  88                 if fname:
  89                     if isinstance(fname, str):
  90                         fname = "{0}.{1}".format(n_, fname)
  91                     fname = self.pinname_tweak(pname, 'outen', fname)
  92                     ret.append("      {0}_outen({1});".format(ps, fname))
  93                 ret.append("    endrule")
  94             if typ == 'in' or typ == 'inout':
  95                 fname = self.pinname_in(pname)
  96                 if fname:
  97                     if p.get('outen'):
  98                         ps_ = ps + '_in'
  99                     else:
 100                         ps_ = ps
 101                     ret.append(
 102                         "    rule con_%s%d_%s_in;" %
 103                         (name, count, pname))
 104                     n_ = "{0}{1}".format(n, count)
 105                     n_ = '{0}.{1}'.format(n_, fname)
 106                     n_ = self.ifname_tweak(pname, 'in', n_)
 107                     ret.append("      {1}({0});".format(ps_, n_))
 108                     ret.append("    endrule")
 109         return '\n'.join(ret)
 110
 111     def mk_cellconn(self, *args):
 112         return ''
 113
 114     def mkslow_peripheral(self, size=0):
 115         return ''
 116
 117     def mksuffix(self, name, i):
 118         return i
 119
 120     def __mk_connection(self, con, aname):
 121         txt = "        mkConnection (slow_fabric.v_to_slaves\n" + \
 122             "                    [fromInteger(valueOf({1}))],\n" + \
 123             "                    {0});"
 124
 125         print "PBase __mk_connection", self.name, aname
 126         if not con:
 127             return ''
 128         return txt.format(con, aname)
 129
 130     def mk_connection(self, count, name=None):
 131         if name is None:
 132             name = self.name
 133         print "PBase mk_conn", self.name, count
 134         aname = self.axi_slave_name(name, count)
 135         #dname = self.mksuffix(name, count)
 136         #dname = "{0}{1}".format(name, dname)
 137         con = self._mk_connection(name, count).format(count, aname)
 138         return self.__mk_connection(con, aname)
 139
 140     def _mk_connection(self, name=None, count=0):
 141         return ''
 142
 143     def pinname_out(self, pname):
 144         return ''
 145
 146     def pinname_in(self, pname):
 147         return ''
 148
 149     def pinname_outen(self, pname):
 150         return ''
 151
 152     def ifname_tweak(self, pname, typ, txt):
 153         return txt
 154
 155     def pinname_tweak(self, pname, typ, txt):
 156         return txt
 157
 158
 159 class uart(PBase):
 160
 161     def slowimport(self):
 162         return "          import Uart_bs         :: *;\n" + \
 163                "          import RS232_modified::*;"
 164
 165     def slowifdecl(self):
 166         return "            interface RS232 uart{0}_coe;\n" + \
 167                "            method Bit#(1) uart{0}_intr;"
 168
 169     def num_axi_regs32(self):
 170         return 8
 171
 172     def mkslow_peripheral(self, size=0):
 173         return "        Ifc_Uart_bs uart{0} <- \n" + \
 174                "                mkUart_bs(clocked_by sp_clock,\n" + \
 175                "                    reset_by uart_reset, sp_clock, sp_reset);"
 176
 177     def _mk_connection(self, name=None, count=0):
 178         return "uart{0}.slave_axi_uart"
 179
 180     def pinname_out(self, pname):
 181         return {'tx': 'coe_rs232.sout'}.get(pname, '')
 182
 183     def pinname_in(self, pname):
 184         return {'rx': 'coe_rs232.sin'}.get(pname, '')
 185
 186
 187 class qquart(PBase):
 188
 189     def slowimport(self):
 190         return "          import Uart16550         :: *;"
 191
 192     def slowifdecl(self):
 193         return "            interface RS232_PHY_Ifc uart{0}_coe;\n" + \
 194                "            method Bit#(1) uart{0}_intr;"
 195
 196     def num_axi_regs32(self):
 197         return 8
 198
 199     def mkslow_peripheral(self, size=0):
 200         return "        Uart16550_AXI4_Lite_Ifc uart{0} <- \n" + \
 201                "                mkUart16550(clocked_by sp_clock,\n" + \
 202                "                    reset_by uart_reset, sp_clock, sp_reset);"
 203
 204     def _mk_connection(self, name=None, count=0):
 205         return "uart{0}.slave_axi_uart"
 206
 207     def pinname_out(self, pname):
 208         return {'tx': 'coe_rs232.sout'}.get(pname, '')
 209
 210     def pinname_in(self, pname):
 211         return {'rx': 'coe_rs232.sin'}.get(pname, '')
 212
 213
 214 class rs232(PBase):
 215
 216     def slowimport(self):
 217         return "        import Uart_bs::*;\n" + \
 218                "        import RS232_modified::*;"
 219
 220     def slowifdecl(self):
 221         return "            interface RS232 uart{0}_coe;"
 222
 223     def num_axi_regs32(self):
 224         return 2
 225
 226     def mkslow_peripheral(self, size=0):
 227         return "        //Ifc_Uart_bs uart{0} <-" + \
 228                "        //       mkUart_bs(clocked_by uart_clock,\n" + \
 229                "        //          reset_by uart_reset,sp_clock, sp_reset);" +\
 230                "        Ifc_Uart_bs uart{0} <-" + \
 231                "                mkUart_bs(clocked_by sp_clock,\n" + \
 232                "                    reset_by sp_reset, sp_clock, sp_reset);"
 233
 234     def _mk_connection(self, name=None, count=0):
 235         return "uart{0}.slave_axi_uart"
 236
 237     def pinname_out(self, pname):
 238         return {'tx': 'coe_rs232.sout'}.get(pname, '')
 239
 240     def pinname_in(self, pname):
 241         return {'rx': 'coe_rs232.sin'}.get(pname, '')
 242
 243
 244 class twi(PBase):
 245
 246     def slowimport(self):
 247         return "        import I2C_top           :: *;"
 248
 249     def slowifdecl(self):
 250         return "            interface I2C_out twi{0}_out;\n" + \
 251                "            method Bit#(1) twi{0}_isint;"
 252
 253     def num_axi_regs32(self):
 254         return 8
 255
 256     def mkslow_peripheral(self, size=0):
 257         return "        I2C_IFC twi{0} <- mkI2CController();"
 258
 259     def _mk_connection(self, name=None, count=0):
 260         return "twi{0}.slave_i2c_axi"
 261
 262     def pinname_out(self, pname):
 263         return {'sda': 'out.sda_out',
 264                 'scl': 'out.scl_out'}.get(pname, '')
 265
 266     def pinname_in(self, pname):
 267         return {'sda': 'out.sda_in',
 268                 'scl': 'out.scl_in'}.get(pname, '')
 269
 270     def pinname_outen(self, pname):
 271         return {'sda': 'out.sda_out_en',
 272                 'scl': 'out.scl_out_en'}.get(pname, '')
 273
 274     def pinname_tweak(self, pname, typ, txt):
 275         if typ == 'outen':
 276             return "pack({0})".format(txt)
 277         return txt
 278
 279
 280 class eint(PBase):
 281
 282     def slowimport(self):
 283         size = len(self.peripheral.pinspecs)
 284         return "    `define NUM_EINTS %d" % size
 285
 286     def mkslow_peripheral(self, size=0):
 287         size = len(self.peripheral.pinspecs)
 288         return "        Wire#(Bit#(%d)) wr_interrupt <- mkWire();" % size
 289
 290     def axi_slave_name(self, name, ifacenum):
 291         return ''
 292
 293     def axi_slave_idx(self, idx, name, ifacenum):
 294         return ('', 0)
 295
 296     def axi_addr_map(self, name, ifacenum):
 297         return ''
 298
 299     def ifname_tweak(self, pname, typ, txt):
 300         if typ != 'in':
 301             return txt
 302         print "ifnameweak", pname, typ, txt
 303         return "wr_interrupt[{0}] <= ".format(pname)
 304
 305     def mk_pincon(self, name, count):
 306         ret = [PBase.mk_pincon(self, name, count)]
 307         size = len(self.peripheral.pinspecs)
 308         ret.append(eint_pincon_template.format(size))
 309         ret.append("    rule con_%s%d_io_in;" % (name, count))
 310         ret.append("    wr_interrupt <= ({")
 311         for idx, p in enumerate(self.peripheral.pinspecs):
 312             pname = p['name']
 313             sname = self.peripheral.pname(pname).format(count)
 314             ps = "pinmux.peripheral_side.%s" % sname
 315             comma = '' if idx == size - 1 else ','
 316             ret.append("             {0}{1}".format(ps, comma))
 317         ret.append("        });")
 318         ret.append("    endrule")
 319
 320         return '\n'.join(ret)
 321
 322
 323 eint_pincon_template = '''\
 324     // TODO: offset i by the number of eints already used
 325     for(Integer i=0;i<{0};i=i+ 1)begin
 326       rule connect_int_to_plic(wr_interrupt[i]==1);
 327                 ff_gateway_queue[i].enq(1);
 328                 plic.ifc_external_irq[i].irq_frm_gateway(True);
 329       endrule
 330     end
 331 '''
 332
 333
 334 class sdmmc(PBase):
 335
 336     def slowimport(self):
 337         return "        import sdcard_dummy              :: *;"
 338
 339     def slowifdecl(self):
 340         return "            interface QSPI_out sd{0}_out;\n" + \
 341                "            method Bit#(1) sd{0}_isint;"
 342
 343     def num_axi_regs32(self):
 344         return 13
 345
 346     def mkslow_peripheral(self):
 347         return "        Ifc_sdcard_dummy sd{0} <-  mksdcard_dummy();"
 348
 349     def _mk_connection(self, name=None, count=0):
 350         return "sd{0}.slave"
 351
 352     def pinname_in(self, pname):
 353         return "out.%s_in" % pname
 354
 355     def pinname_out(self, pname):
 356         return "out.%s_out" % pname
 357
 358     def pinname_outen(self, pname):
 359         if pname.startswith('d'):
 360             return "out.%s_outen" % pname
 361
 362
 363 class spi(PBase):
 364
 365     def slowimport(self):
 366         return "        import qspi              :: *;"
 367
 368     def slowifdecl(self):
 369         return "            interface QSPI_out spi{0}_out;\n" + \
 370                "            method Bit#(1) spi{0}_isint;"
 371
 372     def num_axi_regs32(self):
 373         return 13
 374
 375     def mkslow_peripheral(self):
 376         return "        Ifc_qspi spi{0} <-  mkqspi();"
 377
 378     def _mk_connection(self, name=None, count=0):
 379         return "spi{0}.slave"
 380
 381     def pinname_out(self, pname):
 382         return {'clk': 'out.clk_o',
 383                 'nss': 'out.ncs_o',
 384                 'mosi': 'out.io_o[0]',
 385                 'miso': 'out.io_o[1]',
 386                 }.get(pname, '')
 387
 388     def pinname_outen(self, pname):
 389         return {'clk': 1,
 390                 'nss': 1,
 391                 'mosi': 'out.io_enable[0]',
 392                 'miso': 'out.io_enable[1]',
 393                 }.get(pname, '')
 394
 395     def mk_pincon(self, name, count):
 396         ret = [PBase.mk_pincon(self, name, count)]
 397         # special-case for gpio in, store in a temporary vector
 398         plen = len(self.peripheral.pinspecs)
 399         ret.append("    // XXX NSS and CLK are hard-coded master")
 400         ret.append("    // TODO: must add spi slave-mode")
 401         ret.append("    // all ins done in one rule from 4-bitfield")
 402         ret.append("    rule con_%s%d_io_in;" % (name, count))
 403         ret.append("       {0}{1}.out.io_i({{".format(name, count))
 404         for idx, pname in enumerate(['mosi', 'miso']):
 405             sname = self.peripheral.pname(pname).format(count)
 406             ps = "pinmux.peripheral_side.%s_in" % sname
 407             ret.append("            {0},".format(ps))
 408         ret.append("            1'b0,1'b0")
 409         ret.append("        });")
 410         ret.append("    endrule")
 411         return '\n'.join(ret)
 412
 413
 414 class qspi(PBase):
 415
 416     def slowimport(self):
 417         return "        import qspi              :: *;"
 418
 419     def slowifdecl(self):
 420         return "            interface QSPI_out qspi{0}_out;\n" + \
 421                "            method Bit#(1) qspi{0}_isint;"
 422
 423     def num_axi_regs32(self):
 424         return 13
 425
 426     def mkslow_peripheral(self, size=0):
 427         return "        Ifc_qspi qspi{0} <-  mkqspi();"
 428
 429     def _mk_connection(self, name=None, count=0):
 430         return "qspi{0}.slave"
 431
 432     def pinname_out(self, pname):
 433         return {'ck': 'out.clk_o',
 434                 'nss': 'out.ncs_o',
 435                 'io0': 'out.io_o[0]',
 436                 'io1': 'out.io_o[1]',
 437                 'io2': 'out.io_o[2]',
 438                 'io3': 'out.io_o[3]',
 439                 }.get(pname, '')
 440
 441     def pinname_outen(self, pname):
 442         return {'ck': 1,
 443                 'nss': 1,
 444                 'io0': 'out.io_enable[0]',
 445                 'io1': 'out.io_enable[1]',
 446                 'io2': 'out.io_enable[2]',
 447                 'io3': 'out.io_enable[3]',
 448                 }.get(pname, '')
 449
 450     def mk_pincon(self, name, count):
 451         ret = [PBase.mk_pincon(self, name, count)]
 452         # special-case for gpio in, store in a temporary vector
 453         plen = len(self.peripheral.pinspecs)
 454         ret.append("    // XXX NSS and CLK are hard-coded master")
 455         ret.append("    // TODO: must add qspi slave-mode")
 456         ret.append("    // all ins done in one rule from 4-bitfield")
 457         ret.append("    rule con_%s%d_io_in;" % (name, count))
 458         ret.append("       {0}{1}.out.io_i({{".format(name, count))
 459         for i, p in enumerate(self.peripheral.pinspecs):
 460             typ = p['type']
 461             pname = p['name']
 462             if not pname.startswith('io'):
 463                 continue
 464             idx = pname[1:]
 465             n = name
 466             sname = self.peripheral.pname(pname).format(count)
 467             ps = "pinmux.peripheral_side.%s_in" % sname
 468             comma = '' if i == 5 else ','
 469             ret.append("            {0}{1}".format(ps, comma))
 470         ret.append("        });")
 471         ret.append("    endrule")
 472         return '\n'.join(ret)
 473
 474
 475 class pwm(PBase):
 476
 477     def slowimport(self):
 478         return "        import pwm::*;"
 479
 480     def slowifdecl(self):
 481         return "        interface PWMIO pwm{0}_io;"
 482
 483     def num_axi_regs32(self):
 484         return 4
 485
 486     def mkslow_peripheral(self, size=0):
 487         return "        Ifc_PWM_bus pwm{0} <- mkPWM_bus(sp_clock);"
 488
 489     def _mk_connection(self, name=None, count=0):
 490         return "pwm{0}.axi4_slave"
 491
 492     def pinname_out(self, pname):
 493         return {'out': 'pwm_io.pwm_o'}.get(pname, '')
 494
 495
 496 class gpio(PBase):
 497
 498     def slowimport(self):
 499         return "     import pinmux::*;\n" + \
 500                "     import mux::*;\n" + \
 501                "     import gpio::*;\n"
 502
 503     def slowifdeclmux(self):
 504         size = len(self.peripheral.pinspecs)
 505         return "    interface GPIO_config#(%d) pad_config{0};" % size
 506
 507     def num_axi_regs32(self):
 508         return 2
 509
 510     def axi_slave_idx(self, idx, name, ifacenum):
 511         """ generates AXI slave number definition, except
 512             GPIO also has a muxer per bank
 513         """
 514         name = name.upper()
 515         mname = 'mux' + name[4:]
 516         mname = mname.upper()
 517         print "AXIslavenum", name, mname
 518         (ret, x) = PBase.axi_slave_idx(self, idx, name, ifacenum)
 519         (ret2, x) = PBase.axi_slave_idx(self, idx + 1, mname, ifacenum)
 520         return ("%s\n%s" % (ret, ret2), 2)
 521
 522     def mkslow_peripheral(self, size=0):
 523         print "gpioslow", self.peripheral, dir(self.peripheral)
 524         size = len(self.peripheral.pinspecs)
 525         return "        MUX#(%d) mux{0} <- mkmux();\n" % size + \
 526                "        GPIO#(%d) gpio{0} <- mkgpio();" % size
 527
 528     def mk_connection(self, count):
 529         print "GPIO mk_conn", self.name, count
 530         res = []
 531         dname = self.mksuffix(self.name, count)
 532         for i, n in enumerate(['gpio' + dname, 'mux' + dname]):
 533             res.append(PBase.mk_connection(self, count, n))
 534         return '\n'.join(res)
 535
 536     def _mk_connection(self, name=None, count=0):
 537         n = self.mksuffix(name, count)
 538         if name.startswith('gpio'):
 539             return "gpio{0}.axi_slave".format(n)
 540         if name.startswith('mux'):
 541             return "mux{0}.axi_slave".format(n)
 542
 543     def mksuffix(self, name, i):
 544         if name.startswith('mux'):
 545             return name[3:]
 546         return name[4:]
 547
 548     def mk_cellconn(self, cellnum, name, count):
 549         ret = []
 550         bank = self.mksuffix(name, count)
 551         txt = "       pinmux.mux_lines.cell{0}_mux(mux{1}.mux_config.mux[{2}]);"
 552         for p in self.peripheral.pinspecs:
 553             ret.append(txt.format(cellnum, bank, p['name'][1:]))
 554             cellnum += 1
 555         return ("\n".join(ret), cellnum)
 556
 557     def pinname_out(self, pname):
 558         return "func.gpio_out[{0}]".format(pname[1:])
 559
 560     def pinname_outen(self, pname):
 561         return "func.gpio_out_en[{0}]".format(pname[1:])
 562
 563     def mk_pincon(self, name, count):
 564         ret = [PBase.mk_pincon(self, name, count)]
 565         # special-case for gpio in, store in a temporary vector
 566         plen = len(self.peripheral.pinspecs)
 567         ret.append("    rule con_%s%d_in;" % (name, count))
 568         ret.append("       Vector#({0},Bit#(1)) temp;".format(plen))
 569         for p in self.peripheral.pinspecs:
 570             typ = p['type']
 571             pname = p['name']
 572             idx = pname[1:]
 573             n = name
 574             sname = self.peripheral.pname(pname).format(count)
 575             ps = "pinmux.peripheral_side.%s_in" % sname
 576             ret.append("        temp[{0}]={1};".format(idx, ps))
 577         ret.append("        {0}.func.gpio_in(temp);".format(name))
 578         ret.append("    endrule")
 579         return '\n'.join(ret)
 580
 581
 582 axi_slave_declarations = """\
 583 typedef  0  SlowMaster;
 584 {0}
 585 typedef  TAdd#(LastGen_slave_num,`ifdef CLINT       1 `else 0 `endif )
 586               CLINT_slave_num;
 587 typedef  TAdd#(CLINT_slave_num  ,`ifdef PLIC        1 `else 0 `endif )
 588               Plic_slave_num;
 589 typedef  TAdd#(Plic_slave_num   ,`ifdef AXIEXP      1 `else 0 `endif )
 590               AxiExp1_slave_num;
 591 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
 592 """
 593
 594 pinmux_cellrule = """\
 595     rule connect_select_lines_pinmux;
 596 {0}
 597     endrule
 598 """
 599
 600
 601 class CallFn(object):
 602     def __init__(self, peripheral, name):
 603         self.peripheral = peripheral
 604         self.name = name
 605
 606     def __call__(self, *args):
 607         #print "__call__", self.name, self.peripheral.slow, args
 608         if not self.peripheral.slow:
 609             return ''
 610         return getattr(self.peripheral.slow, self.name)(*args[1:])
 611
 612
 613 class PeripheralIface(object):
 614     def __init__(self, ifacename):
 615         self.slow = None
 616         slow = slowfactory.getcls(ifacename)
 617         print "Iface", ifacename, slow
 618         if slow:
 619             self.slow = slow(ifacename)
 620             self.slow.peripheral = self
 621         for fname in ['slowimport', 'slowifdecl', 'slowifdeclmux',
 622                       'mkslow_peripheral',
 623                       'mk_connection', 'mk_cellconn', 'mk_pincon']:
 624             fn = CallFn(self, fname)
 625             setattr(self, fname, types.MethodType(fn, self))
 626
 627         #print "PeripheralIface"
 628         #print dir(self)
 629
 630     def mksuffix(self, name, i):
 631         if self.slow is None:
 632             return i
 633         return self.slow.mksuffix(name, i)
 634
 635     def axi_reg_def(self, start, count):
 636         if not self.slow:
 637             return ('', 0)
 638         return self.slow.axi_reg_def(start, self.ifacename, count)
 639
 640     def axi_slave_idx(self, start, count):
 641         if not self.slow:
 642             return ('', 0)
 643         return self.slow.axi_slave_idx(start, self.ifacename, count)
 644
 645     def axi_addr_map(self, count):
 646         if not self.slow:
 647             return ''
 648         return self.slow.axi_addr_map(self.ifacename, count)
 649
 650
 651 class PeripheralInterfaces(object):
 652     def __init__(self):
 653         pass
 654
 655     def slowimport(self, *args):
 656         ret = []
 657         for (name, count) in self.ifacecount:
 658             #print "slowimport", name, self.data[name].slowimport
 659             ret.append(self.data[name].slowimport())
 660         return '\n'.join(list(filter(None, ret)))
 661
 662     def slowifdeclmux(self, *args):
 663         ret = []
 664         for (name, count) in self.ifacecount:
 665             for i in range(count):
 666                 ret.append(self.data[name].slowifdeclmux().format(i, name))
 667         return '\n'.join(list(filter(None, ret)))
 668
 669     def slowifdecl(self, *args):
 670         ret = []
 671         for (name, count) in self.ifacecount:
 672             for i in range(count):
 673                 ret.append(self.data[name].slowifdecl().format(i, name))
 674         return '\n'.join(list(filter(None, ret)))
 675
 676     def axi_reg_def(self, *args):
 677         ret = []
 678         start = 0x00011100  # start of AXI peripherals address
 679         for (name, count) in self.ifacecount:
 680             for i in range(count):
 681                 x = self.data[name].axi_reg_def(start, i)
 682                 #print ("ifc", name, x)
 683                 (rdef, offs) = x
 684                 ret.append(rdef)
 685                 start += offs
 686         return '\n'.join(list(filter(None, ret)))
 687
 688     def axi_slave_idx(self, *args):
 689         ret = []
 690         start = 0
 691         for (name, count) in self.ifacecount:
 692             for i in range(count):
 693                 (rdef, offs) = self.data[name].axi_slave_idx(start, i)
 694                 #print ("ifc", name, rdef, offs)
 695                 ret.append(rdef)
 696                 start += offs
 697         ret.append("typedef %d LastGen_slave_num;" % (start - 1))
 698         decls = '\n'.join(list(filter(None, ret)))
 699         return axi_slave_declarations.format(decls)
 700
 701     def axi_addr_map(self, *args):
 702         ret = []
 703         for (name, count) in self.ifacecount:
 704             for i in range(count):
 705                 ret.append(self.data[name].axi_addr_map(i))
 706         return '\n'.join(list(filter(None, ret)))
 707
 708     def mkslow_peripheral(self, *args):
 709         ret = []
 710         for (name, count) in self.ifacecount:
 711             for i in range(count):
 712                 print "mkslow", name, count
 713                 x = self.data[name].mkslow_peripheral()
 714                 print name, count, x
 715                 suffix = self.data[name].mksuffix(name, i)
 716                 ret.append(x.format(suffix))
 717         return '\n'.join(list(filter(None, ret)))
 718
 719     def mk_connection(self, *args):
 720         ret = []
 721         for (name, count) in self.ifacecount:
 722             for i in range(count):
 723                 print "mk_conn", name, i
 724                 txt = self.data[name].mk_connection(i)
 725                 if name == 'gpioa':
 726                     print "txt", txt
 727                     print self.data[name].mk_connection
 728                 ret.append(txt)
 729         return '\n'.join(list(filter(None, ret)))
 730
 731     def mk_cellconn(self):
 732         ret = []
 733         cellcount = 0
 734         for (name, count) in self.ifacecount:
 735             for i in range(count):
 736                 res = self.data[name].mk_cellconn(cellcount, name, i)
 737                 if not res:
 738                     continue
 739                 (txt, cellcount) = res
 740                 ret.append(txt)
 741         ret = '\n'.join(list(filter(None, ret)))
 742         return pinmux_cellrule.format(ret)
 743
 744     def mk_pincon(self):
 745         ret = []
 746         for (name, count) in self.ifacecount:
 747             for i in range(count):
 748                 txt = self.data[name].mk_pincon(name, i)
 749                 ret.append(txt)
 750         return '\n'.join(list(filter(None, ret)))
 751
 752
 753 class PFactory(object):
 754     def getcls(self, name):
 755         for k, v in {'uart': uart,
 756                      'rs232': rs232,
 757                      'twi': twi,
 758                      'qspi': qspi,
 759                      'spi': spi,
 760                      'pwm': pwm,
 761                      'eint': eint,
 762                      'sd': sdmmc,
 763                      'gpio': gpio
 764                      }.items():
 765             if name.startswith(k):
 766                 return v
 767         return None
 768
 769
 770 slowfactory = PFactory()
 771
 772 if __name__ == '__main__':
 773     p = uart('uart')
 774     print p.slowimport()
 775     print p.slowifdecl()
 776     i = PeripheralIface('uart')
 777     print i, i.slow
 778     i = PeripheralIface('gpioa')
 779     print i, i.slow