bd479eaf4a12b5e2883ae7e1fc3c70f4c9889261
2 from copy
import deepcopy
6 def __init__(self
, name
):
9 def axibase(self
, name
, ifacenum
):
11 return "%(name)s%(ifacenum)dBase" % locals()
13 def axiend(self
, name
, ifacenum
):
15 return "%(name)s%(ifacenum)dEnd" % locals()
17 def axi_reg_def(self
, start
, name
, ifacenum
):
19 offs
= self
.num_axi_regs32() * 4 * 16
20 end
= start
+ offs
- 1
21 bname
= self
.axibase(name
, ifacenum
)
22 bend
= self
.axiend(name
, ifacenum
)
23 comment
= "%d 32-bit regs" % self
.num_axi_regs32()
24 return (" `define %(bname)s 'h%(start)08X\n"
25 " `define %(bend)s 'h%(end)08X // %(comment)s" % locals(),
28 def axi_slave_name(self
, name
, ifacenum
):
30 return "{0}{1}_slave_num".format(name
, ifacenum
)
32 def axi_slave_idx(self
, idx
, name
, ifacenum
):
33 name
= self
.axi_slave_name(name
, ifacenum
)
34 return ("typedef {0} {1};".format(idx
, name
), 1)
36 def axi_addr_map(self
, name
, ifacenum
):
37 bname
= self
.axibase(name
, ifacenum
)
38 bend
= self
.axiend(name
, ifacenum
)
39 name
= self
.axi_slave_name(name
, ifacenum
)
41 if(addr>=`{0} && addr<=`{1})
42 return tuple2(True,fromInteger(valueOf({2})));
43 else""".format(bname
, bend
, name
)
45 def mk_pincon(self
, name
, count
):
46 # TODO: really should be using bsv.interface_decl.Interfaces
47 # pin-naming rules.... logic here is hard-coded to duplicate
48 # it (see Interface.__init__ outen)
50 for p
in self
.peripheral
.pinspecs
:
53 #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
54 n
= name
# "{0}{1}".format(self.name, self.mksuffix(name, count))
55 ret
.append(" //%s %s" % (n
, str(p
)))
56 sname
= self
.peripheral
.pname(pname
).format(count
)
57 ps
= "pinmux.peripheral_side.%s" % sname
58 if typ
== 'out' or typ
== 'inout':
59 ret
.append(" rule con_%s%d_%s_out;" % (name
, count
, pname
))
60 fname
= self
.pinname_out(pname
)
66 n_
= "{0}{1}".format(n
, count
)
67 ret
.append(" {0}({1}.{2});".format(ps_
, n_
, fname
))
70 fname
= self
.pinname_outen(pname
)
72 if isinstance(fname
, str):
73 fname
= "{0}{1}.{2}".format(n
, count
, fname
)
74 fname
= self
.pinname_tweak(pname
, 'outen', fname
)
75 ret
.append(" {0}_outen({1});".format(ps
, fname
))
76 ret
.append(" endrule")
77 if typ
== 'in' or typ
== 'inout':
78 fname
= self
.pinname_in(pname
)
85 " rule con_%s%d_%s_in;" %
87 n_
= "{0}{1}".format(n
, count
)
88 ret
.append(" {1}.{2}({0});".format(ps_
, n_
, fname
))
89 ret
.append(" endrule")
92 def mk_cellconn(self
, *args
):
95 def mkslow_peripheral(self
, size
=0):
98 def mksuffix(self
, name
, i
):
101 def __mk_connection(self
, con
, aname
):
102 txt
= " mkConnection (slow_fabric.v_to_slaves\n" + \
103 " [fromInteger(valueOf({1}))],\n" + \
106 print "PBase __mk_connection", self
.name
, aname
109 return txt
.format(con
, aname
)
111 def mk_connection(self
, count
, name
=None):
114 print "PBase mk_conn", self
.name
, count
115 aname
= self
.axi_slave_name(name
, count
)
116 #dname = self.mksuffix(name, count)
117 #dname = "{0}{1}".format(name, dname)
118 con
= self
._mk
_connection
(name
, count
).format(count
, aname
)
119 return self
.__mk
_connection
(con
, aname
)
121 def _mk_connection(self
, name
=None, count
=0):
124 def pinname_out(self
, pname
):
127 def pinname_in(self
, pname
):
130 def pinname_outen(self
, pname
):
133 def pinname_tweak(self
, pname
, typ
, txt
):
139 def slowimport(self
):
140 return " import Uart16550 :: *;"
142 def slowifdecl(self
):
143 return " interface RS232_PHY_Ifc uart{0}_coe;\n" + \
144 " method Bit#(1) uart{0}_intr;"
146 def num_axi_regs32(self
):
149 def mkslow_peripheral(self
, size
=0):
150 return " Uart16550_AXI4_Lite_Ifc uart{0} <- \n" + \
151 " mkUart16550(clocked_by uart_clock,\n" + \
152 " reset_by uart_reset, sp_clock, sp_reset);"
154 def _mk_connection(self
, name
=None, count
=0):
155 return "uart{0}.slave_axi_uart"
157 def pinname_out(self
, pname
):
158 return {'tx': 'coe_rs232.sout'}.get(pname
, '')
160 def pinname_in(self
, pname
):
161 return {'rx': 'coe_rs232.sin'}.get(pname
, '')
166 def slowimport(self
):
167 return " import Uart_bs::*;\n" + \
168 " import RS232_modified::*;"
170 def slowifdecl(self
):
171 return " interface RS232 uart{0}_coe;"
173 def num_axi_regs32(self
):
176 def mkslow_peripheral(self
, size
=0):
177 return " //Ifc_Uart_bs uart{0} <-" + \
178 " // mkUart_bs(clocked_by uart_clock,\n" + \
179 " // reset_by uart_reset,sp_clock, sp_reset);" +\
180 " Ifc_Uart_bs uart{0} <-" + \
181 " mkUart_bs(clocked_by sp_clock,\n" + \
182 " reset_by sp_reset, sp_clock, sp_reset);"
184 def _mk_connection(self
, name
=None, count
=0):
185 return "uart{0}.slave_axi_uart"
187 def pinname_out(self
, pname
):
188 return {'tx': 'coe_rs232.sout'}.get(pname
, '')
190 def pinname_in(self
, pname
):
191 return {'rx': 'coe_rs232.sin'}.get(pname
, '')
196 def slowimport(self
):
197 return " import I2C_top :: *;"
199 def slowifdecl(self
):
200 return " interface I2C_out twi{0}_out;\n" + \
201 " method Bit#(1) twi{0}_isint;"
203 def num_axi_regs32(self
):
206 def mkslow_peripheral(self
, size
=0):
207 return " I2C_IFC twi{0} <- mkI2CController();"
209 def _mk_connection(self
, name
=None, count
=0):
210 return "twi{0}.slave_i2c_axi"
212 def pinname_out(self
, pname
):
213 return {'sda': 'out.sda_out',
214 'scl': 'out.scl_out'}.get(pname
, '')
216 def pinname_in(self
, pname
):
217 return {'sda': 'out.sda_in',
218 'scl': 'out.scl_in'}.get(pname
, '')
220 def pinname_outen(self
, pname
):
221 return {'sda': 'out.sda_outen',
222 'scl': 'out.scl_outen'}.get(pname
, '')
224 def pinname_tweak(self
, pname
, typ
, txt
):
226 return "pack({0})".format(txt
)
232 def slowimport(self
):
233 return " import qspi :: *;"
235 def slowifdecl(self
):
236 return " interface QSPI_out qspi{0}_out;\n" + \
237 " method Bit#(1) qspi{0}_isint;"
239 def num_axi_regs32(self
):
242 def mkslow_peripheral(self
, size
=0):
243 return " Ifc_qspi qspi{0} <- mkqspi();"
245 def _mk_connection(self
, name
=None, count
=0):
246 return "qspi{0}.slave"
248 def pinname_out(self
, pname
):
249 return {'ck': 'out.clk_o',
251 'io0': 'out.io_o[0]',
252 'io1': 'out.io_o[1]',
253 'io2': 'out.io_o[2]',
254 'io3': 'out.io_o[3]',
257 def pinname_outen(self
, pname
):
260 'io0': 'out.io_enable[0]',
261 'io1': 'out.io_enable[1]',
262 'io2': 'out.io_enable[2]',
263 'io3': 'out.io_enable[3]',
266 def mk_pincon(self
, name
, count
):
267 ret
= [PBase
.mk_pincon(self
, name
, count
)]
268 # special-case for gpio in, store in a temporary vector
269 plen
= len(self
.peripheral
.pinspecs
)
270 ret
.append(" // XXX NSS and CLK are hard-coded master")
271 ret
.append(" // TODO: must add qspi slave-mode")
272 ret
.append(" // all ins done in one rule from 4-bitfield")
273 ret
.append(" rule con_%s%d_io_in;" % (name
, count
))
274 ret
.append(" {0}{1}.out.io_i({{".format(name
, count
))
275 for i
, p
in enumerate(self
.peripheral
.pinspecs
):
278 if not pname
.startswith('io'):
282 sname
= self
.peripheral
.pname(pname
).format(count
)
283 ps
= "pinmux.peripheral_side.%s_in" % sname
284 comma
= '' if i
== 5 else ','
285 ret
.append(" {0}{1}".format(ps
, comma
))
287 ret
.append(" endrule")
288 return '\n'.join(ret
)
293 def slowimport(self
):
294 return " import pwm::*;"
296 def slowifdecl(self
):
297 return " interface PWMIO pwm{0}_o;"
299 def num_axi_regs32(self
):
302 def mkslow_peripheral(self
, size
=0):
303 return " Ifc_PWM_bus pwm{0}_bus <- mkPWM_bus(sp_clock);"
305 def _mk_connection(self
, name
=None, count
=0):
306 return "pwm{0}_bus.axi4_slave"
308 def pinname_out(self
, pname
):
309 return {'out': 'pwm_io.pwm_o'}.get(pname
, '')
314 def slowimport(self
):
315 return " import pinmux::*;\n" + \
316 " import mux::*;\n" + \
319 def slowifdecl(self
):
320 return " interface GPIO_config#({1}) pad_config{0};"
322 def num_axi_regs32(self
):
325 def axi_slave_idx(self
, idx
, name
, ifacenum
):
326 """ generates AXI slave number definition, except
327 GPIO also has a muxer per bank
330 mname
= 'mux' + name
[4:]
331 mname
= mname
.upper()
332 print "AXIslavenum", name
, mname
333 (ret
, x
) = PBase
.axi_slave_idx(self
, idx
, name
, ifacenum
)
334 (ret2
, x
) = PBase
.axi_slave_idx(self
, idx
, mname
, ifacenum
)
335 return ("%s\n%s" % (ret
, ret2
), 2)
337 def mkslow_peripheral(self
, size
=0):
338 print "gpioslow", self
.peripheral
, dir(self
.peripheral
)
339 size
= len(self
.peripheral
.pinspecs
)
340 return " MUX#(%d) mux{0} <- mkmux();\n" % size
+ \
341 " GPIO#(%d) gpio{0} <- mkgpio();" % size
343 def mk_connection(self
, count
):
344 print "GPIO mk_conn", self
.name
, count
346 dname
= self
.mksuffix(self
.name
, count
)
347 for i
, n
in enumerate(['gpio' + dname
, 'mux' + dname
]):
348 res
.append(PBase
.mk_connection(self
, count
, n
))
349 return '\n'.join(res
)
351 def _mk_connection(self
, name
=None, count
=0):
352 n
= self
.mksuffix(name
, count
)
353 if name
.startswith('gpio'):
354 return "gpio{0}.axi_slave".format(n
)
355 if name
.startswith('mux'):
356 return "mux{0}.axi_slave".format(n
)
358 def mksuffix(self
, name
, i
):
359 if name
.startswith('mux'):
363 def mk_cellconn(self
, cellnum
, name
, count
):
365 bank
= self
.mksuffix(name
, count
)
366 txt
= " pinmux.mux_lines.cell{0}_mux(mux{1}.mux_config.mux[{2}]);"
367 for p
in self
.peripheral
.pinspecs
:
368 ret
.append(txt
.format(cellnum
, bank
, p
['name'][1:]))
370 return ("\n".join(ret
), cellnum
)
372 def pinname_out(self
, pname
):
373 return "func.gpio_out[{0}]".format(pname
[1:])
375 def pinname_outen(self
, pname
):
376 return {'sda': 'out.sda_outen',
377 'scl': 'out.scl_outen'}.get(pname
, '')
379 def mk_pincon(self
, name
, count
):
380 ret
= [PBase
.mk_pincon(self
, name
, count
)]
381 # special-case for gpio in, store in a temporary vector
382 plen
= len(self
.peripheral
.pinspecs
)
383 ret
.append(" rule con_%s%d_in;" % (name
, count
))
384 ret
.append(" Vector#({0},Bit#(1)) temp;".format(plen
))
385 for p
in self
.peripheral
.pinspecs
:
390 sname
= self
.peripheral
.pname(pname
).format(count
)
391 ps
= "pinmux.peripheral_side.%s_in" % sname
392 ret
.append(" temp[{0}]={1};".format(idx
, ps
))
393 ret
.append(" {0}.func.gpio_in(temp);".format(name
))
394 ret
.append(" endrule")
395 return '\n'.join(ret
)
398 axi_slave_declarations
= """\
399 typedef 0 SlowMaster;
401 typedef TAdd#(LastGen_slave_num,`ifdef CLINT 1 `else 0 `endif )
403 typedef TAdd#(CLINT_slave_num ,`ifdef PLIC 1 `else 0 `endif )
405 typedef TAdd#(Plic_slave_num ,`ifdef AXIEXP 1 `else 0 `endif )
407 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
410 pinmux_cellrule
= """\
411 rule connect_select_lines_pinmux;
417 class CallFn(object):
418 def __init__(self
, peripheral
, name
):
419 self
.peripheral
= peripheral
422 def __call__(self
, *args
):
423 #print "__call__", self.name, self.peripheral.slow, args
424 if not self
.peripheral
.slow
:
426 return getattr(self
.peripheral
.slow
, self
.name
)(*args
[1:])
429 class PeripheralIface(object):
430 def __init__(self
, ifacename
):
432 slow
= slowfactory
.getcls(ifacename
)
433 print "Iface", ifacename
, slow
435 self
.slow
= slow(ifacename
)
436 self
.slow
.peripheral
= self
437 for fname
in ['slowimport', 'slowifdecl', 'mkslow_peripheral',
438 'mk_connection', 'mk_cellconn', 'mk_pincon']:
439 fn
= CallFn(self
, fname
)
440 setattr(self
, fname
, types
.MethodType(fn
, self
))
442 #print "PeripheralIface"
445 def mksuffix(self
, name
, i
):
446 if self
.slow
is None:
448 return self
.slow
.mksuffix(name
, i
)
450 def axi_reg_def(self
, start
, count
):
453 return self
.slow
.axi_reg_def(start
, self
.ifacename
, count
)
455 def axi_slave_idx(self
, start
, count
):
458 return self
.slow
.axi_slave_idx(start
, self
.ifacename
, count
)
460 def axi_addr_map(self
, count
):
463 return self
.slow
.axi_addr_map(self
.ifacename
, count
)
466 class PeripheralInterfaces(object):
470 def slowimport(self
, *args
):
472 for (name
, count
) in self
.ifacecount
:
473 #print "slowimport", name, self.data[name].slowimport
474 ret
.append(self
.data
[name
].slowimport())
475 return '\n'.join(list(filter(None, ret
)))
477 def slowifdecl(self
, *args
):
479 for (name
, count
) in self
.ifacecount
:
480 for i
in range(count
):
481 ret
.append(self
.data
[name
].slowifdecl().format(i
, name
))
482 return '\n'.join(list(filter(None, ret
)))
484 def axi_reg_def(self
, *args
):
486 start
= 0x00011100 # start of AXI peripherals address
487 for (name
, count
) in self
.ifacecount
:
488 for i
in range(count
):
489 x
= self
.data
[name
].axi_reg_def(start
, i
)
490 #print ("ifc", name, x)
494 return '\n'.join(list(filter(None, ret
)))
496 def axi_slave_idx(self
, *args
):
499 for (name
, count
) in self
.ifacecount
:
500 for i
in range(count
):
501 (rdef
, offs
) = self
.data
[name
].axi_slave_idx(start
, i
)
502 #print ("ifc", name, rdef, offs)
505 ret
.append("typedef %d LastGen_slave_num;" % (start
- 1))
506 decls
= '\n'.join(list(filter(None, ret
)))
507 return axi_slave_declarations
.format(decls
)
509 def axi_addr_map(self
, *args
):
511 for (name
, count
) in self
.ifacecount
:
512 for i
in range(count
):
513 ret
.append(self
.data
[name
].axi_addr_map(i
))
514 return '\n'.join(list(filter(None, ret
)))
516 def mkslow_peripheral(self
, *args
):
518 for (name
, count
) in self
.ifacecount
:
519 for i
in range(count
):
520 print "mkslow", name
, count
521 x
= self
.data
[name
].mkslow_peripheral()
523 suffix
= self
.data
[name
].mksuffix(name
, i
)
524 ret
.append(x
.format(suffix
))
525 return '\n'.join(list(filter(None, ret
)))
527 def mk_connection(self
, *args
):
529 for (name
, count
) in self
.ifacecount
:
530 for i
in range(count
):
531 print "mk_conn", name
, i
532 txt
= self
.data
[name
].mk_connection(i
)
535 print self
.data
[name
].mk_connection
537 return '\n'.join(list(filter(None, ret
)))
539 def mk_cellconn(self
):
542 for (name
, count
) in self
.ifacecount
:
543 for i
in range(count
):
544 res
= self
.data
[name
].mk_cellconn(cellcount
, name
, i
)
547 (txt
, cellcount
) = res
549 ret
= '\n'.join(list(filter(None, ret
)))
550 return pinmux_cellrule
.format(ret
)
554 for (name
, count
) in self
.ifacecount
:
555 for i
in range(count
):
556 txt
= self
.data
[name
].mk_pincon(name
, i
)
558 return '\n'.join(list(filter(None, ret
)))
561 class PFactory(object):
562 def getcls(self
, name
):
563 for k
, v
in {'uart': uart
,
570 if name
.startswith(k
):
575 slowfactory
= PFactory()
577 if __name__
== '__main__':
581 i
= PeripheralIface('uart')
583 i
= PeripheralIface('gpioa')