bit of a mess, adding mk_connection to deal with double-interface mux+gpio
[pinmux.git] / src / bsv / peripheral_gen.py
1 import types
2 from copy import deepcopy
3
4
5 class PBase(object):
6 def __init__(self, name):
7 self.name = name
8
9 def axibase(self, name, ifacenum):
10 name = name.upper()
11 return "%(name)s%(ifacenum)dBase" % locals()
12
13 def axiend(self, name, ifacenum):
14 name = name.upper()
15 return "%(name)s%(ifacenum)dEnd" % locals()
16
17 def axi_reg_def(self, start, name, ifacenum):
18 name = name.upper()
19 offs = self.num_axi_regs32() * 4 * 16
20 end = start + offs - 1
21 bname = self.axibase(name, ifacenum)
22 bend = self.axiend(name, ifacenum)
23 comment = "%d 32-bit regs" % self.num_axi_regs32()
24 return (" `define%(bname)s 'h%(start)08X\n"
25 " `define%(bend)s 'h%(end)08X // %(comment)s" % locals(),
26 offs)
27
28 def axi_slave_name(self, name, ifacenum):
29 name = name.upper()
30 return "{0}{1}_slave_num".format(name, ifacenum)
31
32 def axi_slave_idx(self, idx, name, ifacenum):
33 name = self.axi_slave_name(name, ifacenum)
34 return ("typedef {0} {1};".format(idx, name), 1)
35
36 def axi_addr_map(self, name, ifacenum):
37 bname = self.axibase(name, ifacenum)
38 bend = self.axiend(name, ifacenum)
39 name = self.axi_slave_name(name, ifacenum)
40 return """\
41 if(addr>=`{0} && addr<=`{1})
42 return tuple2(True,fromInteger(valueOf({2})));
43 else""".format(bname, bend, name)
44
45 def mkslow_peripheral(self):
46 return ''
47
48 def __mk_connection(self, con, aname):
49 txt = " mkConnection (slow_fabric.v_to_slaves\n" + \
50 " [fromInteger(valueOf({1}))],\n" + \
51 " {0});"
52
53 print "PBase __mk_connection", self.name, aname
54 if not con:
55 return ''
56 return txt.format(con, aname)
57
58 def mk_connection(self, count, name=None):
59 if name is None:
60 name = self.name
61 print "PBase mk_conn", self.name, count
62 aname = self.axi_slave_name(name, count)
63 con = self._mk_connection(name).format(count, aname)
64 return self.__mk_connection(con, aname)
65
66 def _mk_connection(self, name=None):
67 return ''
68
69
70 class uart(PBase):
71
72 def slowimport(self):
73 return " import Uart16550 :: *;"
74
75 def slowifdecl(self):
76 return " interface RS232_PHY_Ifc uart{0}_coe;\n" + \
77 " method Bit#(1) uart{0}_intr;"
78
79 def num_axi_regs32(self):
80 return 8
81
82 def mkslow_peripheral(self):
83 return " Uart16550_AXI4_Lite_Ifc uart{0} <- \n" + \
84 " mkUart16550(clocked_by uart_clock,\n" + \
85 " reset_by uart_reset, sp_clock, sp_reset);"
86
87 def _mk_connection(self, name=None):
88 return "uart{0}.slave_axi_uart"
89
90
91
92 class rs232(PBase):
93
94 def slowimport(self):
95 return " import Uart_bs::*;\n" + \
96 " import RS232_modified::*;"
97
98 def slowifdecl(self):
99 return " interface RS232 uart{0}_coe;"
100
101 def num_axi_regs32(self):
102 return 2
103
104 def mkslow_peripheral(self):
105 return " //Ifc_Uart_bs uart{0} <-" + \
106 " // mkUart_bs(clocked_by uart_clock,\n" + \
107 " // reset_by uart_reset,sp_clock, sp_reset);" +\
108 " Ifc_Uart_bs uart{0} <-" + \
109 " mkUart_bs(clocked_by sp_clock,\n" + \
110 " reset_by sp_reset, sp_clock, sp_reset);"
111
112 def _mk_connection(self, name=None):
113 return "uart{0}.slave_axi_uart"
114
115
116 class twi(PBase):
117
118 def slowimport(self):
119 return " import I2C_top :: *;"
120
121 def slowifdecl(self):
122 return " interface I2C_out i2c{0}_out;\n" + \
123 " method Bit#(1) i2c{0}_isint;"
124
125 def num_axi_regs32(self):
126 return 8
127
128 def mkslow_peripheral(self):
129 return " I2C_IFC i2c{0} <- mkI2CController();"
130
131 def _mk_connection(self, name=None):
132 return "i2c{0}.slave_i2c_axi"
133
134
135 class qspi(PBase):
136
137 def slowimport(self):
138 return " import qspi :: *;"
139
140 def slowifdecl(self):
141 return " interface QSPI_out qspi{0}_out;\n" + \
142 " method Bit#(1) qspi{0}_isint;"
143
144 def num_axi_regs32(self):
145 return 13
146
147 def mkslow_peripheral(self):
148 return " Ifc_qspi qspi{0} <- mkqspi();"
149
150 def _mk_connection(self, name=None):
151 return "qspi{0}.slave"
152
153
154 class pwm(PBase):
155
156 def slowimport(self):
157 return " import pwm::*;"
158
159 def slowifdecl(self):
160 return " interface PWMIO pwm{0}_o;"
161
162 def num_axi_regs32(self):
163 return 4
164
165 def mkslow_peripheral(self):
166 return " Ifc_PWM_bus pwm{0}_bus <- mkPWM_bus(sp_clock);"
167
168 def _mk_connection(self, name=None):
169 return "pwm{0}_bus.axi4_slave"
170
171
172 class gpio(PBase):
173
174 def slowimport(self):
175 return " import pinmux::*;\n" + \
176 " import mux::*;\n" + \
177 " import gpio::*;\n"
178
179 def slowifdecl(self):
180 return " interface GPIO_config#({1}) pad_config{0};"
181
182 def num_axi_regs32(self):
183 return 2
184
185 def axi_slave_idx(self, idx, name, ifacenum):
186 """ generates AXI slave number definition, except
187 GPIO also has a muxer per bank
188 """
189 name = name.upper()
190 (ret, x) = PBase.axi_slave_idx(self, idx, name, ifacenum)
191 (ret2, x) = PBase.axi_slave_idx(self, idx, "mux", ifacenum)
192 return ("%s\n%s" % (ret, ret2), 2)
193
194 def mkslow_peripheral(self):
195 return " MUX#(%(name)s) mux{0} <- mkmux();\n" + \
196 " GPIO#(%(name)s) gpio{0} <- mkgpio();" % \
197 {'name': self.name}
198
199 def mk_connection(self, count):
200 print "GPIO mk_conn", self.name, count
201 res = []
202 for i, n in enumerate(['gpio', 'mux']):
203 res.append(PBase.mk_connection(self, count, n))
204 return '\n'.join(res)
205
206 def _mk_connection(self, name=None):
207 if name.startswith('gpio'):
208 return "gpio{0}.axi_slave"
209 if name.startswith('mux'):
210 return "mux{0}.axi_slave"
211
212
213 axi_slave_declarations = """\
214 typedef 0 SlowMaster;
215 {0}
216 typedef TAdd#(LastGen_slave_num,`ifdef CLINT 1 `else 0 `endif )
217 CLINT_slave_num;
218 typedef TAdd#(CLINT_slave_num ,`ifdef PLIC 1 `else 0 `endif )
219 Plic_slave_num;
220 typedef TAdd#(Plic_slave_num ,`ifdef AXIEXP 1 `else 0 `endif )
221 AxiExp1_slave_num;
222 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
223 """
224
225
226 class CallFn(object):
227 def __init__(self, peripheral, name):
228 self.peripheral = peripheral
229 self.name = name
230
231 def __call__(self, *args):
232 print "__call__", self.name, self.peripheral.slow, args
233 if not self.peripheral.slow:
234 return ''
235 return getattr(self.peripheral.slow, self.name)(*args[1:])
236
237
238 class PeripheralIface(object):
239 def __init__(self, ifacename):
240 self.slow = None
241 slow = slowfactory.getcls(ifacename)
242 print "Iface", ifacename, slow
243 if slow:
244 self.slow = slow(ifacename)
245 for fname in ['slowimport', 'slowifdecl', 'mkslow_peripheral',
246 'mk_connection']:
247 fn = CallFn(self, fname)
248 setattr(self, fname, types.MethodType(fn, self))
249
250 #print "PeripheralIface"
251 #print dir(self)
252
253 def axi_reg_def(self, start, count):
254 if not self.slow:
255 return ('', 0)
256 return self.slow.axi_reg_def(start, self.ifacename, count)
257
258 def axi_slave_idx(self, start, count):
259 if not self.slow:
260 return ('', 0)
261 return self.slow.axi_slave_idx(start, self.ifacename, count)
262
263 def axi_addr_map(self, count):
264 if not self.slow:
265 return ''
266 return self.slow.axi_addr_map(self.ifacename, count)
267
268
269 class PeripheralInterfaces(object):
270 def __init__(self):
271 pass
272
273 def slowimport(self, *args):
274 ret = []
275 for (name, count) in self.ifacecount:
276 #print "slowimport", name, self.data[name].slowimport
277 ret.append(self.data[name].slowimport())
278 return '\n'.join(list(filter(None, ret)))
279
280 def slowifdecl(self, *args):
281 ret = []
282 for (name, count) in self.ifacecount:
283 for i in range(count):
284 ret.append(self.data[name].slowifdecl().format(i, name))
285 return '\n'.join(list(filter(None, ret)))
286
287 def axi_reg_def(self, *args):
288 ret = []
289 start = 0x00011100 # start of AXI peripherals address
290 for (name, count) in self.ifacecount:
291 for i in range(count):
292 x = self.data[name].axi_reg_def(start, i)
293 #print ("ifc", name, x)
294 (rdef, offs) = x
295 ret.append(rdef)
296 start += offs
297 return '\n'.join(list(filter(None, ret)))
298
299 def axi_slave_idx(self, *args):
300 ret = []
301 start = 0
302 for (name, count) in self.ifacecount:
303 for i in range(count):
304 (rdef, offs) = self.data[name].axi_slave_idx(start, i)
305 #print ("ifc", name, rdef, offs)
306 ret.append(rdef)
307 start += offs
308 ret.append("typedef %d LastGen_slave_num" % (start - 1))
309 decls = '\n'.join(list(filter(None, ret)))
310 return axi_slave_declarations.format(decls)
311
312 def axi_addr_map(self, *args):
313 ret = []
314 for (name, count) in self.ifacecount:
315 for i in range(count):
316 ret.append(self.data[name].axi_addr_map(i))
317 return '\n'.join(list(filter(None, ret)))
318
319 def mkslow_peripheral(self, *args):
320 ret = []
321 for (name, count) in self.ifacecount:
322 for i in range(count):
323 x = self.data[name].mkslow_peripheral()
324 print name, count, x
325 ret.append(x.format(i))
326 return '\n'.join(list(filter(None, ret)))
327
328 def mk_connection(self, *args):
329 ret = []
330 for (name, count) in self.ifacecount:
331 for i in range(count):
332 print "mk_conn", name, i
333 txt = self.data[name].mk_connection(i)
334 if name == 'gpioa':
335 print "txt", txt
336 print self.data[name].mk_connection
337 ret.append(txt)
338 return '\n'.join(list(filter(None, ret)))
339
340
341 class PFactory(object):
342 def getcls(self, name):
343 for k, v in {'uart': uart,
344 'rs232': rs232,
345 'twi': twi,
346 'qspi': qspi,
347 'pwm': pwm,
348 'gpio': gpio
349 }.items():
350 if name.startswith(k):
351 return v
352 return None
353
354
355 slowfactory = PFactory()
356
357 if __name__ == '__main__':
358 p = uart('uart')
359 print p.slowimport()
360 print p.slowifdecl()
361 i = PeripheralIface('uart')
362 print i, i.slow
363 i = PeripheralIface('gpioa')
364 print i, i.slow