src/bsv/peripheral_gen.py

   1 import types
   2 from copy import deepcopy
   3
   4
   5 class PBase(object):
   6     def __init__(self, name):
   7         self.name = name
   8
   9     def axibase(self, name, ifacenum):
  10         name = name.upper()
  11         return "%(name)s%(ifacenum)dBase" % locals()
  12
  13     def axiend(self, name, ifacenum):
  14         name = name.upper()
  15         return "%(name)s%(ifacenum)dEnd" % locals()
  16
  17     def axi_reg_def(self, start, name, ifacenum):
  18         name = name.upper()
  19         offs = self.num_axi_regs32() * 4 * 16
  20         end = start + offs - 1
  21         bname = self.axibase(name, ifacenum)
  22         bend = self.axiend(name, ifacenum)
  23         comment = "%d 32-bit regs" % self.num_axi_regs32()
  24         return ("    `define %(bname)s 'h%(start)08X\n"
  25                 "    `define %(bend)s  'h%(end)08X // %(comment)s" % locals(),
  26                 offs)
  27
  28     def axi_slave_name(self, name, ifacenum):
  29         name = name.upper()
  30         return "{0}{1}_slave_num".format(name, ifacenum)
  31
  32     def axi_slave_idx(self, idx, name, ifacenum):
  33         name = self.axi_slave_name(name, ifacenum)
  34         return ("typedef {0} {1};".format(idx, name), 1)
  35
  36     def axi_addr_map(self, name, ifacenum):
  37         bname = self.axibase(name, ifacenum)
  38         bend = self.axiend(name, ifacenum)
  39         name = self.axi_slave_name(name, ifacenum)
  40         return """\
  41         if(addr>=`{0} && addr<=`{1})
  42             return tuple2(True,fromInteger(valueOf({2})));
  43         else""".format(bname, bend, name)
  44
  45     def mk_pincon(self, name, count):
  46         # TODO: really should be using bsv.interface_decl.Interfaces
  47         # pin-naming rules.... logic here is hard-coded to duplicate
  48         # it (see Interface.__init__ outen)
  49         ret = []
  50         for p in self.peripheral.pinspecs:
  51             typ = p['type']
  52             pname = p['name']
  53             #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
  54             n = name  # "{0}{1}".format(self.name, self.mksuffix(name, count))
  55             ret.append("    //%s %s" % (n, str(p)))
  56             sname = self.peripheral.pname(pname).format(count)
  57             ps = "pinmux.peripheral_side.%s" % sname
  58             if typ == 'out' or typ == 'inout':
  59                 ret.append("    rule con_%s%d_%s_out;" % (name, count, pname))
  60                 fname = self.pinname_out(pname)
  61                 if fname:
  62                     if p.get('outen'):
  63                         ps_ = ps + '_out'
  64                     else:
  65                         ps_ = ps
  66                     n_ = "{0}{1}".format(n, count)
  67                     ret.append("      {0}({1}.{2});".format(ps_, n_, fname))
  68                 fname = None
  69                 if p.get('outen'):
  70                     fname = self.pinname_outen(pname)
  71                 if fname:
  72                     if isinstance(fname, str):
  73                         fname = "{0}{1}.{2}".format(n, count, fname)
  74                     fname = self.pinname_tweak(pname, 'outen', fname)
  75                     ret.append("      {0}_outen({1});".format(ps, fname))
  76                 ret.append("    endrule")
  77             if typ == 'in' or typ == 'inout':
  78                 fname = self.pinname_in(pname)
  79                 if fname:
  80                     if p.get('outen'):
  81                         ps_ = ps + '_in'
  82                     else:
  83                         ps_ = ps
  84                     ret.append(
  85                         "    rule con_%s%d_%s_in;" %
  86                         (name, count, pname))
  87                     n_ = "{0}{1}".format(n, count)
  88                     ret.append("      {1}.{2}({0});".format(ps_, n_, fname))
  89                     ret.append("    endrule")
  90         return '\n'.join(ret)
  91
  92     def mk_cellconn(self, *args):
  93         return ''
  94
  95     def mkslow_peripheral(self, size=0):
  96         return ''
  97
  98     def mksuffix(self, name, i):
  99         return i
 100
 101     def __mk_connection(self, con, aname):
 102         txt = "        mkConnection (slow_fabric.v_to_slaves\n" + \
 103             "                    [fromInteger(valueOf({1}))],\n" + \
 104             "                    {0});"
 105
 106         print "PBase __mk_connection", self.name, aname
 107         if not con:
 108             return ''
 109         return txt.format(con, aname)
 110
 111     def mk_connection(self, count, name=None):
 112         if name is None:
 113             name = self.name
 114         print "PBase mk_conn", self.name, count
 115         aname = self.axi_slave_name(name, count)
 116         #dname = self.mksuffix(name, count)
 117         #dname = "{0}{1}".format(name, dname)
 118         con = self._mk_connection(name, count).format(count, aname)
 119         return self.__mk_connection(con, aname)
 120
 121     def _mk_connection(self, name=None, count=0):
 122         return ''
 123
 124     def pinname_out(self, pname):
 125         return ''
 126
 127     def pinname_in(self, pname):
 128         return ''
 129
 130     def pinname_outen(self, pname):
 131         return ''
 132
 133     def pinname_tweak(self, pname, typ, txt):
 134         return txt
 135
 136
 137 class uart(PBase):
 138
 139     def slowimport(self):
 140         return "          import Uart16550         :: *;"
 141
 142     def slowifdecl(self):
 143         return "            interface RS232_PHY_Ifc uart{0}_coe;\n" + \
 144                "            method Bit#(1) uart{0}_intr;"
 145
 146     def num_axi_regs32(self):
 147         return 8
 148
 149     def mkslow_peripheral(self, size=0):
 150         return "        Uart16550_AXI4_Lite_Ifc uart{0} <- \n" + \
 151                "                mkUart16550(clocked_by uart_clock,\n" + \
 152                "                    reset_by uart_reset, sp_clock, sp_reset);"
 153
 154     def _mk_connection(self, name=None, count=0):
 155         return "uart{0}.slave_axi_uart"
 156
 157     def pinname_out(self, pname):
 158         return {'tx': 'coe_rs232.sout'}.get(pname, '')
 159
 160     def pinname_in(self, pname):
 161         return {'rx': 'coe_rs232.sin'}.get(pname, '')
 162
 163
 164 class rs232(PBase):
 165
 166     def slowimport(self):
 167         return "        import Uart_bs::*;\n" + \
 168                "        import RS232_modified::*;"
 169
 170     def slowifdecl(self):
 171         return "            interface RS232 uart{0}_coe;"
 172
 173     def num_axi_regs32(self):
 174         return 2
 175
 176     def mkslow_peripheral(self, size=0):
 177         return "        //Ifc_Uart_bs uart{0} <-" + \
 178                "        //       mkUart_bs(clocked_by uart_clock,\n" + \
 179                "        //          reset_by uart_reset,sp_clock, sp_reset);" +\
 180                "        Ifc_Uart_bs uart{0} <-" + \
 181                "                mkUart_bs(clocked_by sp_clock,\n" + \
 182                "                    reset_by sp_reset, sp_clock, sp_reset);"
 183
 184     def _mk_connection(self, name=None, count=0):
 185         return "uart{0}.slave_axi_uart"
 186
 187     def pinname_out(self, pname):
 188         return {'tx': 'coe_rs232.sout'}.get(pname, '')
 189
 190     def pinname_in(self, pname):
 191         return {'rx': 'coe_rs232.sin'}.get(pname, '')
 192
 193
 194 class twi(PBase):
 195
 196     def slowimport(self):
 197         return "        import I2C_top           :: *;"
 198
 199     def slowifdecl(self):
 200         return "            interface I2C_out twi{0}_out;\n" + \
 201                "            method Bit#(1) twi{0}_isint;"
 202
 203     def num_axi_regs32(self):
 204         return 8
 205
 206     def mkslow_peripheral(self, size=0):
 207         return "        I2C_IFC twi{0} <- mkI2CController();"
 208
 209     def _mk_connection(self, name=None, count=0):
 210         return "twi{0}.slave_i2c_axi"
 211
 212     def pinname_out(self, pname):
 213         return {'sda': 'out.sda_out',
 214                 'scl': 'out.scl_out'}.get(pname, '')
 215
 216     def pinname_in(self, pname):
 217         return {'sda': 'out.sda_in',
 218                 'scl': 'out.scl_in'}.get(pname, '')
 219
 220     def pinname_outen(self, pname):
 221         return {'sda': 'out.sda_out_en',
 222                 'scl': 'out.scl_out_en'}.get(pname, '')
 223
 224     def pinname_tweak(self, pname, typ, txt):
 225         if typ == 'outen':
 226             return "pack({0})".format(txt)
 227         return txt
 228
 229
 230 class qspi(PBase):
 231
 232     def slowimport(self):
 233         return "        import qspi              :: *;"
 234
 235     def slowifdecl(self):
 236         return "            interface QSPI_out qspi{0}_out;\n" + \
 237                "            method Bit#(1) qspi{0}_isint;"
 238
 239     def num_axi_regs32(self):
 240         return 13
 241
 242     def mkslow_peripheral(self, size=0):
 243         return "        Ifc_qspi qspi{0} <-  mkqspi();"
 244
 245     def _mk_connection(self, name=None, count=0):
 246         return "qspi{0}.slave"
 247
 248     def pinname_out(self, pname):
 249         return {'ck': 'out.clk_o',
 250                 'nss': 'out.ncs_o',
 251                 'io0': 'out.io_o[0]',
 252                 'io1': 'out.io_o[1]',
 253                 'io2': 'out.io_o[2]',
 254                 'io3': 'out.io_o[3]',
 255                 }.get(pname, '')
 256
 257     def pinname_outen(self, pname):
 258         return {'ck': 1,
 259                 'nss': 1,
 260                 'io0': 'out.io_enable[0]',
 261                 'io1': 'out.io_enable[1]',
 262                 'io2': 'out.io_enable[2]',
 263                 'io3': 'out.io_enable[3]',
 264                 }.get(pname, '')
 265
 266     def mk_pincon(self, name, count):
 267         ret = [PBase.mk_pincon(self, name, count)]
 268         # special-case for gpio in, store in a temporary vector
 269         plen = len(self.peripheral.pinspecs)
 270         ret.append("    // XXX NSS and CLK are hard-coded master")
 271         ret.append("    // TODO: must add qspi slave-mode")
 272         ret.append("    // all ins done in one rule from 4-bitfield")
 273         ret.append("    rule con_%s%d_io_in;" % (name, count))
 274         ret.append("       {0}{1}.out.io_i({{".format(name, count))
 275         for i, p in enumerate(self.peripheral.pinspecs):
 276             typ = p['type']
 277             pname = p['name']
 278             if not pname.startswith('io'):
 279                 continue
 280             idx = pname[1:]
 281             n = name
 282             sname = self.peripheral.pname(pname).format(count)
 283             ps = "pinmux.peripheral_side.%s_in" % sname
 284             comma = '' if i == 5 else ','
 285             ret.append("            {0}{1}".format(ps, comma))
 286         ret.append("        });")
 287         ret.append("    endrule")
 288         return '\n'.join(ret)
 289
 290
 291 class pwm(PBase):
 292
 293     def slowimport(self):
 294         return "        import pwm::*;"
 295
 296     def slowifdecl(self):
 297         return "        interface PWMIO pwm{0}_o;"
 298
 299     def num_axi_regs32(self):
 300         return 4
 301
 302     def mkslow_peripheral(self, size=0):
 303         return "        Ifc_PWM_bus pwm{0}_bus <- mkPWM_bus(sp_clock);"
 304
 305     def _mk_connection(self, name=None, count=0):
 306         return "pwm{0}_bus.axi4_slave"
 307
 308     def pinname_out(self, pname):
 309         return {'out': 'pwm_io.pwm_o'}.get(pname, '')
 310
 311
 312 class gpio(PBase):
 313
 314     def slowimport(self):
 315         return "     import pinmux::*;\n" + \
 316                "     import mux::*;\n" + \
 317                "     import gpio::*;\n"
 318
 319     def slowifdecl(self):
 320         return "        interface GPIO_config#({1}) pad_config{0};"
 321
 322     def num_axi_regs32(self):
 323         return 2
 324
 325     def axi_slave_idx(self, idx, name, ifacenum):
 326         """ generates AXI slave number definition, except
 327             GPIO also has a muxer per bank
 328         """
 329         name = name.upper()
 330         mname = 'mux' + name[4:]
 331         mname = mname.upper()
 332         print "AXIslavenum", name,  mname
 333         (ret, x) = PBase.axi_slave_idx(self, idx, name, ifacenum)
 334         (ret2, x) = PBase.axi_slave_idx(self, idx, mname, ifacenum)
 335         return ("%s\n%s" % (ret, ret2), 2)
 336
 337     def mkslow_peripheral(self, size=0):
 338         print "gpioslow", self.peripheral,  dir(self.peripheral)
 339         size = len(self.peripheral.pinspecs)
 340         return "        MUX#(%d) mux{0} <- mkmux();\n" % size + \
 341                "        GPIO#(%d) gpio{0} <- mkgpio();" % size
 342
 343     def mk_connection(self, count):
 344         print "GPIO mk_conn", self.name, count
 345         res = []
 346         dname = self.mksuffix(self.name, count)
 347         for i, n in enumerate(['gpio' + dname, 'mux' + dname]):
 348             res.append(PBase.mk_connection(self, count, n))
 349         return '\n'.join(res)
 350
 351     def _mk_connection(self, name=None, count=0):
 352         n = self.mksuffix(name, count)
 353         if name.startswith('gpio'):
 354             return "gpio{0}.axi_slave".format(n)
 355         if name.startswith('mux'):
 356             return "mux{0}.axi_slave".format(n)
 357
 358     def mksuffix(self, name, i):
 359         if name.startswith('mux'):
 360             return name[3:]
 361         return name[4:]
 362
 363     def mk_cellconn(self, cellnum, name, count):
 364         ret = []
 365         bank = self.mksuffix(name, count)
 366         txt = "       pinmux.mux_lines.cell{0}_mux(mux{1}.mux_config.mux[{2}]);"
 367         for p in self.peripheral.pinspecs:
 368             ret.append(txt.format(cellnum, bank, p['name'][1:]))
 369             cellnum += 1
 370         return ("\n".join(ret), cellnum)
 371
 372     def pinname_out(self, pname):
 373         return "func.gpio_out[{0}]".format(pname[1:])
 374
 375     def pinname_outen(self, pname):
 376         return {'sda': 'out.sda_outen',
 377                 'scl': 'out.scl_outen'}.get(pname, '')
 378
 379     def mk_pincon(self, name, count):
 380         ret = [PBase.mk_pincon(self, name, count)]
 381         # special-case for gpio in, store in a temporary vector
 382         plen = len(self.peripheral.pinspecs)
 383         ret.append("    rule con_%s%d_in;" % (name, count))
 384         ret.append("       Vector#({0},Bit#(1)) temp;".format(plen))
 385         for p in self.peripheral.pinspecs:
 386             typ = p['type']
 387             pname = p['name']
 388             idx = pname[1:]
 389             n = name
 390             sname = self.peripheral.pname(pname).format(count)
 391             ps = "pinmux.peripheral_side.%s_in" % sname
 392             ret.append("        temp[{0}]={1};".format(idx, ps))
 393         ret.append("        {0}.func.gpio_in(temp);".format(name))
 394         ret.append("    endrule")
 395         return '\n'.join(ret)
 396
 397
 398 axi_slave_declarations = """\
 399 typedef  0  SlowMaster;
 400 {0}
 401 typedef  TAdd#(LastGen_slave_num,`ifdef CLINT       1 `else 0 `endif )
 402               CLINT_slave_num;
 403 typedef  TAdd#(CLINT_slave_num  ,`ifdef PLIC        1 `else 0 `endif )
 404               Plic_slave_num;
 405 typedef  TAdd#(Plic_slave_num   ,`ifdef AXIEXP      1 `else 0 `endif )
 406               AxiExp1_slave_num;
 407 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
 408 """
 409
 410 pinmux_cellrule = """\
 411     rule connect_select_lines_pinmux;
 412 {0}
 413     endrule
 414 """
 415
 416
 417 class CallFn(object):
 418     def __init__(self, peripheral, name):
 419         self.peripheral = peripheral
 420         self.name = name
 421
 422     def __call__(self, *args):
 423         #print "__call__", self.name, self.peripheral.slow, args
 424         if not self.peripheral.slow:
 425             return ''
 426         return getattr(self.peripheral.slow, self.name)(*args[1:])
 427
 428
 429 class PeripheralIface(object):
 430     def __init__(self, ifacename):
 431         self.slow = None
 432         slow = slowfactory.getcls(ifacename)
 433         print "Iface", ifacename, slow
 434         if slow:
 435             self.slow = slow(ifacename)
 436             self.slow.peripheral = self
 437         for fname in ['slowimport', 'slowifdecl', 'mkslow_peripheral',
 438                       'mk_connection', 'mk_cellconn', 'mk_pincon']:
 439             fn = CallFn(self, fname)
 440             setattr(self, fname, types.MethodType(fn, self))
 441
 442         #print "PeripheralIface"
 443         #print dir(self)
 444
 445     def mksuffix(self, name, i):
 446         if self.slow is None:
 447             return i
 448         return self.slow.mksuffix(name, i)
 449
 450     def axi_reg_def(self, start, count):
 451         if not self.slow:
 452             return ('', 0)
 453         return self.slow.axi_reg_def(start, self.ifacename, count)
 454
 455     def axi_slave_idx(self, start, count):
 456         if not self.slow:
 457             return ('', 0)
 458         return self.slow.axi_slave_idx(start, self.ifacename, count)
 459
 460     def axi_addr_map(self, count):
 461         if not self.slow:
 462             return ''
 463         return self.slow.axi_addr_map(self.ifacename, count)
 464
 465
 466 class PeripheralInterfaces(object):
 467     def __init__(self):
 468         pass
 469
 470     def slowimport(self, *args):
 471         ret = []
 472         for (name, count) in self.ifacecount:
 473             #print "slowimport", name, self.data[name].slowimport
 474             ret.append(self.data[name].slowimport())
 475         return '\n'.join(list(filter(None, ret)))
 476
 477     def slowifdecl(self, *args):
 478         ret = []
 479         for (name, count) in self.ifacecount:
 480             for i in range(count):
 481                 ret.append(self.data[name].slowifdecl().format(i, name))
 482         return '\n'.join(list(filter(None, ret)))
 483
 484     def axi_reg_def(self, *args):
 485         ret = []
 486         start = 0x00011100  # start of AXI peripherals address
 487         for (name, count) in self.ifacecount:
 488             for i in range(count):
 489                 x = self.data[name].axi_reg_def(start, i)
 490                 #print ("ifc", name, x)
 491                 (rdef, offs) = x
 492                 ret.append(rdef)
 493                 start += offs
 494         return '\n'.join(list(filter(None, ret)))
 495
 496     def axi_slave_idx(self, *args):
 497         ret = []
 498         start = 0
 499         for (name, count) in self.ifacecount:
 500             for i in range(count):
 501                 (rdef, offs) = self.data[name].axi_slave_idx(start, i)
 502                 #print ("ifc", name, rdef, offs)
 503                 ret.append(rdef)
 504                 start += offs
 505         ret.append("typedef %d LastGen_slave_num;" % (start - 1))
 506         decls = '\n'.join(list(filter(None, ret)))
 507         return axi_slave_declarations.format(decls)
 508
 509     def axi_addr_map(self, *args):
 510         ret = []
 511         for (name, count) in self.ifacecount:
 512             for i in range(count):
 513                 ret.append(self.data[name].axi_addr_map(i))
 514         return '\n'.join(list(filter(None, ret)))
 515
 516     def mkslow_peripheral(self, *args):
 517         ret = []
 518         for (name, count) in self.ifacecount:
 519             for i in range(count):
 520                 print "mkslow", name, count
 521                 x = self.data[name].mkslow_peripheral()
 522                 print name, count, x
 523                 suffix = self.data[name].mksuffix(name, i)
 524                 ret.append(x.format(suffix))
 525         return '\n'.join(list(filter(None, ret)))
 526
 527     def mk_connection(self, *args):
 528         ret = []
 529         for (name, count) in self.ifacecount:
 530             for i in range(count):
 531                 print "mk_conn", name, i
 532                 txt = self.data[name].mk_connection(i)
 533                 if name == 'gpioa':
 534                     print "txt", txt
 535                     print self.data[name].mk_connection
 536                 ret.append(txt)
 537         return '\n'.join(list(filter(None, ret)))
 538
 539     def mk_cellconn(self):
 540         ret = []
 541         cellcount = 0
 542         for (name, count) in self.ifacecount:
 543             for i in range(count):
 544                 res = self.data[name].mk_cellconn(cellcount, name, i)
 545                 if not res:
 546                     continue
 547                 (txt, cellcount) = res
 548                 ret.append(txt)
 549         ret = '\n'.join(list(filter(None, ret)))
 550         return pinmux_cellrule.format(ret)
 551
 552     def mk_pincon(self):
 553         ret = []
 554         for (name, count) in self.ifacecount:
 555             for i in range(count):
 556                 txt = self.data[name].mk_pincon(name, i)
 557                 ret.append(txt)
 558         return '\n'.join(list(filter(None, ret)))
 559
 560
 561 class PFactory(object):
 562     def getcls(self, name):
 563         for k, v in {'uart': uart,
 564                      'rs232': rs232,
 565                      'twi': twi,
 566                      'qspi': qspi,
 567                      'pwm': pwm,
 568                      'gpio': gpio
 569                      }.items():
 570             if name.startswith(k):
 571                 return v
 572         return None
 573
 574
 575 slowfactory = PFactory()
 576
 577 if __name__ == '__main__':
 578     p = uart('uart')
 579     print p.slowimport()
 580     print p.slowifdecl()
 581     i = PeripheralIface('uart')
 582     print i, i.slow
 583     i = PeripheralIface('gpioa')
 584     print i, i.slow