2 from copy
import deepcopy
6 def __init__(self
, name
):
9 def axibase(self
, name
, ifacenum
):
11 return "%(name)s%(ifacenum)dBase" % locals()
13 def axiend(self
, name
, ifacenum
):
15 return "%(name)s%(ifacenum)dEnd" % locals()
17 def axi_reg_def(self
, start
, name
, ifacenum
):
19 offs
= self
.num_axi_regs32() * 4 * 16
20 end
= start
+ offs
- 1
21 bname
= self
.axibase(name
, ifacenum
)
22 bend
= self
.axiend(name
, ifacenum
)
23 comment
= "%d 32-bit regs" % self
.num_axi_regs32()
24 return (" `define %(bname)s 'h%(start)08X\n"
25 " `define %(bend)s 'h%(end)08X // %(comment)s" % locals(),
28 def axi_slave_name(self
, name
, ifacenum
):
30 return "{0}{1}_slave_num".format(name
, ifacenum
)
32 def axi_slave_idx(self
, idx
, name
, ifacenum
):
33 name
= self
.axi_slave_name(name
, ifacenum
)
34 return ("typedef {0} {1};".format(idx
, name
), 1)
36 def axi_addr_map(self
, name
, ifacenum
):
37 bname
= self
.axibase(name
, ifacenum
)
38 bend
= self
.axiend(name
, ifacenum
)
39 name
= self
.axi_slave_name(name
, ifacenum
)
41 if(addr>=`{0} && addr<=`{1})
42 return tuple2(True,fromInteger(valueOf({2})));
43 else""".format(bname
, bend
, name
)
45 def mk_pincon(self
, name
, count
):
46 # TODO: really should be using bsv.interface_decl.Interfaces
47 # pin-naming rules.... logic here is hard-coded to duplicate
48 # it (see Interface.__init__ outen)
50 for p
in self
.peripheral
.pinspecs
:
53 #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
54 n
= name
# "{0}{1}".format(self.name, self.mksuffix(name, count))
55 ret
.append(" //%s %s" % (n
, str(p
)))
56 sname
= self
.peripheral
.pname(pname
).format(count
)
57 ps
= "pinmux.peripheral_side.%s" % sname
58 if typ
== 'out' or typ
== 'inout':
59 ret
.append(" rule con_%s%d_%s_out;" % (name
, count
, pname
))
60 fname
= self
.pinname_out(pname
)
66 if not n
.startswith('gpio'): # XXX EURGH! horrible hack
67 n_
= "{0}{1}".format(n
, count
)
70 ret
.append(" {0}({1}.{2});".format(ps_
, n_
, fname
))
73 fname
= self
.pinname_outen(pname
)
75 if isinstance(fname
, str):
76 fname
= "{0}{1}.{2}".format(n
, count
, fname
)
77 fname
= self
.pinname_tweak(pname
, 'outen', fname
)
78 ret
.append(" {0}_outen({1});".format(ps
, fname
))
79 ret
.append(" endrule")
80 if typ
== 'in' or typ
== 'inout':
81 fname
= self
.pinname_in(pname
)
88 " rule con_%s%d_%s_in;" %
90 n_
= "{0}{1}".format(n
, count
)
91 ret
.append(" {1}.{2}({0});".format(ps_
, n_
, fname
))
92 ret
.append(" endrule")
95 def mk_cellconn(self
, *args
):
98 def mkslow_peripheral(self
, size
=0):
101 def mksuffix(self
, name
, i
):
104 def __mk_connection(self
, con
, aname
):
105 txt
= " mkConnection (slow_fabric.v_to_slaves\n" + \
106 " [fromInteger(valueOf({1}))],\n" + \
109 print "PBase __mk_connection", self
.name
, aname
112 return txt
.format(con
, aname
)
114 def mk_connection(self
, count
, name
=None):
117 print "PBase mk_conn", self
.name
, count
118 aname
= self
.axi_slave_name(name
, count
)
119 #dname = self.mksuffix(name, count)
120 #dname = "{0}{1}".format(name, dname)
121 con
= self
._mk
_connection
(name
, count
).format(count
, aname
)
122 return self
.__mk
_connection
(con
, aname
)
124 def _mk_connection(self
, name
=None, count
=0):
127 def pinname_out(self
, pname
):
130 def pinname_in(self
, pname
):
133 def pinname_outen(self
, pname
):
136 def pinname_tweak(self
, pname
, typ
, txt
):
142 def slowimport(self
):
143 return " import Uart16550 :: *;"
145 def slowifdecl(self
):
146 return " interface RS232_PHY_Ifc uart{0}_coe;\n" + \
147 " method Bit#(1) uart{0}_intr;"
149 def num_axi_regs32(self
):
152 def mkslow_peripheral(self
, size
=0):
153 return " Uart16550_AXI4_Lite_Ifc uart{0} <- \n" + \
154 " mkUart16550(clocked_by uart_clock,\n" + \
155 " reset_by uart_reset, sp_clock, sp_reset);"
157 def _mk_connection(self
, name
=None, count
=0):
158 return "uart{0}.slave_axi_uart"
160 def pinname_out(self
, pname
):
161 return {'tx': 'coe_rs232.sout'}.get(pname
, '')
163 def pinname_in(self
, pname
):
164 return {'rx': 'coe_rs232.sin'}.get(pname
, '')
169 def slowimport(self
):
170 return " import Uart_bs::*;\n" + \
171 " import RS232_modified::*;"
173 def slowifdecl(self
):
174 return " interface RS232 uart{0}_coe;"
176 def num_axi_regs32(self
):
179 def mkslow_peripheral(self
, size
=0):
180 return " //Ifc_Uart_bs uart{0} <-" + \
181 " // mkUart_bs(clocked_by uart_clock,\n" + \
182 " // reset_by uart_reset,sp_clock, sp_reset);" +\
183 " Ifc_Uart_bs uart{0} <-" + \
184 " mkUart_bs(clocked_by sp_clock,\n" + \
185 " reset_by sp_reset, sp_clock, sp_reset);"
187 def _mk_connection(self
, name
=None, count
=0):
188 return "uart{0}.slave_axi_uart"
190 def pinname_out(self
, pname
):
191 return {'tx': 'coe_rs232.sout'}.get(pname
, '')
193 def pinname_in(self
, pname
):
194 return {'rx': 'coe_rs232.sin'}.get(pname
, '')
199 def slowimport(self
):
200 return " import I2C_top :: *;"
202 def slowifdecl(self
):
203 return " interface I2C_out twi{0}_out;\n" + \
204 " method Bit#(1) twi{0}_isint;"
206 def num_axi_regs32(self
):
209 def mkslow_peripheral(self
, size
=0):
210 return " I2C_IFC twi{0} <- mkI2CController();"
212 def _mk_connection(self
, name
=None, count
=0):
213 return "twi{0}.slave_i2c_axi"
215 def pinname_out(self
, pname
):
216 return {'sda': 'out.sda_out',
217 'scl': 'out.scl_out'}.get(pname
, '')
219 def pinname_in(self
, pname
):
220 return {'sda': 'out.sda_in',
221 'scl': 'out.scl_in'}.get(pname
, '')
223 def pinname_outen(self
, pname
):
224 return {'sda': 'out.sda_out_en',
225 'scl': 'out.scl_out_en'}.get(pname
, '')
227 def pinname_tweak(self
, pname
, typ
, txt
):
229 return "pack({0})".format(txt
)
235 def slowimport(self
):
236 return " import qspi :: *;"
238 def slowifdecl(self
):
239 return " interface QSPI_out qspi{0}_out;\n" + \
240 " method Bit#(1) qspi{0}_isint;"
242 def num_axi_regs32(self
):
245 def mkslow_peripheral(self
, size
=0):
246 return " Ifc_qspi qspi{0} <- mkqspi();"
248 def _mk_connection(self
, name
=None, count
=0):
249 return "qspi{0}.slave"
251 def pinname_out(self
, pname
):
252 return {'ck': 'out.clk_o',
254 'io0': 'out.io_o[0]',
255 'io1': 'out.io_o[1]',
256 'io2': 'out.io_o[2]',
257 'io3': 'out.io_o[3]',
260 def pinname_outen(self
, pname
):
263 'io0': 'out.io_enable[0]',
264 'io1': 'out.io_enable[1]',
265 'io2': 'out.io_enable[2]',
266 'io3': 'out.io_enable[3]',
269 def mk_pincon(self
, name
, count
):
270 ret
= [PBase
.mk_pincon(self
, name
, count
)]
271 # special-case for gpio in, store in a temporary vector
272 plen
= len(self
.peripheral
.pinspecs
)
273 ret
.append(" // XXX NSS and CLK are hard-coded master")
274 ret
.append(" // TODO: must add qspi slave-mode")
275 ret
.append(" // all ins done in one rule from 4-bitfield")
276 ret
.append(" rule con_%s%d_io_in;" % (name
, count
))
277 ret
.append(" {0}{1}.out.io_i({{".format(name
, count
))
278 for i
, p
in enumerate(self
.peripheral
.pinspecs
):
281 if not pname
.startswith('io'):
285 sname
= self
.peripheral
.pname(pname
).format(count
)
286 ps
= "pinmux.peripheral_side.%s_in" % sname
287 comma
= '' if i
== 5 else ','
288 ret
.append(" {0}{1}".format(ps
, comma
))
290 ret
.append(" endrule")
291 return '\n'.join(ret
)
296 def slowimport(self
):
297 return " import pwm::*;"
299 def slowifdecl(self
):
300 return " interface PWMIO pwm{0};"
302 def num_axi_regs32(self
):
305 def mkslow_peripheral(self
, size
=0):
306 return " Ifc_PWM_bus pwm{0}_bus <- mkPWM_bus(sp_clock);"
308 def _mk_connection(self
, name
=None, count
=0):
309 return "pwm{0}_bus.axi4_slave"
311 def pinname_out(self
, pname
):
312 return {'out': 'pwm_io.pwm_o'}.get(pname
, '')
317 def slowimport(self
):
318 return " import pinmux::*;\n" + \
319 " import mux::*;\n" + \
322 def slowifdecl(self
):
323 return " interface GPIO_config#({1}) pad_config{0};"
325 def num_axi_regs32(self
):
328 def axi_slave_idx(self
, idx
, name
, ifacenum
):
329 """ generates AXI slave number definition, except
330 GPIO also has a muxer per bank
333 mname
= 'mux' + name
[4:]
334 mname
= mname
.upper()
335 print "AXIslavenum", name
, mname
336 (ret
, x
) = PBase
.axi_slave_idx(self
, idx
, name
, ifacenum
)
337 (ret2
, x
) = PBase
.axi_slave_idx(self
, idx
, mname
, ifacenum
)
338 return ("%s\n%s" % (ret
, ret2
), 2)
340 def mkslow_peripheral(self
, size
=0):
341 print "gpioslow", self
.peripheral
, dir(self
.peripheral
)
342 size
= len(self
.peripheral
.pinspecs
)
343 return " MUX#(%d) mux{0} <- mkmux();\n" % size
+ \
344 " GPIO#(%d) gpio{0} <- mkgpio();" % size
346 def mk_connection(self
, count
):
347 print "GPIO mk_conn", self
.name
, count
349 dname
= self
.mksuffix(self
.name
, count
)
350 for i
, n
in enumerate(['gpio' + dname
, 'mux' + dname
]):
351 res
.append(PBase
.mk_connection(self
, count
, n
))
352 return '\n'.join(res
)
354 def _mk_connection(self
, name
=None, count
=0):
355 n
= self
.mksuffix(name
, count
)
356 if name
.startswith('gpio'):
357 return "gpio{0}.axi_slave".format(n
)
358 if name
.startswith('mux'):
359 return "mux{0}.axi_slave".format(n
)
361 def mksuffix(self
, name
, i
):
362 if name
.startswith('mux'):
366 def mk_cellconn(self
, cellnum
, name
, count
):
368 bank
= self
.mksuffix(name
, count
)
369 txt
= " pinmux.mux_lines.cell{0}_mux(mux{1}.mux_config.mux[{2}]);"
370 for p
in self
.peripheral
.pinspecs
:
371 ret
.append(txt
.format(cellnum
, bank
, p
['name'][1:]))
373 return ("\n".join(ret
), cellnum
)
375 def pinname_out(self
, pname
):
376 return "func.gpio_out[{0}]".format(pname
[1:])
378 def pinname_outen(self
, pname
):
379 return {'sda': 'out.sda_outen',
380 'scl': 'out.scl_outen'}.get(pname
, '')
382 def mk_pincon(self
, name
, count
):
383 ret
= [PBase
.mk_pincon(self
, name
, count
)]
384 # special-case for gpio in, store in a temporary vector
385 plen
= len(self
.peripheral
.pinspecs
)
386 ret
.append(" rule con_%s%d_in;" % (name
, count
))
387 ret
.append(" Vector#({0},Bit#(1)) temp;".format(plen
))
388 for p
in self
.peripheral
.pinspecs
:
393 sname
= self
.peripheral
.pname(pname
).format(count
)
394 ps
= "pinmux.peripheral_side.%s_in" % sname
395 ret
.append(" temp[{0}]={1};".format(idx
, ps
))
396 ret
.append(" {0}.func.gpio_in(temp);".format(name
))
397 ret
.append(" endrule")
398 return '\n'.join(ret
)
401 axi_slave_declarations
= """\
402 typedef 0 SlowMaster;
404 typedef TAdd#(LastGen_slave_num,`ifdef CLINT 1 `else 0 `endif )
406 typedef TAdd#(CLINT_slave_num ,`ifdef PLIC 1 `else 0 `endif )
408 typedef TAdd#(Plic_slave_num ,`ifdef AXIEXP 1 `else 0 `endif )
410 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
413 pinmux_cellrule
= """\
414 rule connect_select_lines_pinmux;
420 class CallFn(object):
421 def __init__(self
, peripheral
, name
):
422 self
.peripheral
= peripheral
425 def __call__(self
, *args
):
426 #print "__call__", self.name, self.peripheral.slow, args
427 if not self
.peripheral
.slow
:
429 return getattr(self
.peripheral
.slow
, self
.name
)(*args
[1:])
432 class PeripheralIface(object):
433 def __init__(self
, ifacename
):
435 slow
= slowfactory
.getcls(ifacename
)
436 print "Iface", ifacename
, slow
438 self
.slow
= slow(ifacename
)
439 self
.slow
.peripheral
= self
440 for fname
in ['slowimport', 'slowifdecl', 'mkslow_peripheral',
441 'mk_connection', 'mk_cellconn', 'mk_pincon']:
442 fn
= CallFn(self
, fname
)
443 setattr(self
, fname
, types
.MethodType(fn
, self
))
445 #print "PeripheralIface"
448 def mksuffix(self
, name
, i
):
449 if self
.slow
is None:
451 return self
.slow
.mksuffix(name
, i
)
453 def axi_reg_def(self
, start
, count
):
456 return self
.slow
.axi_reg_def(start
, self
.ifacename
, count
)
458 def axi_slave_idx(self
, start
, count
):
461 return self
.slow
.axi_slave_idx(start
, self
.ifacename
, count
)
463 def axi_addr_map(self
, count
):
466 return self
.slow
.axi_addr_map(self
.ifacename
, count
)
469 class PeripheralInterfaces(object):
473 def slowimport(self
, *args
):
475 for (name
, count
) in self
.ifacecount
:
476 #print "slowimport", name, self.data[name].slowimport
477 ret
.append(self
.data
[name
].slowimport())
478 return '\n'.join(list(filter(None, ret
)))
480 def slowifdecl(self
, *args
):
482 for (name
, count
) in self
.ifacecount
:
483 for i
in range(count
):
484 ret
.append(self
.data
[name
].slowifdecl().format(i
, name
))
485 return '\n'.join(list(filter(None, ret
)))
487 def axi_reg_def(self
, *args
):
489 start
= 0x00011100 # start of AXI peripherals address
490 for (name
, count
) in self
.ifacecount
:
491 for i
in range(count
):
492 x
= self
.data
[name
].axi_reg_def(start
, i
)
493 #print ("ifc", name, x)
497 return '\n'.join(list(filter(None, ret
)))
499 def axi_slave_idx(self
, *args
):
502 for (name
, count
) in self
.ifacecount
:
503 for i
in range(count
):
504 (rdef
, offs
) = self
.data
[name
].axi_slave_idx(start
, i
)
505 #print ("ifc", name, rdef, offs)
508 ret
.append("typedef %d LastGen_slave_num;" % (start
- 1))
509 decls
= '\n'.join(list(filter(None, ret
)))
510 return axi_slave_declarations
.format(decls
)
512 def axi_addr_map(self
, *args
):
514 for (name
, count
) in self
.ifacecount
:
515 for i
in range(count
):
516 ret
.append(self
.data
[name
].axi_addr_map(i
))
517 return '\n'.join(list(filter(None, ret
)))
519 def mkslow_peripheral(self
, *args
):
521 for (name
, count
) in self
.ifacecount
:
522 for i
in range(count
):
523 print "mkslow", name
, count
524 x
= self
.data
[name
].mkslow_peripheral()
526 suffix
= self
.data
[name
].mksuffix(name
, i
)
527 ret
.append(x
.format(suffix
))
528 return '\n'.join(list(filter(None, ret
)))
530 def mk_connection(self
, *args
):
532 for (name
, count
) in self
.ifacecount
:
533 for i
in range(count
):
534 print "mk_conn", name
, i
535 txt
= self
.data
[name
].mk_connection(i
)
538 print self
.data
[name
].mk_connection
540 return '\n'.join(list(filter(None, ret
)))
542 def mk_cellconn(self
):
545 for (name
, count
) in self
.ifacecount
:
546 for i
in range(count
):
547 res
= self
.data
[name
].mk_cellconn(cellcount
, name
, i
)
550 (txt
, cellcount
) = res
552 ret
= '\n'.join(list(filter(None, ret
)))
553 return pinmux_cellrule
.format(ret
)
557 for (name
, count
) in self
.ifacecount
:
558 for i
in range(count
):
559 txt
= self
.data
[name
].mk_pincon(name
, i
)
561 return '\n'.join(list(filter(None, ret
)))
564 class PFactory(object):
565 def getcls(self
, name
):
566 for k
, v
in {'uart': uart
,
573 if name
.startswith(k
):
578 slowfactory
= PFactory()
580 if __name__
== '__main__':
584 i
= PeripheralIface('uart')
586 i
= PeripheralIface('gpioa')