src/bsv/peripheral_gen.py

   1 import types
   2 from copy import deepcopy
   3
   4
   5 class PBase(object):
   6     def __init__(self, name):
   7         self.name = name
   8
   9     def slowifdeclmux(self):
  10         return ''
  11
  12     def slowifdecl(self):
  13         return ''
  14
  15     def axibase(self, name, ifacenum):
  16         name = name.upper()
  17         return "%(name)s%(ifacenum)dBase" % locals()
  18
  19     def axiend(self, name, ifacenum):
  20         name = name.upper()
  21         return "%(name)s%(ifacenum)dEnd" % locals()
  22
  23     def axi_reg_def(self, start, name, ifacenum):
  24         name = name.upper()
  25         offs = self.num_axi_regs32() * 4 * 16
  26         end = start + offs - 1
  27         bname = self.axibase(name, ifacenum)
  28         bend = self.axiend(name, ifacenum)
  29         comment = "%d 32-bit regs" % self.num_axi_regs32()
  30         return ("    `define %(bname)s 'h%(start)08X\n"
  31                 "    `define %(bend)s  'h%(end)08X // %(comment)s" % locals(),
  32                 offs)
  33
  34     def axi_slave_name(self, name, ifacenum):
  35         name = name.upper()
  36         return "{0}{1}_slave_num".format(name, ifacenum)
  37
  38     def axi_slave_idx(self, idx, name, ifacenum):
  39         name = self.axi_slave_name(name, ifacenum)
  40         return ("typedef {0} {1};".format(idx, name), 1)
  41
  42     def axi_addr_map(self, name, ifacenum):
  43         bname = self.axibase(name, ifacenum)
  44         bend = self.axiend(name, ifacenum)
  45         name = self.axi_slave_name(name, ifacenum)
  46         return """\
  47         if(addr>=`{0} && addr<=`{1})
  48             return tuple2(True,fromInteger(valueOf({2})));
  49         else""".format(bname, bend, name)
  50
  51     def mk_pincon(self, name, count):
  52         # TODO: really should be using bsv.interface_decl.Interfaces
  53         # pin-naming rules.... logic here is hard-coded to duplicate
  54         # it (see Interface.__init__ outen)
  55         ret = []
  56         for p in self.peripheral.pinspecs:
  57             typ = p['type']
  58             pname = p['name']
  59             #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
  60             n = name  # "{0}{1}".format(self.name, self.mksuffix(name, count))
  61             ret.append("    //%s %s" % (n, str(p)))
  62             sname = self.peripheral.pname(pname).format(count)
  63             ps = "pinmux.peripheral_side.%s" % sname
  64             if typ == 'out' or typ == 'inout':
  65                 ret.append("    rule con_%s%d_%s_out;" % (name, count, pname))
  66                 fname = self.pinname_out(pname)
  67                 if not n.startswith('gpio'): # XXX EURGH! horrible hack
  68                   n_ = "{0}{1}".format(n, count)
  69                 else:
  70                   n_ = n
  71                 if fname:
  72                     if p.get('outen'):
  73                         ps_ = ps + '_out'
  74                     else:
  75                         ps_ = ps
  76                     ret.append("      {0}({1}.{2});".format(ps_, n_, fname))
  77                 fname = None
  78                 if p.get('outen'):
  79                     fname = self.pinname_outen(pname)
  80                 if fname:
  81                     if isinstance(fname, str):
  82                         fname = "{0}.{1}".format(n_, fname)
  83                     fname = self.pinname_tweak(pname, 'outen', fname)
  84                     ret.append("      {0}_outen({1});".format(ps, fname))
  85                 ret.append("    endrule")
  86             if typ == 'in' or typ == 'inout':
  87                 fname = self.pinname_in(pname)
  88                 if fname:
  89                     if p.get('outen'):
  90                         ps_ = ps + '_in'
  91                     else:
  92                         ps_ = ps
  93                     ret.append(
  94                         "    rule con_%s%d_%s_in;" %
  95                         (name, count, pname))
  96                     n_ = "{0}{1}".format(n, count)
  97                     ret.append("      {1}.{2}({0});".format(ps_, n_, fname))
  98                     ret.append("    endrule")
  99         return '\n'.join(ret)
 100
 101     def mk_cellconn(self, *args):
 102         return ''
 103
 104     def mkslow_peripheral(self, size=0):
 105         return ''
 106
 107     def mksuffix(self, name, i):
 108         return i
 109
 110     def __mk_connection(self, con, aname):
 111         txt = "        mkConnection (slow_fabric.v_to_slaves\n" + \
 112             "                    [fromInteger(valueOf({1}))],\n" + \
 113             "                    {0});"
 114
 115         print "PBase __mk_connection", self.name, aname
 116         if not con:
 117             return ''
 118         return txt.format(con, aname)
 119
 120     def mk_connection(self, count, name=None):
 121         if name is None:
 122             name = self.name
 123         print "PBase mk_conn", self.name, count
 124         aname = self.axi_slave_name(name, count)
 125         #dname = self.mksuffix(name, count)
 126         #dname = "{0}{1}".format(name, dname)
 127         con = self._mk_connection(name, count).format(count, aname)
 128         return self.__mk_connection(con, aname)
 129
 130     def _mk_connection(self, name=None, count=0):
 131         return ''
 132
 133     def pinname_out(self, pname):
 134         return ''
 135
 136     def pinname_in(self, pname):
 137         return ''
 138
 139     def pinname_outen(self, pname):
 140         return ''
 141
 142     def pinname_tweak(self, pname, typ, txt):
 143         return txt
 144
 145
 146 class uart(PBase):
 147
 148     def slowimport(self):
 149         return "          import Uart_bs         :: *;\n" + \
 150                "          import RS232_modified::*;"
 151
 152     def slowifdecl(self):
 153         return "            interface RS232 uart{0}_coe;\n" + \
 154                "            method Bit#(1) uart{0}_intr;"
 155
 156     def num_axi_regs32(self):
 157         return 8
 158
 159     def mkslow_peripheral(self, size=0):
 160         return "        Ifc_Uart_bs uart{0} <- \n" + \
 161                "                mkUart_bs(clocked_by sp_clock,\n" + \
 162                "                    reset_by uart_reset, sp_clock, sp_reset);"
 163
 164     def _mk_connection(self, name=None, count=0):
 165         return "uart{0}.slave_axi_uart"
 166
 167     def pinname_out(self, pname):
 168         return {'tx': 'coe_rs232.sout'}.get(pname, '')
 169
 170     def pinname_in(self, pname):
 171         return {'rx': 'coe_rs232.sin'}.get(pname, '')
 172
 173
 174 class qquart(PBase):
 175
 176     def slowimport(self):
 177         return "          import Uart16550         :: *;"
 178
 179     def slowifdecl(self):
 180         return "            interface RS232_PHY_Ifc uart{0}_coe;\n" + \
 181                "            method Bit#(1) uart{0}_intr;"
 182
 183     def num_axi_regs32(self):
 184         return 8
 185
 186     def mkslow_peripheral(self, size=0):
 187         return "        Uart16550_AXI4_Lite_Ifc uart{0} <- \n" + \
 188                "                mkUart16550(clocked_by sp_clock,\n" + \
 189                "                    reset_by uart_reset, sp_clock, sp_reset);"
 190
 191     def _mk_connection(self, name=None, count=0):
 192         return "uart{0}.slave_axi_uart"
 193
 194     def pinname_out(self, pname):
 195         return {'tx': 'coe_rs232.sout'}.get(pname, '')
 196
 197     def pinname_in(self, pname):
 198         return {'rx': 'coe_rs232.sin'}.get(pname, '')
 199
 200
 201 class rs232(PBase):
 202
 203     def slowimport(self):
 204         return "        import Uart_bs::*;\n" + \
 205                "        import RS232_modified::*;"
 206
 207     def slowifdecl(self):
 208         return "            interface RS232 uart{0}_coe;"
 209
 210     def num_axi_regs32(self):
 211         return 2
 212
 213     def mkslow_peripheral(self, size=0):
 214         return "        //Ifc_Uart_bs uart{0} <-" + \
 215                "        //       mkUart_bs(clocked_by uart_clock,\n" + \
 216                "        //          reset_by uart_reset,sp_clock, sp_reset);" +\
 217                "        Ifc_Uart_bs uart{0} <-" + \
 218                "                mkUart_bs(clocked_by sp_clock,\n" + \
 219                "                    reset_by sp_reset, sp_clock, sp_reset);"
 220
 221     def _mk_connection(self, name=None, count=0):
 222         return "uart{0}.slave_axi_uart"
 223
 224     def pinname_out(self, pname):
 225         return {'tx': 'coe_rs232.sout'}.get(pname, '')
 226
 227     def pinname_in(self, pname):
 228         return {'rx': 'coe_rs232.sin'}.get(pname, '')
 229
 230
 231 class twi(PBase):
 232
 233     def slowimport(self):
 234         return "        import I2C_top           :: *;"
 235
 236     def slowifdecl(self):
 237         return "            interface I2C_out twi{0}_out;\n" + \
 238                "            method Bit#(1) twi{0}_isint;"
 239
 240     def num_axi_regs32(self):
 241         return 8
 242
 243     def mkslow_peripheral(self, size=0):
 244         return "        I2C_IFC twi{0} <- mkI2CController();"
 245
 246     def _mk_connection(self, name=None, count=0):
 247         return "twi{0}.slave_i2c_axi"
 248
 249     def pinname_out(self, pname):
 250         return {'sda': 'out.sda_out',
 251                 'scl': 'out.scl_out'}.get(pname, '')
 252
 253     def pinname_in(self, pname):
 254         return {'sda': 'out.sda_in',
 255                 'scl': 'out.scl_in'}.get(pname, '')
 256
 257     def pinname_outen(self, pname):
 258         return {'sda': 'out.sda_out_en',
 259                 'scl': 'out.scl_out_en'}.get(pname, '')
 260
 261     def pinname_tweak(self, pname, typ, txt):
 262         if typ == 'outen':
 263             return "pack({0})".format(txt)
 264         return txt
 265
 266
 267 class spi(PBase):
 268
 269     def slowimport(self):
 270         return "        import qspi              :: *;"
 271
 272     def slowifdecl(self):
 273         return "            interface QSPI_out spi{0}_out;\n" + \
 274                "            method Bit#(1) spi{0}_isint;"
 275
 276     def num_axi_regs32(self):
 277         return 13
 278
 279     def mkslow_peripheral(self):
 280         return "        Ifc_qspi spi{0} <-  mkqspi();"
 281
 282     def _mk_connection(self, name=None, count=0):
 283         return "qspi{0}.slave"
 284
 285     def pinname_out(self, pname):
 286         return {'clk': 'out.clk_o',
 287                 'nss': 'out.ncs_o',
 288                 'mosi': 'out.io_o[0]',
 289                 'miso': 'out.io_o[1]',
 290                 }.get(pname, '')
 291
 292     def pinname_outen(self, pname):
 293         return {'ck': 1,
 294                 'nss': 1,
 295                 'mosi': 'out.io_enable[0]',
 296                 'miso': 'out.io_enable[1]',
 297                 }.get(pname, '')
 298
 299     def mk_pincon(self, name, count):
 300         ret = [PBase.mk_pincon(self, name, count)]
 301         # special-case for gpio in, store in a temporary vector
 302         plen = len(self.peripheral.pinspecs)
 303         ret.append("    // XXX NSS and CLK are hard-coded master")
 304         ret.append("    // TODO: must add qspi slave-mode")
 305         ret.append("    // all ins done in one rule from 4-bitfield")
 306         ret.append("    rule con_%s%d_io_in;" % (name, count))
 307         ret.append("       {0}{1}.out.io_i({{".format(name, count))
 308         for idx, pname in enumerate(['mosi', 'miso']):
 309             sname = self.peripheral.pname(pname).format(count)
 310             ps = "pinmux.peripheral_side.%s_in" % sname
 311             ret.append("            {0},".format(ps))
 312         ret.append("            0,0")
 313         ret.append("        });")
 314         ret.append("    endrule")
 315         return '\n'.join(ret)
 316
 317
 318 class qspi(PBase):
 319
 320     def slowimport(self):
 321         return "        import qspi              :: *;"
 322
 323     def slowifdecl(self):
 324         return "            interface QSPI_out qspi{0}_out;\n" + \
 325                "            method Bit#(1) qspi{0}_isint;"
 326
 327     def num_axi_regs32(self):
 328         return 13
 329
 330     def mkslow_peripheral(self, size=0):
 331         return "        Ifc_qspi qspi{0} <-  mkqspi();"
 332
 333     def _mk_connection(self, name=None, count=0):
 334         return "qspi{0}.slave"
 335
 336     def pinname_out(self, pname):
 337         return {'ck': 'out.clk_o',
 338                 'nss': 'out.ncs_o',
 339                 'io0': 'out.io_o[0]',
 340                 'io1': 'out.io_o[1]',
 341                 'io2': 'out.io_o[2]',
 342                 'io3': 'out.io_o[3]',
 343                 }.get(pname, '')
 344
 345     def pinname_outen(self, pname):
 346         return {'ck': 1,
 347                 'nss': 1,
 348                 'io0': 'out.io_enable[0]',
 349                 'io1': 'out.io_enable[1]',
 350                 'io2': 'out.io_enable[2]',
 351                 'io3': 'out.io_enable[3]',
 352                 }.get(pname, '')
 353
 354     def mk_pincon(self, name, count):
 355         ret = [PBase.mk_pincon(self, name, count)]
 356         # special-case for gpio in, store in a temporary vector
 357         plen = len(self.peripheral.pinspecs)
 358         ret.append("    // XXX NSS and CLK are hard-coded master")
 359         ret.append("    // TODO: must add qspi slave-mode")
 360         ret.append("    // all ins done in one rule from 4-bitfield")
 361         ret.append("    rule con_%s%d_io_in;" % (name, count))
 362         ret.append("       {0}{1}.out.io_i({{".format(name, count))
 363         for i, p in enumerate(self.peripheral.pinspecs):
 364             typ = p['type']
 365             pname = p['name']
 366             if not pname.startswith('io'):
 367                 continue
 368             idx = pname[1:]
 369             n = name
 370             sname = self.peripheral.pname(pname).format(count)
 371             ps = "pinmux.peripheral_side.%s_in" % sname
 372             comma = '' if i == 5 else ','
 373             ret.append("            {0}{1}".format(ps, comma))
 374         ret.append("        });")
 375         ret.append("    endrule")
 376         return '\n'.join(ret)
 377
 378
 379 class pwm(PBase):
 380
 381     def slowimport(self):
 382         return "        import pwm::*;"
 383
 384     def slowifdecl(self):
 385         return "        interface PWMIO pwm{0}_io;"
 386
 387     def num_axi_regs32(self):
 388         return 4
 389
 390     def mkslow_peripheral(self, size=0):
 391         return "        Ifc_PWM_bus pwm{0} <- mkPWM_bus(sp_clock);"
 392
 393     def _mk_connection(self, name=None, count=0):
 394         return "pwm{0}.axi4_slave"
 395
 396     def pinname_out(self, pname):
 397         return {'out': 'pwm_io.pwm_o'}.get(pname, '')
 398
 399
 400 class gpio(PBase):
 401
 402     def slowimport(self):
 403         return "     import pinmux::*;\n" + \
 404                "     import mux::*;\n" + \
 405                "     import gpio::*;\n"
 406
 407     def slowifdeclmux(self):
 408         size = len(self.peripheral.pinspecs)
 409         return "    interface GPIO_config#(%d) pad_config{0};" % size
 410
 411     def num_axi_regs32(self):
 412         return 2
 413
 414     def axi_slave_idx(self, idx, name, ifacenum):
 415         """ generates AXI slave number definition, except
 416             GPIO also has a muxer per bank
 417         """
 418         name = name.upper()
 419         mname = 'mux' + name[4:]
 420         mname = mname.upper()
 421         print "AXIslavenum", name,  mname
 422         (ret, x) = PBase.axi_slave_idx(self, idx, name, ifacenum)
 423         (ret2, x) = PBase.axi_slave_idx(self, idx+1, mname, ifacenum)
 424         return ("%s\n%s" % (ret, ret2), 2)
 425
 426     def mkslow_peripheral(self, size=0):
 427         print "gpioslow", self.peripheral,  dir(self.peripheral)
 428         size = len(self.peripheral.pinspecs)
 429         return "        MUX#(%d) mux{0} <- mkmux();\n" % size + \
 430                "        GPIO#(%d) gpio{0} <- mkgpio();" % size
 431
 432     def mk_connection(self, count):
 433         print "GPIO mk_conn", self.name, count
 434         res = []
 435         dname = self.mksuffix(self.name, count)
 436         for i, n in enumerate(['gpio' + dname, 'mux' + dname]):
 437             res.append(PBase.mk_connection(self, count, n))
 438         return '\n'.join(res)
 439
 440     def _mk_connection(self, name=None, count=0):
 441         n = self.mksuffix(name, count)
 442         if name.startswith('gpio'):
 443             return "gpio{0}.axi_slave".format(n)
 444         if name.startswith('mux'):
 445             return "mux{0}.axi_slave".format(n)
 446
 447     def mksuffix(self, name, i):
 448         if name.startswith('mux'):
 449             return name[3:]
 450         return name[4:]
 451
 452     def mk_cellconn(self, cellnum, name, count):
 453         ret = []
 454         bank = self.mksuffix(name, count)
 455         txt = "       pinmux.mux_lines.cell{0}_mux(mux{1}.mux_config.mux[{2}]);"
 456         for p in self.peripheral.pinspecs:
 457             ret.append(txt.format(cellnum, bank, p['name'][1:]))
 458             cellnum += 1
 459         return ("\n".join(ret), cellnum)
 460
 461     def pinname_out(self, pname):
 462         return "func.gpio_out[{0}]".format(pname[1:])
 463
 464     def pinname_outen(self, pname):
 465         return "func.gpio_out_en[{0}]".format(pname[1:])
 466
 467     def mk_pincon(self, name, count):
 468         ret = [PBase.mk_pincon(self, name, count)]
 469         # special-case for gpio in, store in a temporary vector
 470         plen = len(self.peripheral.pinspecs)
 471         ret.append("    rule con_%s%d_in;" % (name, count))
 472         ret.append("       Vector#({0},Bit#(1)) temp;".format(plen))
 473         for p in self.peripheral.pinspecs:
 474             typ = p['type']
 475             pname = p['name']
 476             idx = pname[1:]
 477             n = name
 478             sname = self.peripheral.pname(pname).format(count)
 479             ps = "pinmux.peripheral_side.%s_in" % sname
 480             ret.append("        temp[{0}]={1};".format(idx, ps))
 481         ret.append("        {0}.func.gpio_in(temp);".format(name))
 482         ret.append("    endrule")
 483         return '\n'.join(ret)
 484
 485
 486 axi_slave_declarations = """\
 487 typedef  0  SlowMaster;
 488 {0}
 489 typedef  TAdd#(LastGen_slave_num,`ifdef CLINT       1 `else 0 `endif )
 490               CLINT_slave_num;
 491 typedef  TAdd#(CLINT_slave_num  ,`ifdef PLIC        1 `else 0 `endif )
 492               Plic_slave_num;
 493 typedef  TAdd#(Plic_slave_num   ,`ifdef AXIEXP      1 `else 0 `endif )
 494               AxiExp1_slave_num;
 495 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
 496 """
 497
 498 pinmux_cellrule = """\
 499     rule connect_select_lines_pinmux;
 500 {0}
 501     endrule
 502 """
 503
 504
 505 class CallFn(object):
 506     def __init__(self, peripheral, name):
 507         self.peripheral = peripheral
 508         self.name = name
 509
 510     def __call__(self, *args):
 511         #print "__call__", self.name, self.peripheral.slow, args
 512         if not self.peripheral.slow:
 513             return ''
 514         return getattr(self.peripheral.slow, self.name)(*args[1:])
 515
 516
 517 class PeripheralIface(object):
 518     def __init__(self, ifacename):
 519         self.slow = None
 520         slow = slowfactory.getcls(ifacename)
 521         print "Iface", ifacename, slow
 522         if slow:
 523             self.slow = slow(ifacename)
 524             self.slow.peripheral = self
 525         for fname in ['slowimport', 'slowifdecl', 'slowifdeclmux',
 526                       'mkslow_peripheral',
 527                       'mk_connection', 'mk_cellconn', 'mk_pincon']:
 528             fn = CallFn(self, fname)
 529             setattr(self, fname, types.MethodType(fn, self))
 530
 531         #print "PeripheralIface"
 532         #print dir(self)
 533
 534     def mksuffix(self, name, i):
 535         if self.slow is None:
 536             return i
 537         return self.slow.mksuffix(name, i)
 538
 539     def axi_reg_def(self, start, count):
 540         if not self.slow:
 541             return ('', 0)
 542         return self.slow.axi_reg_def(start, self.ifacename, count)
 543
 544     def axi_slave_idx(self, start, count):
 545         if not self.slow:
 546             return ('', 0)
 547         return self.slow.axi_slave_idx(start, self.ifacename, count)
 548
 549     def axi_addr_map(self, count):
 550         if not self.slow:
 551             return ''
 552         return self.slow.axi_addr_map(self.ifacename, count)
 553
 554
 555 class PeripheralInterfaces(object):
 556     def __init__(self):
 557         pass
 558
 559     def slowimport(self, *args):
 560         ret = []
 561         for (name, count) in self.ifacecount:
 562             #print "slowimport", name, self.data[name].slowimport
 563             ret.append(self.data[name].slowimport())
 564         return '\n'.join(list(filter(None, ret)))
 565
 566     def slowifdeclmux(self, *args):
 567         ret = []
 568         for (name, count) in self.ifacecount:
 569             for i in range(count):
 570                 ret.append(self.data[name].slowifdeclmux().format(i, name))
 571         return '\n'.join(list(filter(None, ret)))
 572
 573     def slowifdecl(self, *args):
 574         ret = []
 575         for (name, count) in self.ifacecount:
 576             for i in range(count):
 577                 ret.append(self.data[name].slowifdecl().format(i, name))
 578         return '\n'.join(list(filter(None, ret)))
 579
 580     def axi_reg_def(self, *args):
 581         ret = []
 582         start = 0x00011100  # start of AXI peripherals address
 583         for (name, count) in self.ifacecount:
 584             for i in range(count):
 585                 x = self.data[name].axi_reg_def(start, i)
 586                 #print ("ifc", name, x)
 587                 (rdef, offs) = x
 588                 ret.append(rdef)
 589                 start += offs
 590         return '\n'.join(list(filter(None, ret)))
 591
 592     def axi_slave_idx(self, *args):
 593         ret = []
 594         start = 0
 595         for (name, count) in self.ifacecount:
 596             for i in range(count):
 597                 (rdef, offs) = self.data[name].axi_slave_idx(start, i)
 598                 #print ("ifc", name, rdef, offs)
 599                 ret.append(rdef)
 600                 start += offs
 601         ret.append("typedef %d LastGen_slave_num;" % (start - 1))
 602         decls = '\n'.join(list(filter(None, ret)))
 603         return axi_slave_declarations.format(decls)
 604
 605     def axi_addr_map(self, *args):
 606         ret = []
 607         for (name, count) in self.ifacecount:
 608             for i in range(count):
 609                 ret.append(self.data[name].axi_addr_map(i))
 610         return '\n'.join(list(filter(None, ret)))
 611
 612     def mkslow_peripheral(self, *args):
 613         ret = []
 614         for (name, count) in self.ifacecount:
 615             for i in range(count):
 616                 print "mkslow", name, count
 617                 x = self.data[name].mkslow_peripheral()
 618                 print name, count, x
 619                 suffix = self.data[name].mksuffix(name, i)
 620                 ret.append(x.format(suffix))
 621         return '\n'.join(list(filter(None, ret)))
 622
 623     def mk_connection(self, *args):
 624         ret = []
 625         for (name, count) in self.ifacecount:
 626             for i in range(count):
 627                 print "mk_conn", name, i
 628                 txt = self.data[name].mk_connection(i)
 629                 if name == 'gpioa':
 630                     print "txt", txt
 631                     print self.data[name].mk_connection
 632                 ret.append(txt)
 633         return '\n'.join(list(filter(None, ret)))
 634
 635     def mk_cellconn(self):
 636         ret = []
 637         cellcount = 0
 638         for (name, count) in self.ifacecount:
 639             for i in range(count):
 640                 res = self.data[name].mk_cellconn(cellcount, name, i)
 641                 if not res:
 642                     continue
 643                 (txt, cellcount) = res
 644                 ret.append(txt)
 645         ret = '\n'.join(list(filter(None, ret)))
 646         return pinmux_cellrule.format(ret)
 647
 648     def mk_pincon(self):
 649         ret = []
 650         for (name, count) in self.ifacecount:
 651             for i in range(count):
 652                 txt = self.data[name].mk_pincon(name, i)
 653                 ret.append(txt)
 654         return '\n'.join(list(filter(None, ret)))
 655
 656
 657 class PFactory(object):
 658     def getcls(self, name):
 659         for k, v in {'uart': uart,
 660                      'rs232': rs232,
 661                      'twi': twi,
 662                      'qspi': qspi,
 663                      'spi': spi,
 664                      'pwm': pwm,
 665                      'gpio': gpio
 666                      }.items():
 667             if name.startswith(k):
 668                 return v
 669         return None
 670
 671
 672 slowfactory = PFactory()
 673
 674 if __name__ == '__main__':
 675     p = uart('uart')
 676     print p.slowimport()
 677     print p.slowifdecl()
 678     i = PeripheralIface('uart')
 679     print i, i.slow
 680     i = PeripheralIface('gpioa')
 681     print i, i.slow