src/bsv/peripheral_gen.py

   1 import types
   2 from copy import deepcopy
   3
   4
   5 class PBase(object):
   6     def __init__(self, name):
   7         self.name = name
   8
   9     def slowifdeclmux(self):
  10         return ''
  11
  12     def slowimport(self):
  13         return ''
  14
  15     def num_axi_regs32(self):
  16         return 0
  17
  18     def slowifdecl(self):
  19         return ''
  20
  21     def axibase(self, name, ifacenum):
  22         name = name.upper()
  23         return "%(name)s%(ifacenum)dBase" % locals()
  24
  25     def axiend(self, name, ifacenum):
  26         name = name.upper()
  27         return "%(name)s%(ifacenum)dEnd" % locals()
  28
  29     def axi_reg_def(self, start, name, ifacenum):
  30         name = name.upper()
  31         offs = self.num_axi_regs32() * 4 * 16
  32         if offs == 0:
  33             return ('', 0)
  34         end = start + offs - 1
  35         bname = self.axibase(name, ifacenum)
  36         bend = self.axiend(name, ifacenum)
  37         comment = "%d 32-bit regs" % self.num_axi_regs32()
  38         return ("    `define %(bname)s 'h%(start)08X\n"
  39                 "    `define %(bend)s  'h%(end)08X // %(comment)s" % locals(),
  40                 offs)
  41
  42     def axi_slave_name(self, name, ifacenum):
  43         name = name.upper()
  44         return "{0}{1}_slave_num".format(name, ifacenum)
  45
  46     def axi_slave_idx(self, idx, name, ifacenum):
  47         name = self.axi_slave_name(name, ifacenum)
  48         return ("typedef {0} {1};".format(idx, name), 1)
  49
  50     def axi_addr_map(self, name, ifacenum):
  51         bname = self.axibase(name, ifacenum)
  52         bend = self.axiend(name, ifacenum)
  53         name = self.axi_slave_name(name, ifacenum)
  54         return """\
  55         if(addr>=`{0} && addr<=`{1})
  56             return tuple2(True,fromInteger(valueOf({2})));
  57         else""".format(bname, bend, name)
  58
  59     def mk_pincon(self, name, count):
  60         # TODO: really should be using bsv.interface_decl.Interfaces
  61         # pin-naming rules.... logic here is hard-coded to duplicate
  62         # it (see Interface.__init__ outen)
  63         ret = []
  64         for p in self.peripheral.pinspecs:
  65             typ = p['type']
  66             pname = p['name']
  67             #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
  68             n = name  # "{0}{1}".format(self.name, self.mksuffix(name, count))
  69             ret.append("    //%s %s" % (n, str(p)))
  70             sname = self.peripheral.pname(pname).format(count)
  71             ps = "pinmux.peripheral_side.%s" % sname
  72             if typ == 'out' or typ == 'inout':
  73                 ret.append("    rule con_%s%d_%s_out;" % (name, count, pname))
  74                 fname = self.pinname_out(pname)
  75                 if not n.startswith('gpio'): # XXX EURGH! horrible hack
  76                   n_ = "{0}{1}".format(n, count)
  77                 else:
  78                   n_ = n
  79                 if fname:
  80                     if p.get('outen'):
  81                         ps_ = ps + '_out'
  82                     else:
  83                         ps_ = ps
  84                     ret.append("      {0}({1}.{2});".format(ps_, n_, fname))
  85                 fname = None
  86                 if p.get('outen'):
  87                     fname = self.pinname_outen(pname)
  88                 if fname:
  89                     if isinstance(fname, str):
  90                         fname = "{0}.{1}".format(n_, fname)
  91                     fname = self.pinname_tweak(pname, 'outen', fname)
  92                     ret.append("      {0}_outen({1});".format(ps, fname))
  93                 ret.append("    endrule")
  94             if typ == 'in' or typ == 'inout':
  95                 fname = self.pinname_in(pname)
  96                 if fname:
  97                     if p.get('outen'):
  98                         ps_ = ps + '_in'
  99                     else:
 100                         ps_ = ps
 101                     ret.append(
 102                         "    rule con_%s%d_%s_in;" %
 103                         (name, count, pname))
 104                     n_ = "{0}{1}".format(n, count)
 105                     ret.append("      {1}.{2}({0});".format(ps_, n_, fname))
 106                     ret.append("    endrule")
 107         return '\n'.join(ret)
 108
 109     def mk_cellconn(self, *args):
 110         return ''
 111
 112     def mkslow_peripheral(self, size=0):
 113         return ''
 114
 115     def mksuffix(self, name, i):
 116         return i
 117
 118     def __mk_connection(self, con, aname):
 119         txt = "        mkConnection (slow_fabric.v_to_slaves\n" + \
 120             "                    [fromInteger(valueOf({1}))],\n" + \
 121             "                    {0});"
 122
 123         print "PBase __mk_connection", self.name, aname
 124         if not con:
 125             return ''
 126         return txt.format(con, aname)
 127
 128     def mk_connection(self, count, name=None):
 129         if name is None:
 130             name = self.name
 131         print "PBase mk_conn", self.name, count
 132         aname = self.axi_slave_name(name, count)
 133         #dname = self.mksuffix(name, count)
 134         #dname = "{0}{1}".format(name, dname)
 135         con = self._mk_connection(name, count).format(count, aname)
 136         return self.__mk_connection(con, aname)
 137
 138     def _mk_connection(self, name=None, count=0):
 139         return ''
 140
 141     def pinname_out(self, pname):
 142         return ''
 143
 144     def pinname_in(self, pname):
 145         return ''
 146
 147     def pinname_outen(self, pname):
 148         return ''
 149
 150     def pinname_tweak(self, pname, typ, txt):
 151         return txt
 152
 153
 154 class uart(PBase):
 155
 156     def slowimport(self):
 157         return "          import Uart_bs         :: *;\n" + \
 158                "          import RS232_modified::*;"
 159
 160     def slowifdecl(self):
 161         return "            interface RS232 uart{0}_coe;\n" + \
 162                "            method Bit#(1) uart{0}_intr;"
 163
 164     def num_axi_regs32(self):
 165         return 8
 166
 167     def mkslow_peripheral(self, size=0):
 168         return "        Ifc_Uart_bs uart{0} <- \n" + \
 169                "                mkUart_bs(clocked_by sp_clock,\n" + \
 170                "                    reset_by uart_reset, sp_clock, sp_reset);"
 171
 172     def _mk_connection(self, name=None, count=0):
 173         return "uart{0}.slave_axi_uart"
 174
 175     def pinname_out(self, pname):
 176         return {'tx': 'coe_rs232.sout'}.get(pname, '')
 177
 178     def pinname_in(self, pname):
 179         return {'rx': 'coe_rs232.sin'}.get(pname, '')
 180
 181
 182 class qquart(PBase):
 183
 184     def slowimport(self):
 185         return "          import Uart16550         :: *;"
 186
 187     def slowifdecl(self):
 188         return "            interface RS232_PHY_Ifc uart{0}_coe;\n" + \
 189                "            method Bit#(1) uart{0}_intr;"
 190
 191     def num_axi_regs32(self):
 192         return 8
 193
 194     def mkslow_peripheral(self, size=0):
 195         return "        Uart16550_AXI4_Lite_Ifc uart{0} <- \n" + \
 196                "                mkUart16550(clocked_by sp_clock,\n" + \
 197                "                    reset_by uart_reset, sp_clock, sp_reset);"
 198
 199     def _mk_connection(self, name=None, count=0):
 200         return "uart{0}.slave_axi_uart"
 201
 202     def pinname_out(self, pname):
 203         return {'tx': 'coe_rs232.sout'}.get(pname, '')
 204
 205     def pinname_in(self, pname):
 206         return {'rx': 'coe_rs232.sin'}.get(pname, '')
 207
 208
 209 class rs232(PBase):
 210
 211     def slowimport(self):
 212         return "        import Uart_bs::*;\n" + \
 213                "        import RS232_modified::*;"
 214
 215     def slowifdecl(self):
 216         return "            interface RS232 uart{0}_coe;"
 217
 218     def num_axi_regs32(self):
 219         return 2
 220
 221     def mkslow_peripheral(self, size=0):
 222         return "        //Ifc_Uart_bs uart{0} <-" + \
 223                "        //       mkUart_bs(clocked_by uart_clock,\n" + \
 224                "        //          reset_by uart_reset,sp_clock, sp_reset);" +\
 225                "        Ifc_Uart_bs uart{0} <-" + \
 226                "                mkUart_bs(clocked_by sp_clock,\n" + \
 227                "                    reset_by sp_reset, sp_clock, sp_reset);"
 228
 229     def _mk_connection(self, name=None, count=0):
 230         return "uart{0}.slave_axi_uart"
 231
 232     def pinname_out(self, pname):
 233         return {'tx': 'coe_rs232.sout'}.get(pname, '')
 234
 235     def pinname_in(self, pname):
 236         return {'rx': 'coe_rs232.sin'}.get(pname, '')
 237
 238
 239 class twi(PBase):
 240
 241     def slowimport(self):
 242         return "        import I2C_top           :: *;"
 243
 244     def slowifdecl(self):
 245         return "            interface I2C_out twi{0}_out;\n" + \
 246                "            method Bit#(1) twi{0}_isint;"
 247
 248     def num_axi_regs32(self):
 249         return 8
 250
 251     def mkslow_peripheral(self, size=0):
 252         return "        I2C_IFC twi{0} <- mkI2CController();"
 253
 254     def _mk_connection(self, name=None, count=0):
 255         return "twi{0}.slave_i2c_axi"
 256
 257     def pinname_out(self, pname):
 258         return {'sda': 'out.sda_out',
 259                 'scl': 'out.scl_out'}.get(pname, '')
 260
 261     def pinname_in(self, pname):
 262         return {'sda': 'out.sda_in',
 263                 'scl': 'out.scl_in'}.get(pname, '')
 264
 265     def pinname_outen(self, pname):
 266         return {'sda': 'out.sda_out_en',
 267                 'scl': 'out.scl_out_en'}.get(pname, '')
 268
 269     def pinname_tweak(self, pname, typ, txt):
 270         if typ == 'outen':
 271             return "pack({0})".format(txt)
 272         return txt
 273
 274
 275 class eint(PBase):
 276
 277     def mkslow_peripheral(self, size=0):
 278         size = len(self.peripheral.pinspecs)
 279         return "        Wire#(Bit#(%d)) wr_interrupt <- mkWire();" % size
 280
 281
 282     def _pinname_out(self, pname):
 283         return {'sda': 'out.sda_out',
 284                 'scl': 'out.scl_out'}.get(pname, '')
 285
 286     def _pinname_in(self, pname):
 287         return {'sda': 'out.sda_in',
 288                 'scl': 'out.scl_in'}.get(pname, '')
 289
 290     def _pinname_outen(self, pname):
 291         return {'sda': 'out.sda_out_en',
 292                 'scl': 'out.scl_out_en'}.get(pname, '')
 293
 294     def mk_pincon(self, name, count):
 295         size = len(self.peripheral.pinspecs)
 296         ret = []
 297         ret.append(eint_pincon_template.format(size))
 298         return '\n'.join(ret)
 299
 300
 301 eint_pincon_template = '''\
 302     // TODO: offset i by the number of eints already used
 303     for(Integer i=0;i<{0};i=i+ 1)begin
 304       rule connect_int_to_plic(wr_interrupt[i]==1);
 305                 ff_gateway_queue[i].enq(1);
 306                 plic.ifc_external_irq[i].irq_frm_gateway(True);
 307       endrule
 308     end
 309 '''
 310
 311
 312 class spi(PBase):
 313
 314     def slowimport(self):
 315         return "        import qspi              :: *;"
 316
 317     def slowifdecl(self):
 318         return "            interface QSPI_out spi{0}_out;\n" + \
 319                "            method Bit#(1) spi{0}_isint;"
 320
 321     def num_axi_regs32(self):
 322         return 13
 323
 324     def mkslow_peripheral(self):
 325         return "        Ifc_qspi spi{0} <-  mkqspi();"
 326
 327     def _mk_connection(self, name=None, count=0):
 328         return "spi{0}.slave"
 329
 330     def pinname_out(self, pname):
 331         return {'clk': 'out.clk_o',
 332                 'nss': 'out.ncs_o',
 333                 'mosi': 'out.io_o[0]',
 334                 'miso': 'out.io_o[1]',
 335                 }.get(pname, '')
 336
 337     def pinname_outen(self, pname):
 338         return {'clk': 1,
 339                 'nss': 1,
 340                 'mosi': 'out.io_enable[0]',
 341                 'miso': 'out.io_enable[1]',
 342                 }.get(pname, '')
 343
 344     def mk_pincon(self, name, count):
 345         ret = [PBase.mk_pincon(self, name, count)]
 346         # special-case for gpio in, store in a temporary vector
 347         plen = len(self.peripheral.pinspecs)
 348         ret.append("    // XXX NSS and CLK are hard-coded master")
 349         ret.append("    // TODO: must add spi slave-mode")
 350         ret.append("    // all ins done in one rule from 4-bitfield")
 351         ret.append("    rule con_%s%d_io_in;" % (name, count))
 352         ret.append("       {0}{1}.out.io_i({{".format(name, count))
 353         for idx, pname in enumerate(['mosi', 'miso']):
 354             sname = self.peripheral.pname(pname).format(count)
 355             ps = "pinmux.peripheral_side.%s_in" % sname
 356             ret.append("            {0},".format(ps))
 357         ret.append("            1'b0,1'b0")
 358         ret.append("        });")
 359         ret.append("    endrule")
 360         return '\n'.join(ret)
 361
 362
 363 class qspi(PBase):
 364
 365     def slowimport(self):
 366         return "        import qspi              :: *;"
 367
 368     def slowifdecl(self):
 369         return "            interface QSPI_out qspi{0}_out;\n" + \
 370                "            method Bit#(1) qspi{0}_isint;"
 371
 372     def num_axi_regs32(self):
 373         return 13
 374
 375     def mkslow_peripheral(self, size=0):
 376         return "        Ifc_qspi qspi{0} <-  mkqspi();"
 377
 378     def _mk_connection(self, name=None, count=0):
 379         return "qspi{0}.slave"
 380
 381     def pinname_out(self, pname):
 382         return {'ck': 'out.clk_o',
 383                 'nss': 'out.ncs_o',
 384                 'io0': 'out.io_o[0]',
 385                 'io1': 'out.io_o[1]',
 386                 'io2': 'out.io_o[2]',
 387                 'io3': 'out.io_o[3]',
 388                 }.get(pname, '')
 389
 390     def pinname_outen(self, pname):
 391         return {'ck': 1,
 392                 'nss': 1,
 393                 'io0': 'out.io_enable[0]',
 394                 'io1': 'out.io_enable[1]',
 395                 'io2': 'out.io_enable[2]',
 396                 'io3': 'out.io_enable[3]',
 397                 }.get(pname, '')
 398
 399     def mk_pincon(self, name, count):
 400         ret = [PBase.mk_pincon(self, name, count)]
 401         # special-case for gpio in, store in a temporary vector
 402         plen = len(self.peripheral.pinspecs)
 403         ret.append("    // XXX NSS and CLK are hard-coded master")
 404         ret.append("    // TODO: must add qspi slave-mode")
 405         ret.append("    // all ins done in one rule from 4-bitfield")
 406         ret.append("    rule con_%s%d_io_in;" % (name, count))
 407         ret.append("       {0}{1}.out.io_i({{".format(name, count))
 408         for i, p in enumerate(self.peripheral.pinspecs):
 409             typ = p['type']
 410             pname = p['name']
 411             if not pname.startswith('io'):
 412                 continue
 413             idx = pname[1:]
 414             n = name
 415             sname = self.peripheral.pname(pname).format(count)
 416             ps = "pinmux.peripheral_side.%s_in" % sname
 417             comma = '' if i == 5 else ','
 418             ret.append("            {0}{1}".format(ps, comma))
 419         ret.append("        });")
 420         ret.append("    endrule")
 421         return '\n'.join(ret)
 422
 423
 424 class pwm(PBase):
 425
 426     def slowimport(self):
 427         return "        import pwm::*;"
 428
 429     def slowifdecl(self):
 430         return "        interface PWMIO pwm{0}_io;"
 431
 432     def num_axi_regs32(self):
 433         return 4
 434
 435     def mkslow_peripheral(self, size=0):
 436         return "        Ifc_PWM_bus pwm{0} <- mkPWM_bus(sp_clock);"
 437
 438     def _mk_connection(self, name=None, count=0):
 439         return "pwm{0}.axi4_slave"
 440
 441     def pinname_out(self, pname):
 442         return {'out': 'pwm_io.pwm_o'}.get(pname, '')
 443
 444
 445 class gpio(PBase):
 446
 447     def slowimport(self):
 448         return "     import pinmux::*;\n" + \
 449                "     import mux::*;\n" + \
 450                "     import gpio::*;\n"
 451
 452     def slowifdeclmux(self):
 453         size = len(self.peripheral.pinspecs)
 454         return "    interface GPIO_config#(%d) pad_config{0};" % size
 455
 456     def num_axi_regs32(self):
 457         return 2
 458
 459     def axi_slave_idx(self, idx, name, ifacenum):
 460         """ generates AXI slave number definition, except
 461             GPIO also has a muxer per bank
 462         """
 463         name = name.upper()
 464         mname = 'mux' + name[4:]
 465         mname = mname.upper()
 466         print "AXIslavenum", name,  mname
 467         (ret, x) = PBase.axi_slave_idx(self, idx, name, ifacenum)
 468         (ret2, x) = PBase.axi_slave_idx(self, idx+1, mname, ifacenum)
 469         return ("%s\n%s" % (ret, ret2), 2)
 470
 471     def mkslow_peripheral(self, size=0):
 472         print "gpioslow", self.peripheral,  dir(self.peripheral)
 473         size = len(self.peripheral.pinspecs)
 474         return "        MUX#(%d) mux{0} <- mkmux();\n" % size + \
 475                "        GPIO#(%d) gpio{0} <- mkgpio();" % size
 476
 477     def mk_connection(self, count):
 478         print "GPIO mk_conn", self.name, count
 479         res = []
 480         dname = self.mksuffix(self.name, count)
 481         for i, n in enumerate(['gpio' + dname, 'mux' + dname]):
 482             res.append(PBase.mk_connection(self, count, n))
 483         return '\n'.join(res)
 484
 485     def _mk_connection(self, name=None, count=0):
 486         n = self.mksuffix(name, count)
 487         if name.startswith('gpio'):
 488             return "gpio{0}.axi_slave".format(n)
 489         if name.startswith('mux'):
 490             return "mux{0}.axi_slave".format(n)
 491
 492     def mksuffix(self, name, i):
 493         if name.startswith('mux'):
 494             return name[3:]
 495         return name[4:]
 496
 497     def mk_cellconn(self, cellnum, name, count):
 498         ret = []
 499         bank = self.mksuffix(name, count)
 500         txt = "       pinmux.mux_lines.cell{0}_mux(mux{1}.mux_config.mux[{2}]);"
 501         for p in self.peripheral.pinspecs:
 502             ret.append(txt.format(cellnum, bank, p['name'][1:]))
 503             cellnum += 1
 504         return ("\n".join(ret), cellnum)
 505
 506     def pinname_out(self, pname):
 507         return "func.gpio_out[{0}]".format(pname[1:])
 508
 509     def pinname_outen(self, pname):
 510         return "func.gpio_out_en[{0}]".format(pname[1:])
 511
 512     def mk_pincon(self, name, count):
 513         ret = [PBase.mk_pincon(self, name, count)]
 514         # special-case for gpio in, store in a temporary vector
 515         plen = len(self.peripheral.pinspecs)
 516         ret.append("    rule con_%s%d_in;" % (name, count))
 517         ret.append("       Vector#({0},Bit#(1)) temp;".format(plen))
 518         for p in self.peripheral.pinspecs:
 519             typ = p['type']
 520             pname = p['name']
 521             idx = pname[1:]
 522             n = name
 523             sname = self.peripheral.pname(pname).format(count)
 524             ps = "pinmux.peripheral_side.%s_in" % sname
 525             ret.append("        temp[{0}]={1};".format(idx, ps))
 526         ret.append("        {0}.func.gpio_in(temp);".format(name))
 527         ret.append("    endrule")
 528         return '\n'.join(ret)
 529
 530
 531 axi_slave_declarations = """\
 532 typedef  0  SlowMaster;
 533 {0}
 534 typedef  TAdd#(LastGen_slave_num,`ifdef CLINT       1 `else 0 `endif )
 535               CLINT_slave_num;
 536 typedef  TAdd#(CLINT_slave_num  ,`ifdef PLIC        1 `else 0 `endif )
 537               Plic_slave_num;
 538 typedef  TAdd#(Plic_slave_num   ,`ifdef AXIEXP      1 `else 0 `endif )
 539               AxiExp1_slave_num;
 540 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
 541 """
 542
 543 pinmux_cellrule = """\
 544     rule connect_select_lines_pinmux;
 545 {0}
 546     endrule
 547 """
 548
 549
 550 class CallFn(object):
 551     def __init__(self, peripheral, name):
 552         self.peripheral = peripheral
 553         self.name = name
 554
 555     def __call__(self, *args):
 556         #print "__call__", self.name, self.peripheral.slow, args
 557         if not self.peripheral.slow:
 558             return ''
 559         return getattr(self.peripheral.slow, self.name)(*args[1:])
 560
 561
 562 class PeripheralIface(object):
 563     def __init__(self, ifacename):
 564         self.slow = None
 565         slow = slowfactory.getcls(ifacename)
 566         print "Iface", ifacename, slow
 567         if slow:
 568             self.slow = slow(ifacename)
 569             self.slow.peripheral = self
 570         for fname in ['slowimport', 'slowifdecl', 'slowifdeclmux',
 571                       'mkslow_peripheral',
 572                       'mk_connection', 'mk_cellconn', 'mk_pincon']:
 573             fn = CallFn(self, fname)
 574             setattr(self, fname, types.MethodType(fn, self))
 575
 576         #print "PeripheralIface"
 577         #print dir(self)
 578
 579     def mksuffix(self, name, i):
 580         if self.slow is None:
 581             return i
 582         return self.slow.mksuffix(name, i)
 583
 584     def axi_reg_def(self, start, count):
 585         if not self.slow:
 586             return ('', 0)
 587         return self.slow.axi_reg_def(start, self.ifacename, count)
 588
 589     def axi_slave_idx(self, start, count):
 590         if not self.slow:
 591             return ('', 0)
 592         return self.slow.axi_slave_idx(start, self.ifacename, count)
 593
 594     def axi_addr_map(self, count):
 595         if not self.slow:
 596             return ''
 597         return self.slow.axi_addr_map(self.ifacename, count)
 598
 599
 600 class PeripheralInterfaces(object):
 601     def __init__(self):
 602         pass
 603
 604     def slowimport(self, *args):
 605         ret = []
 606         for (name, count) in self.ifacecount:
 607             #print "slowimport", name, self.data[name].slowimport
 608             ret.append(self.data[name].slowimport())
 609         return '\n'.join(list(filter(None, ret)))
 610
 611     def slowifdeclmux(self, *args):
 612         ret = []
 613         for (name, count) in self.ifacecount:
 614             for i in range(count):
 615                 ret.append(self.data[name].slowifdeclmux().format(i, name))
 616         return '\n'.join(list(filter(None, ret)))
 617
 618     def slowifdecl(self, *args):
 619         ret = []
 620         for (name, count) in self.ifacecount:
 621             for i in range(count):
 622                 ret.append(self.data[name].slowifdecl().format(i, name))
 623         return '\n'.join(list(filter(None, ret)))
 624
 625     def axi_reg_def(self, *args):
 626         ret = []
 627         start = 0x00011100  # start of AXI peripherals address
 628         for (name, count) in self.ifacecount:
 629             for i in range(count):
 630                 x = self.data[name].axi_reg_def(start, i)
 631                 #print ("ifc", name, x)
 632                 (rdef, offs) = x
 633                 ret.append(rdef)
 634                 start += offs
 635         return '\n'.join(list(filter(None, ret)))
 636
 637     def axi_slave_idx(self, *args):
 638         ret = []
 639         start = 0
 640         for (name, count) in self.ifacecount:
 641             for i in range(count):
 642                 (rdef, offs) = self.data[name].axi_slave_idx(start, i)
 643                 #print ("ifc", name, rdef, offs)
 644                 ret.append(rdef)
 645                 start += offs
 646         ret.append("typedef %d LastGen_slave_num;" % (start - 1))
 647         decls = '\n'.join(list(filter(None, ret)))
 648         return axi_slave_declarations.format(decls)
 649
 650     def axi_addr_map(self, *args):
 651         ret = []
 652         for (name, count) in self.ifacecount:
 653             for i in range(count):
 654                 ret.append(self.data[name].axi_addr_map(i))
 655         return '\n'.join(list(filter(None, ret)))
 656
 657     def mkslow_peripheral(self, *args):
 658         ret = []
 659         for (name, count) in self.ifacecount:
 660             for i in range(count):
 661                 print "mkslow", name, count
 662                 x = self.data[name].mkslow_peripheral()
 663                 print name, count, x
 664                 suffix = self.data[name].mksuffix(name, i)
 665                 ret.append(x.format(suffix))
 666         return '\n'.join(list(filter(None, ret)))
 667
 668     def mk_connection(self, *args):
 669         ret = []
 670         for (name, count) in self.ifacecount:
 671             for i in range(count):
 672                 print "mk_conn", name, i
 673                 txt = self.data[name].mk_connection(i)
 674                 if name == 'gpioa':
 675                     print "txt", txt
 676                     print self.data[name].mk_connection
 677                 ret.append(txt)
 678         return '\n'.join(list(filter(None, ret)))
 679
 680     def mk_cellconn(self):
 681         ret = []
 682         cellcount = 0
 683         for (name, count) in self.ifacecount:
 684             for i in range(count):
 685                 res = self.data[name].mk_cellconn(cellcount, name, i)
 686                 if not res:
 687                     continue
 688                 (txt, cellcount) = res
 689                 ret.append(txt)
 690         ret = '\n'.join(list(filter(None, ret)))
 691         return pinmux_cellrule.format(ret)
 692
 693     def mk_pincon(self):
 694         ret = []
 695         for (name, count) in self.ifacecount:
 696             for i in range(count):
 697                 txt = self.data[name].mk_pincon(name, i)
 698                 ret.append(txt)
 699         return '\n'.join(list(filter(None, ret)))
 700
 701
 702 class PFactory(object):
 703     def getcls(self, name):
 704         for k, v in {'uart': uart,
 705                      'rs232': rs232,
 706                      'twi': twi,
 707                      'qspi': qspi,
 708                      'spi': spi,
 709                      'pwm': pwm,
 710                      'eint': eint,
 711                      'gpio': gpio
 712                      }.items():
 713             if name.startswith(k):
 714                 return v
 715         return None
 716
 717
 718 slowfactory = PFactory()
 719
 720 if __name__ == '__main__':
 721     p = uart('uart')
 722     print p.slowimport()
 723     print p.slowifdecl()
 724     i = PeripheralIface('uart')
 725     print i, i.slow
 726     i = PeripheralIface('gpioa')
 727     print i, i.slow