src/bsv/peripheral_gen.py

   1 import types
   2 from copy import deepcopy
   3
   4
   5 class PBase(object):
   6     def __init__(self, name):
   7         self.name = name
   8
   9     def axibase(self, name, ifacenum):
  10         name = name.upper()
  11         return "%(name)s%(ifacenum)dBase" % locals()
  12
  13     def axiend(self, name, ifacenum):
  14         name = name.upper()
  15         return "%(name)s%(ifacenum)dEnd" % locals()
  16
  17     def axi_reg_def(self, start, name, ifacenum):
  18         name = name.upper()
  19         offs = self.num_axi_regs32() * 4 * 16
  20         end = start + offs - 1
  21         bname = self.axibase(name, ifacenum)
  22         bend = self.axiend(name, ifacenum)
  23         comment = "%d 32-bit regs" % self.num_axi_regs32()
  24         return ("    `define%(bname)s 'h%(start)08X\n"
  25                 "    `define%(bend)s  'h%(end)08X // %(comment)s" % locals(),
  26                 offs)
  27
  28     def axi_slave_name(self, name, ifacenum):
  29         name = name.upper()
  30         return "{0}{1}_slave_num".format(name, ifacenum)
  31
  32     def axi_slave_idx(self, idx, name, ifacenum):
  33         name = self.axi_slave_name(name, ifacenum)
  34         return ("typedef {0} {1};".format(idx, name), 1)
  35
  36     def axi_addr_map(self, name, ifacenum):
  37         bname = self.axibase(name, ifacenum)
  38         bend = self.axiend(name, ifacenum)
  39         name = self.axi_slave_name(name, ifacenum)
  40         return """\
  41         if(addr>=`{0} && addr<=`{1})
  42             return tuple2(True,fromInteger(valueOf({2})));
  43         else""".format(bname, bend, name)
  44
  45     def mk_pincon(self, name, count):
  46         # TODO: really should be using bsv.interface_decl.Interfaces
  47         # pin-naming rules.... logic here is hard-coded to duplicate
  48         # it (see Interface.__init__ outen)
  49         ret = []
  50         for p in self.peripheral.pinspecs:
  51             typ = p['type']
  52             pname = p['name']
  53             #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
  54             n = name  # "{0}{1}".format(self.name, self.mksuffix(name, count))
  55             ret.append("    //%s %s" % (n, str(p)))
  56             sname = self.peripheral.pname(pname).format(count)
  57             ps = "pinmux.peripheral_side.%s" % sname
  58             if typ == 'out' or typ == 'inout':
  59                 ret.append("    rule con_%s%d_%s_out" % (name, count, pname))
  60                 fname = self.pinname_out(pname)
  61                 if fname:
  62                     if p.get('outen'):
  63                         ps_ = ps + '_out'
  64                     else:
  65                         ps_ = ps
  66                     n_ = "{0}{1}".format(n, count)
  67                     ret.append("      {0}({1}.{2});".format(ps_, n_, fname))
  68                 fname = None
  69                 if p.get('outen'):
  70                     fname = self.pinname_outen(pname)
  71                 if fname:
  72                     fname = "{0}{1}.{2}".format(n, count, fname)
  73                     fname = self.pinname_tweak(pname, 'outen', fname)
  74                     ret.append("      {0}_outen({1});".format(ps, fname))
  75                 ret.append("    endrule")
  76             if typ == 'in' or typ == 'inout':
  77                 fname = self.pinname_in(pname)
  78                 if fname:
  79                     if p.get('outen'):
  80                         ps_ = ps + '_in'
  81                     else:
  82                         ps_ = ps
  83                     ret.append(
  84                         "    rule con_%s%d_%s_in" %
  85                         (name, count, pname))
  86                     ret.append("      {1}.{2}({0});".format(ps_, n, fname))
  87                     ret.append("    endrule")
  88         return '\n'.join(ret)
  89
  90     def mk_cellconn(self, *args):
  91         return ''
  92
  93     def mkslow_peripheral(self):
  94         return ''
  95
  96     def mksuffix(self, name, i):
  97         return i
  98
  99     def __mk_connection(self, con, aname):
 100         txt = "        mkConnection (slow_fabric.v_to_slaves\n" + \
 101             "                    [fromInteger(valueOf({1}))],\n" + \
 102             "                    {0});"
 103
 104         print "PBase __mk_connection", self.name, aname
 105         if not con:
 106             return ''
 107         return txt.format(con, aname)
 108
 109     def mk_connection(self, count, name=None):
 110         if name is None:
 111             name = self.name
 112         print "PBase mk_conn", self.name, count
 113         aname = self.axi_slave_name(name, count)
 114         #dname = self.mksuffix(name, count)
 115         #dname = "{0}{1}".format(name, dname)
 116         con = self._mk_connection(name, count).format(count, aname)
 117         return self.__mk_connection(con, aname)
 118
 119     def _mk_connection(self, name=None, count=0):
 120         return ''
 121
 122     def pinname_out(self, pname):
 123         return ''
 124
 125     def pinname_in(self, pname):
 126         return ''
 127
 128     def pinname_outen(self, pname):
 129         return ''
 130
 131     def pinname_tweak(self, pname, typ, txt):
 132         return txt
 133
 134
 135 class uart(PBase):
 136
 137     def slowimport(self):
 138         return "          import Uart16550         :: *;"
 139
 140     def slowifdecl(self):
 141         return "            interface RS232_PHY_Ifc uart{0}_coe;\n" + \
 142                "            method Bit#(1) uart{0}_intr;"
 143
 144     def num_axi_regs32(self):
 145         return 8
 146
 147     def mkslow_peripheral(self):
 148         return "        Uart16550_AXI4_Lite_Ifc uart{0} <- \n" + \
 149                "                mkUart16550(clocked_by uart_clock,\n" + \
 150                "                    reset_by uart_reset, sp_clock, sp_reset);"
 151
 152     def _mk_connection(self, name=None, count=0):
 153         return "uart{0}.slave_axi_uart"
 154
 155     def pinname_out(self, pname):
 156         return {'tx': 'coe_rs232.sout'}.get(pname, '')
 157
 158     def pinname_in(self, pname):
 159         return {'rx': 'coe_rs232.sin'}.get(pname, '')
 160
 161
 162 class rs232(PBase):
 163
 164     def slowimport(self):
 165         return "        import Uart_bs::*;\n" + \
 166                "        import RS232_modified::*;"
 167
 168     def slowifdecl(self):
 169         return "            interface RS232 uart{0}_coe;"
 170
 171     def num_axi_regs32(self):
 172         return 2
 173
 174     def mkslow_peripheral(self):
 175         return "        //Ifc_Uart_bs uart{0} <-" + \
 176                "        //       mkUart_bs(clocked_by uart_clock,\n" + \
 177                "        //          reset_by uart_reset,sp_clock, sp_reset);" +\
 178                "        Ifc_Uart_bs uart{0} <-" + \
 179                "                mkUart_bs(clocked_by sp_clock,\n" + \
 180                "                    reset_by sp_reset, sp_clock, sp_reset);"
 181
 182     def _mk_connection(self, name=None, count=0):
 183         return "uart{0}.slave_axi_uart"
 184
 185     def pinname_out(self, pname):
 186         return {'tx': 'coe_rs232.sout'}.get(pname, '')
 187
 188     def pinname_in(self, pname):
 189         return {'rx': 'coe_rs232.sin'}.get(pname, '')
 190
 191
 192 class twi(PBase):
 193
 194     def slowimport(self):
 195         return "        import I2C_top           :: *;"
 196
 197     def slowifdecl(self):
 198         return "            interface I2C_out twi{0}_out;\n" + \
 199                "            method Bit#(1) twi{0}_isint;"
 200
 201     def num_axi_regs32(self):
 202         return 8
 203
 204     def mkslow_peripheral(self):
 205         return "        I2C_IFC twi{0} <- mkI2CController();"
 206
 207     def _mk_connection(self, name=None, count=0):
 208         return "twi{0}.slave_i2c_axi"
 209
 210     def pinname_out(self, pname):
 211         return {'sda': 'out.sda_out',
 212                 'scl': 'out.scl_out'}.get(pname, '')
 213
 214     def pinname_in(self, pname):
 215         return {'sda': 'out.sda_in',
 216                 'scl': 'out.scl_in'}.get(pname, '')
 217
 218     def pinname_outen(self, pname):
 219         return {'sda': 'out.sda_outen',
 220                 'scl': 'out.scl_outen'}.get(pname, '')
 221
 222     def pinname_tweak(self, pname, typ, txt):
 223         if typ == 'outen':
 224             return "pack({0})".format(txt)
 225         return txt
 226
 227
 228 class qspi(PBase):
 229
 230     def slowimport(self):
 231         return "        import qspi              :: *;"
 232
 233     def slowifdecl(self):
 234         return "            interface QSPI_out qspi{0}_out;\n" + \
 235                "            method Bit#(1) qspi{0}_isint;"
 236
 237     def num_axi_regs32(self):
 238         return 13
 239
 240     def mkslow_peripheral(self):
 241         return "        Ifc_qspi qspi{0} <-  mkqspi();"
 242
 243     def _mk_connection(self, name=None, count=0):
 244         return "qspi{0}.slave"
 245
 246
 247 class pwm(PBase):
 248
 249     def slowimport(self):
 250         return "        import pwm::*;"
 251
 252     def slowifdecl(self):
 253         return "        interface PWMIO pwm{0}_o;"
 254
 255     def num_axi_regs32(self):
 256         return 4
 257
 258     def mkslow_peripheral(self):
 259         return "        Ifc_PWM_bus pwm{0}_bus <- mkPWM_bus(sp_clock);"
 260
 261     def _mk_connection(self, name=None, count=0):
 262         return "pwm{0}_bus.axi4_slave"
 263
 264     def pinname_out(self, pname):
 265         return {'out': 'pwm_io.pwm_o'}.get(pname, '')
 266
 267
 268 class gpio(PBase):
 269
 270     def slowimport(self):
 271         return "     import pinmux::*;\n" + \
 272                "     import mux::*;\n" + \
 273                "     import gpio::*;\n"
 274
 275     def slowifdecl(self):
 276         return "        interface GPIO_config#({1}) pad_config{0};"
 277
 278     def num_axi_regs32(self):
 279         return 2
 280
 281     def axi_slave_idx(self, idx, name, ifacenum):
 282         """ generates AXI slave number definition, except
 283             GPIO also has a muxer per bank
 284         """
 285         name = name.upper()
 286         (ret, x) = PBase.axi_slave_idx(self, idx, name, ifacenum)
 287         (ret2, x) = PBase.axi_slave_idx(self, idx, "mux", ifacenum)
 288         return ("%s\n%s" % (ret, ret2), 2)
 289
 290     def mkslow_peripheral(self):
 291         return "        MUX#(%(name)s) mux{0} <- mkmux();\n" + \
 292                "        GPIO#(%(name)s) gpio{0} <- mkgpio();" % \
 293             {'name': self.name}
 294
 295     def mk_connection(self, count):
 296         print "GPIO mk_conn", self.name, count
 297         res = []
 298         dname = self.mksuffix(self.name, count)
 299         for i, n in enumerate(['gpio' + dname, 'mux' + dname]):
 300             res.append(PBase.mk_connection(self, count, n))
 301         return '\n'.join(res)
 302
 303     def _mk_connection(self, name=None, count=0):
 304         n = self.mksuffix(name, count)
 305         if name.startswith('gpio'):
 306             return "gpio{0}.axi_slave".format(n)
 307         if name.startswith('mux'):
 308             return "mux{0}.axi_slave".format(n)
 309
 310     def mksuffix(self, name, i):
 311         if name.startswith('mux'):
 312             return name[3:]
 313         return name[4:]
 314
 315     def mk_cellconn(self, cellnum, name, count):
 316         ret = []
 317         bank = self.mksuffix(name, count)
 318         txt = "       pinmux.mux_lines.cell{0}_mux(mux{1}.mux_config.mux[{2}]);"
 319         for p in self.peripheral.pinspecs:
 320             ret.append(txt.format(cellnum, bank, p['name'][1:]))
 321             cellnum += 1
 322         return ("\n".join(ret), cellnum)
 323
 324     def pinname_out(self, pname):
 325         return "func.gpio_out[{0}]".format(pname[1:])
 326
 327     def pinname_outen(self, pname):
 328         return {'sda': 'out.sda_outen',
 329                 'scl': 'out.scl_outen'}.get(pname, '')
 330
 331     def mk_pincon(self, name, count):
 332         ret = [PBase.mk_pincon(self, name, count)]
 333         # special-case for gpio in, store in a temporary vector
 334         plen = len(self.peripheral.pinspecs)
 335         ret.append("    rule con_%s%d_in" % (name, count))
 336         ret.append("       Vector#({0},Bit#(1)) temp;".format(plen))
 337         for p in self.peripheral.pinspecs:
 338             typ = p['type']
 339             pname = p['name']
 340             idx = pname[1:]
 341             n = name
 342             sname = self.peripheral.pname(pname).format(count)
 343             ps = "pinmux.peripheral_side.%s_in" % sname
 344             ret.append("        temp[{0}]={1};".format(idx, ps))
 345         ret.append("        {0}.func.gpio_in(temp);".format(name))
 346         ret.append("    endrule")
 347         return '\n'.join(ret)
 348
 349
 350 axi_slave_declarations = """\
 351 typedef  0  SlowMaster;
 352 {0}
 353 typedef  TAdd#(LastGen_slave_num,`ifdef CLINT       1 `else 0 `endif )
 354               CLINT_slave_num;
 355 typedef  TAdd#(CLINT_slave_num  ,`ifdef PLIC        1 `else 0 `endif )
 356               Plic_slave_num;
 357 typedef  TAdd#(Plic_slave_num   ,`ifdef AXIEXP      1 `else 0 `endif )
 358               AxiExp1_slave_num;
 359 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
 360 """
 361
 362 pinmux_cellrule = """\
 363     rule connect_select_lines_pinmux;
 364 {0}
 365     endrule
 366 """
 367
 368
 369 class CallFn(object):
 370     def __init__(self, peripheral, name):
 371         self.peripheral = peripheral
 372         self.name = name
 373
 374     def __call__(self, *args):
 375         #print "__call__", self.name, self.peripheral.slow, args
 376         if not self.peripheral.slow:
 377             return ''
 378         return getattr(self.peripheral.slow, self.name)(*args[1:])
 379
 380
 381 class PeripheralIface(object):
 382     def __init__(self, ifacename):
 383         self.slow = None
 384         slow = slowfactory.getcls(ifacename)
 385         print "Iface", ifacename, slow
 386         if slow:
 387             self.slow = slow(ifacename)
 388             self.slow.peripheral = self
 389         for fname in ['slowimport', 'slowifdecl', 'mkslow_peripheral',
 390                       'mk_connection', 'mk_cellconn', 'mk_pincon']:
 391             fn = CallFn(self, fname)
 392             setattr(self, fname, types.MethodType(fn, self))
 393
 394         #print "PeripheralIface"
 395         #print dir(self)
 396
 397     def mksuffix(self, name, i):
 398         if self.slow is None:
 399             return i
 400         return self.slow.mksuffix(name, i)
 401
 402     def axi_reg_def(self, start, count):
 403         if not self.slow:
 404             return ('', 0)
 405         return self.slow.axi_reg_def(start, self.ifacename, count)
 406
 407     def axi_slave_idx(self, start, count):
 408         if not self.slow:
 409             return ('', 0)
 410         return self.slow.axi_slave_idx(start, self.ifacename, count)
 411
 412     def axi_addr_map(self, count):
 413         if not self.slow:
 414             return ''
 415         return self.slow.axi_addr_map(self.ifacename, count)
 416
 417
 418 class PeripheralInterfaces(object):
 419     def __init__(self):
 420         pass
 421
 422     def slowimport(self, *args):
 423         ret = []
 424         for (name, count) in self.ifacecount:
 425             #print "slowimport", name, self.data[name].slowimport
 426             ret.append(self.data[name].slowimport())
 427         return '\n'.join(list(filter(None, ret)))
 428
 429     def slowifdecl(self, *args):
 430         ret = []
 431         for (name, count) in self.ifacecount:
 432             for i in range(count):
 433                 ret.append(self.data[name].slowifdecl().format(i, name))
 434         return '\n'.join(list(filter(None, ret)))
 435
 436     def axi_reg_def(self, *args):
 437         ret = []
 438         start = 0x00011100  # start of AXI peripherals address
 439         for (name, count) in self.ifacecount:
 440             for i in range(count):
 441                 x = self.data[name].axi_reg_def(start, i)
 442                 #print ("ifc", name, x)
 443                 (rdef, offs) = x
 444                 ret.append(rdef)
 445                 start += offs
 446         return '\n'.join(list(filter(None, ret)))
 447
 448     def axi_slave_idx(self, *args):
 449         ret = []
 450         start = 0
 451         for (name, count) in self.ifacecount:
 452             for i in range(count):
 453                 (rdef, offs) = self.data[name].axi_slave_idx(start, i)
 454                 #print ("ifc", name, rdef, offs)
 455                 ret.append(rdef)
 456                 start += offs
 457         ret.append("typedef %d LastGen_slave_num" % (start - 1))
 458         decls = '\n'.join(list(filter(None, ret)))
 459         return axi_slave_declarations.format(decls)
 460
 461     def axi_addr_map(self, *args):
 462         ret = []
 463         for (name, count) in self.ifacecount:
 464             for i in range(count):
 465                 ret.append(self.data[name].axi_addr_map(i))
 466         return '\n'.join(list(filter(None, ret)))
 467
 468     def mkslow_peripheral(self, *args):
 469         ret = []
 470         for (name, count) in self.ifacecount:
 471             for i in range(count):
 472                 print "mkslow", name, count
 473                 x = self.data[name].mkslow_peripheral()
 474                 print name, count, x
 475                 suffix = self.data[name].mksuffix(name, i)
 476                 ret.append(x.format(suffix))
 477         return '\n'.join(list(filter(None, ret)))
 478
 479     def mk_connection(self, *args):
 480         ret = []
 481         for (name, count) in self.ifacecount:
 482             for i in range(count):
 483                 print "mk_conn", name, i
 484                 txt = self.data[name].mk_connection(i)
 485                 if name == 'gpioa':
 486                     print "txt", txt
 487                     print self.data[name].mk_connection
 488                 ret.append(txt)
 489         return '\n'.join(list(filter(None, ret)))
 490
 491     def mk_cellconn(self):
 492         ret = []
 493         cellcount = 0
 494         for (name, count) in self.ifacecount:
 495             for i in range(count):
 496                 res = self.data[name].mk_cellconn(cellcount, name, i)
 497                 if not res:
 498                     continue
 499                 (txt, cellcount) = res
 500                 ret.append(txt)
 501         ret = '\n'.join(list(filter(None, ret)))
 502         return pinmux_cellrule.format(ret)
 503
 504     def mk_pincon(self):
 505         ret = []
 506         for (name, count) in self.ifacecount:
 507             for i in range(count):
 508                 txt = self.data[name].mk_pincon(name, i)
 509                 ret.append(txt)
 510         return '\n'.join(list(filter(None, ret)))
 511
 512
 513 class PFactory(object):
 514     def getcls(self, name):
 515         for k, v in {'uart': uart,
 516                      'rs232': rs232,
 517                      'twi': twi,
 518                      'qspi': qspi,
 519                      'pwm': pwm,
 520                      'gpio': gpio
 521                      }.items():
 522             if name.startswith(k):
 523                 return v
 524         return None
 525
 526
 527 slowfactory = PFactory()
 528
 529 if __name__ == '__main__':
 530     p = uart('uart')
 531     print p.slowimport()
 532     print p.slowifdecl()
 533     i = PeripheralIface('uart')
 534     print i, i.slow
 535     i = PeripheralIface('gpioa')
 536     print i, i.slow