src/bsv/peripheral_gen.py

   1 import types
   2 from copy import deepcopy
   3
   4
   5 class PBase(object):
   6     def __init__(self, name):
   7         self.name = name
   8
   9     def axibase(self, name, ifacenum):
  10         name = name.upper()
  11         return "%(name)s%(ifacenum)dBase" % locals()
  12
  13     def axiend(self, name, ifacenum):
  14         name = name.upper()
  15         return "%(name)s%(ifacenum)dEnd" % locals()
  16
  17     def axi_reg_def(self, start, name, ifacenum):
  18         name = name.upper()
  19         offs = self.num_axi_regs32() * 4 * 16
  20         end = start + offs - 1
  21         bname = self.axibase(name, ifacenum)
  22         bend = self.axiend(name, ifacenum)
  23         comment = "%d 32-bit regs" % self.num_axi_regs32()
  24         return ("    `define%(bname)s 'h%(start)08X\n"
  25                 "    `define%(bend)s  'h%(end)08X // %(comment)s" % locals(),
  26                 offs)
  27
  28     def axi_slave_name(self, name, ifacenum):
  29         name = name.upper()
  30         return "{0}{1}_slave_num".format(name, ifacenum)
  31
  32     def axi_slave_idx(self, idx, name, ifacenum):
  33         name = self.axi_slave_name(name, ifacenum)
  34         return ("typedef {0} {1};".format(idx, name), 1)
  35
  36     def axi_addr_map(self, name, ifacenum):
  37         bname = self.axibase(name, ifacenum)
  38         bend = self.axiend(name, ifacenum)
  39         name = self.axi_slave_name(name, ifacenum)
  40         return """\
  41         if(addr>=`{0} && addr<=`{1})
  42             return tuple2(True,fromInteger(valueOf({2})));
  43         else""".format(bname, bend, name)
  44
  45     def mk_pincon(self, name, count):
  46         ret = []
  47         for p in self.peripheral.pinspecs:
  48             typ = p['type']
  49             pname = p['name']
  50             n = "{0}{1}".format(name, self.mksuffix(name, count))
  51             ret.append("    //%s %s" % (n, str(p)))
  52             sname = self.peripheral.pname(pname).format(count)
  53             ps = "pinmux.peripheral_side.%s" % sname
  54             if typ == 'out' or typ == 'inout':
  55                 ret.append("    rule con_%s%d_%s_out" % (name, count, pname))
  56                 fname = self.pinname_out(pname)
  57                 if fname:
  58                     ret.append("      {0}_out({1}.{2});".format(ps, n, fname))
  59                 fname = None
  60                 if p.get('outen'):
  61                     fname = self.pinname_outen(pname)
  62                 if fname:
  63                     ret.append("      {0}_outen({1}.{2});".format(ps, n, fname))
  64                 ret.append("    endrule")
  65             if typ == 'in' or typ == 'inout':
  66                 fname = self.pinname_in(pname)
  67                 if fname:
  68                     ret.append("    rule con_%s%d_%s_in" % (name, count, pname))
  69                     ret.append("      {1}.{2}({0}_in);".format(ps, n, fname))
  70                     ret.append("    endrule")
  71         return '\n'.join(ret)
  72
  73     def mk_cellconn(self, *args):
  74         return ''
  75
  76     def mkslow_peripheral(self):
  77         return ''
  78
  79     def mksuffix(self, name, i):
  80         return i
  81
  82     def __mk_connection(self, con, aname):
  83         txt =  "        mkConnection (slow_fabric.v_to_slaves\n" + \
  84                "                    [fromInteger(valueOf({1}))],\n" + \
  85                "                    {0});"
  86
  87         print "PBase __mk_connection", self.name, aname
  88         if not con:
  89             return ''
  90         return txt.format(con, aname)
  91
  92     def mk_connection(self, count, name=None):
  93         if name is None:
  94             name = self.name
  95         print "PBase mk_conn", self.name, count
  96         aname = self.axi_slave_name(name, count)
  97         #dname = self.mksuffix(name, count)
  98         #dname = "{0}{1}".format(name, dname)
  99         con = self._mk_connection(name, count).format(count, aname)
 100         return self.__mk_connection(con, aname)
 101
 102     def _mk_connection(self, name=None, count=0):
 103         return ''
 104
 105     def pinname_out(self, pname):
 106         return ''
 107
 108     def pinname_in(self, pname):
 109         return ''
 110
 111     def pinname_outen(self, pname):
 112         return ''
 113
 114
 115 class uart(PBase):
 116
 117     def slowimport(self):
 118         return "          import Uart16550         :: *;"
 119
 120     def slowifdecl(self):
 121         return "            interface RS232_PHY_Ifc uart{0}_coe;\n" + \
 122                "            method Bit#(1) uart{0}_intr;"
 123
 124     def num_axi_regs32(self):
 125         return 8
 126
 127     def mkslow_peripheral(self):
 128         return "        Uart16550_AXI4_Lite_Ifc uart{0} <- \n" + \
 129                "                mkUart16550(clocked_by uart_clock,\n" + \
 130                "                    reset_by uart_reset, sp_clock, sp_reset);"
 131
 132     def _mk_connection(self, name=None, count=0):
 133         return "uart{0}.slave_axi_uart"
 134
 135     def pinname_out(self, pname):
 136         return {'tx': 'coe_rs232.sout'}.get(pname, '')
 137
 138     def pinname_in(self, pname):
 139         return {'rx': 'coe_rs232.sin'}.get(pname, '')
 140
 141
 142 class rs232(PBase):
 143
 144     def slowimport(self):
 145         return "        import Uart_bs::*;\n" + \
 146                "        import RS232_modified::*;"
 147
 148     def slowifdecl(self):
 149         return "            interface RS232 uart{0}_coe;"
 150
 151     def num_axi_regs32(self):
 152         return 2
 153
 154     def mkslow_peripheral(self):
 155         return "        //Ifc_Uart_bs uart{0} <-" + \
 156                "        //       mkUart_bs(clocked_by uart_clock,\n" + \
 157                "        //          reset_by uart_reset,sp_clock, sp_reset);" +\
 158                "        Ifc_Uart_bs uart{0} <-" + \
 159                "                mkUart_bs(clocked_by sp_clock,\n" + \
 160                "                    reset_by sp_reset, sp_clock, sp_reset);"
 161
 162     def _mk_connection(self, name=None, count=0):
 163         return "uart{0}.slave_axi_uart"
 164
 165     def pinname_out(self, pname):
 166         return {'tx': 'coe_rs232.sout'}.get(pname, '')
 167
 168     def pinname_in(self, pname):
 169         return {'rx': 'coe_rs232.sin'}.get(pname, '')
 170
 171
 172 class twi(PBase):
 173
 174     def slowimport(self):
 175         return "        import I2C_top           :: *;"
 176
 177     def slowifdecl(self):
 178         return "            interface I2C_out twi{0}_out;\n" + \
 179                "            method Bit#(1) twi{0}_isint;"
 180
 181     def num_axi_regs32(self):
 182         return 8
 183
 184     def mkslow_peripheral(self):
 185         return "        I2C_IFC twi{0} <- mkI2CController();"
 186
 187     def _mk_connection(self, name=None, count=0):
 188         return "twi{0}.slave_i2c_axi"
 189
 190     def pinname_out(self, pname):
 191         return {'sda': 'out.sda_out',
 192                 'scl': 'out.scl_out'}.get(pname, '')
 193
 194     def pinname_in(self, pname):
 195         return {'sda': 'out.sda_in',
 196                 'scl': 'out.scl_in'}.get(pname, '')
 197
 198     def pinname_outen(self, pname):
 199         return {'sda': 'out.sda_outen',
 200                 'scl': 'out.scl_outen'}.get(pname, '')
 201
 202
 203
 204 class qspi(PBase):
 205
 206     def slowimport(self):
 207         return "        import qspi              :: *;"
 208
 209     def slowifdecl(self):
 210         return "            interface QSPI_out qspi{0}_out;\n" + \
 211                "            method Bit#(1) qspi{0}_isint;"
 212
 213     def num_axi_regs32(self):
 214         return 13
 215
 216     def mkslow_peripheral(self):
 217         return "        Ifc_qspi qspi{0} <-  mkqspi();"
 218
 219     def _mk_connection(self, name=None, count=0):
 220         return "qspi{0}.slave"
 221
 222
 223 class pwm(PBase):
 224
 225     def slowimport(self):
 226         return "        import pwm::*;"
 227
 228     def slowifdecl(self):
 229         return "        interface PWMIO pwm{0}_o;"
 230
 231     def num_axi_regs32(self):
 232         return 4
 233
 234     def mkslow_peripheral(self):
 235         return "        Ifc_PWM_bus pwm{0}_bus <- mkPWM_bus(sp_clock);"
 236
 237     def _mk_connection(self, name=None, count=0):
 238         return "pwm{0}_bus.axi4_slave"
 239
 240
 241 class gpio(PBase):
 242
 243     def slowimport(self):
 244         return "     import pinmux::*;\n" + \
 245                "     import mux::*;\n" + \
 246                "     import gpio::*;\n"
 247
 248     def slowifdecl(self):
 249         return "        interface GPIO_config#({1}) pad_config{0};"
 250
 251     def num_axi_regs32(self):
 252         return 2
 253
 254     def axi_slave_idx(self, idx, name, ifacenum):
 255         """ generates AXI slave number definition, except
 256             GPIO also has a muxer per bank
 257         """
 258         name = name.upper()
 259         (ret, x) = PBase.axi_slave_idx(self, idx, name, ifacenum)
 260         (ret2, x) = PBase.axi_slave_idx(self, idx, "mux", ifacenum)
 261         return ("%s\n%s" % (ret, ret2), 2)
 262
 263     def mkslow_peripheral(self):
 264         return "        MUX#(%(name)s) mux{0} <- mkmux();\n" + \
 265                "        GPIO#(%(name)s) gpio{0} <- mkgpio();" % \
 266                     {'name': self.name}
 267
 268     def mk_connection(self, count):
 269         print "GPIO mk_conn", self.name, count
 270         res = []
 271         dname = self.mksuffix(self.name, count)
 272         for i, n in enumerate(['gpio' + dname, 'mux' + dname]):
 273             res.append(PBase.mk_connection(self, count, n))
 274         return '\n'.join(res)
 275
 276     def _mk_connection(self, name=None, count=0):
 277         n = self.mksuffix(name, count)
 278         if name.startswith('gpio'):
 279             return "gpio{0}.axi_slave".format(n)
 280         if name.startswith('mux'):
 281             return "mux{0}.axi_slave".format(n)
 282
 283     def mksuffix(self, name, i):
 284         if name.startswith('mux'):
 285             return name[3:]
 286         return name[4:]
 287
 288     def mk_cellconn(self, cellnum, name, count):
 289         ret = []
 290         bank = self.mksuffix(name, count)
 291         txt = "       pinmux.mux_lines.cell{0}_mux(mux{1}.mux_config.mux[{2}]);"
 292         for p in self.peripheral.pinspecs:
 293             ret.append(txt.format(cellnum, bank, p['name'][1:]))
 294             cellnum += 1
 295         return ("\n".join(ret), cellnum)
 296
 297
 298 axi_slave_declarations = """\
 299 typedef  0  SlowMaster;
 300 {0}
 301 typedef  TAdd#(LastGen_slave_num,`ifdef CLINT       1 `else 0 `endif )
 302               CLINT_slave_num;
 303 typedef  TAdd#(CLINT_slave_num  ,`ifdef PLIC        1 `else 0 `endif )
 304               Plic_slave_num;
 305 typedef  TAdd#(Plic_slave_num   ,`ifdef AXIEXP      1 `else 0 `endif )
 306               AxiExp1_slave_num;
 307 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
 308 """
 309
 310 pinmux_cellrule = """\
 311     rule connect_select_lines_pinmux;
 312 {0}
 313     endrule
 314 """
 315
 316
 317 class CallFn(object):
 318     def __init__(self, peripheral, name):
 319         self.peripheral = peripheral
 320         self.name = name
 321
 322     def __call__(self, *args):
 323         #print "__call__", self.name, self.peripheral.slow, args
 324         if not self.peripheral.slow:
 325             return ''
 326         return getattr(self.peripheral.slow, self.name)(*args[1:])
 327
 328
 329 class PeripheralIface(object):
 330     def __init__(self, ifacename):
 331         self.slow = None
 332         slow = slowfactory.getcls(ifacename)
 333         print "Iface", ifacename, slow
 334         if slow:
 335             self.slow = slow(ifacename)
 336             self.slow.peripheral = self
 337         for fname in ['slowimport', 'slowifdecl', 'mkslow_peripheral',
 338                       'mk_connection', 'mk_cellconn', 'mk_pincon']:
 339             fn = CallFn(self, fname)
 340             setattr(self, fname, types.MethodType(fn, self))
 341
 342         #print "PeripheralIface"
 343         #print dir(self)
 344
 345     def mksuffix(self, name, i):
 346         if self.slow is None:
 347             return i
 348         return self.slow.mksuffix(name, i)
 349
 350     def axi_reg_def(self, start, count):
 351         if not self.slow:
 352             return ('', 0)
 353         return self.slow.axi_reg_def(start, self.ifacename, count)
 354
 355     def axi_slave_idx(self, start, count):
 356         if not self.slow:
 357             return ('', 0)
 358         return self.slow.axi_slave_idx(start, self.ifacename, count)
 359
 360     def axi_addr_map(self, count):
 361         if not self.slow:
 362             return ''
 363         return self.slow.axi_addr_map(self.ifacename, count)
 364
 365
 366 class PeripheralInterfaces(object):
 367     def __init__(self):
 368         pass
 369
 370     def slowimport(self, *args):
 371         ret = []
 372         for (name, count) in self.ifacecount:
 373             #print "slowimport", name, self.data[name].slowimport
 374             ret.append(self.data[name].slowimport())
 375         return '\n'.join(list(filter(None, ret)))
 376
 377     def slowifdecl(self, *args):
 378         ret = []
 379         for (name, count) in self.ifacecount:
 380             for i in range(count):
 381                 ret.append(self.data[name].slowifdecl().format(i, name))
 382         return '\n'.join(list(filter(None, ret)))
 383
 384     def axi_reg_def(self, *args):
 385         ret = []
 386         start = 0x00011100  # start of AXI peripherals address
 387         for (name, count) in self.ifacecount:
 388             for i in range(count):
 389                 x = self.data[name].axi_reg_def(start, i)
 390                 #print ("ifc", name, x)
 391                 (rdef, offs) = x
 392                 ret.append(rdef)
 393                 start += offs
 394         return '\n'.join(list(filter(None, ret)))
 395
 396     def axi_slave_idx(self, *args):
 397         ret = []
 398         start = 0
 399         for (name, count) in self.ifacecount:
 400             for i in range(count):
 401                 (rdef, offs) = self.data[name].axi_slave_idx(start, i)
 402                 #print ("ifc", name, rdef, offs)
 403                 ret.append(rdef)
 404                 start += offs
 405         ret.append("typedef %d LastGen_slave_num" % (start - 1))
 406         decls = '\n'.join(list(filter(None, ret)))
 407         return axi_slave_declarations.format(decls)
 408
 409     def axi_addr_map(self, *args):
 410         ret = []
 411         for (name, count) in self.ifacecount:
 412             for i in range(count):
 413                 ret.append(self.data[name].axi_addr_map(i))
 414         return '\n'.join(list(filter(None, ret)))
 415
 416     def mkslow_peripheral(self, *args):
 417         ret = []
 418         for (name, count) in self.ifacecount:
 419             for i in range(count):
 420                 print "mkslow", name, count
 421                 x = self.data[name].mkslow_peripheral()
 422                 print name, count, x
 423                 suffix = self.data[name].mksuffix(name, i)
 424                 ret.append(x.format(suffix))
 425         return '\n'.join(list(filter(None, ret)))
 426
 427     def mk_connection(self, *args):
 428         ret = []
 429         for (name, count) in self.ifacecount:
 430             for i in range(count):
 431                 print "mk_conn", name, i
 432                 txt = self.data[name].mk_connection(i)
 433                 if name == 'gpioa':
 434                     print "txt", txt
 435                     print self.data[name].mk_connection
 436                 ret.append(txt)
 437         return '\n'.join(list(filter(None, ret)))
 438
 439     def mk_cellconn(self):
 440         ret = []
 441         cellcount = 0
 442         for (name, count) in self.ifacecount:
 443             for i in range(count):
 444                 res = self.data[name].mk_cellconn(cellcount, name, i)
 445                 if not res:
 446                     continue
 447                 (txt, cellcount) = res
 448                 ret.append(txt)
 449         ret = '\n'.join(list(filter(None, ret)))
 450         return pinmux_cellrule.format(ret)
 451
 452     def mk_pincon(self):
 453         ret = []
 454         for (name, count) in self.ifacecount:
 455             for i in range(count):
 456                 txt = self.data[name].mk_pincon(name, i)
 457                 ret.append(txt)
 458         return '\n'.join(list(filter(None, ret)))
 459
 460 class PFactory(object):
 461     def getcls(self, name):
 462         for k, v in {'uart': uart,
 463                 'rs232': rs232,
 464                 'twi': twi,
 465                 'qspi': qspi,
 466                 'pwm': pwm,
 467                 'gpio': gpio
 468                 }.items():
 469             if name.startswith(k):
 470                 return v
 471         return None
 472
 473
 474 slowfactory = PFactory()
 475
 476 if __name__ == '__main__':
 477     p = uart('uart')
 478     print p.slowimport()
 479     print p.slowifdecl()
 480     i = PeripheralIface('uart')
 481     print i, i.slow
 482     i = PeripheralIface('gpioa')
 483     print i, i.slow