src/bsv/peripheral_gen.py

   1 import types
   2 from copy import deepcopy
   3
   4
   5 class PBase(object):
   6     def __init__(self, name):
   7         self.name = name
   8
   9     def axibase(self, name, ifacenum):
  10         name = name.upper()
  11         return "%(name)s%(ifacenum)dBase" % locals()
  12
  13     def axiend(self, name, ifacenum):
  14         name = name.upper()
  15         return "%(name)s%(ifacenum)dEnd" % locals()
  16
  17     def axi_reg_def(self, start, name, ifacenum):
  18         name = name.upper()
  19         offs = self.num_axi_regs32() * 4 * 16
  20         end = start + offs - 1
  21         bname = self.axibase(name, ifacenum)
  22         bend = self.axiend(name, ifacenum)
  23         comment = "%d 32-bit regs" % self.num_axi_regs32()
  24         return ("    `define%(bname)s 'h%(start)08X\n"
  25                 "    `define%(bend)s  'h%(end)08X // %(comment)s" % locals(),
  26                 offs)
  27
  28     def axi_slave_name(self, name, ifacenum):
  29         name = name.upper()
  30         return "{0}{1}_slave_num".format(name, ifacenum)
  31
  32     def axi_slave_idx(self, idx, name, ifacenum):
  33         name = self.axi_slave_name(name, ifacenum)
  34         return ("typedef {0} {1};".format(idx, name), 1)
  35
  36     def axi_addr_map(self, name, ifacenum):
  37         bname = self.axibase(name, ifacenum)
  38         bend = self.axiend(name, ifacenum)
  39         name = self.axi_slave_name(name, ifacenum)
  40         return """\
  41         if(addr>=`{0} && addr<=`{1})
  42             return tuple2(True,fromInteger(valueOf({2})));
  43         else""".format(bname, bend, name)
  44
  45     def mkslow_peripheral(self):
  46         return ''
  47
  48     def __mk_connection(self, con, aname):
  49         txt =  "        mkConnection (slow_fabric.v_to_slaves\n" + \
  50                "                    [fromInteger(valueOf({1}))],\n" + \
  51                "                    {0});"
  52
  53         print "PBase __mk_connection", self.name, aname
  54         if not con:
  55             return ''
  56         return txt.format(con, aname)
  57
  58     def mk_connection(self, count, name=None):
  59         if name is None:
  60             name = self.name
  61         print "PBase mk_conn", self.name, count
  62         aname = self.axi_slave_name(name, count)
  63         con = self._mk_connection(name).format(count, aname)
  64         return self.__mk_connection(con, aname)
  65
  66     def _mk_connection(self, name=None):
  67         return ''
  68
  69
  70 class uart(PBase):
  71
  72     def slowimport(self):
  73         return "          import Uart16550         :: *;"
  74
  75     def slowifdecl(self):
  76         return "            interface RS232_PHY_Ifc uart{0}_coe;\n" + \
  77                "            method Bit#(1) uart{0}_intr;"
  78
  79     def num_axi_regs32(self):
  80         return 8
  81
  82     def mkslow_peripheral(self):
  83         return "        Uart16550_AXI4_Lite_Ifc uart{0} <- \n" + \
  84                "                mkUart16550(clocked_by uart_clock,\n" + \
  85                "                    reset_by uart_reset, sp_clock, sp_reset);"
  86
  87     def _mk_connection(self, name=None):
  88         return "uart{0}.slave_axi_uart"
  89
  90
  91
  92 class rs232(PBase):
  93
  94     def slowimport(self):
  95         return "        import Uart_bs::*;\n" + \
  96                "        import RS232_modified::*;"
  97
  98     def slowifdecl(self):
  99         return "            interface RS232 uart{0}_coe;"
 100
 101     def num_axi_regs32(self):
 102         return 2
 103
 104     def mkslow_peripheral(self):
 105         return "        //Ifc_Uart_bs uart{0} <-" + \
 106                "        //       mkUart_bs(clocked_by uart_clock,\n" + \
 107                "        //          reset_by uart_reset,sp_clock, sp_reset);" +\
 108                "        Ifc_Uart_bs uart{0} <-" + \
 109                "                mkUart_bs(clocked_by sp_clock,\n" + \
 110                "                    reset_by sp_reset, sp_clock, sp_reset);"
 111
 112     def _mk_connection(self, name=None):
 113         return "uart{0}.slave_axi_uart"
 114
 115
 116 class twi(PBase):
 117
 118     def slowimport(self):
 119         return "        import I2C_top           :: *;"
 120
 121     def slowifdecl(self):
 122         return "            interface I2C_out i2c{0}_out;\n" + \
 123                "            method Bit#(1) i2c{0}_isint;"
 124
 125     def num_axi_regs32(self):
 126         return 8
 127
 128     def mkslow_peripheral(self):
 129         return "        I2C_IFC i2c{0} <- mkI2CController();"
 130
 131     def _mk_connection(self, name=None):
 132         return "i2c{0}.slave_i2c_axi"
 133
 134
 135 class qspi(PBase):
 136
 137     def slowimport(self):
 138         return "        import qspi              :: *;"
 139
 140     def slowifdecl(self):
 141         return "            interface QSPI_out qspi{0}_out;\n" + \
 142                "            method Bit#(1) qspi{0}_isint;"
 143
 144     def num_axi_regs32(self):
 145         return 13
 146
 147     def mkslow_peripheral(self):
 148         return "        Ifc_qspi qspi{0} <-  mkqspi();"
 149
 150     def _mk_connection(self, name=None):
 151         return "qspi{0}.slave"
 152
 153
 154 class pwm(PBase):
 155
 156     def slowimport(self):
 157         return "        import pwm::*;"
 158
 159     def slowifdecl(self):
 160         return "        interface PWMIO pwm{0}_o;"
 161
 162     def num_axi_regs32(self):
 163         return 4
 164
 165     def mkslow_peripheral(self):
 166         return "        Ifc_PWM_bus pwm{0}_bus <- mkPWM_bus(sp_clock);"
 167
 168     def _mk_connection(self, name=None):
 169         return "pwm{0}_bus.axi4_slave"
 170
 171
 172 class gpio(PBase):
 173
 174     def slowimport(self):
 175         return "     import pinmux::*;\n" + \
 176                "     import mux::*;\n" + \
 177                "     import gpio::*;\n"
 178
 179     def slowifdecl(self):
 180         return "        interface GPIO_config#({1}) pad_config{0};"
 181
 182     def num_axi_regs32(self):
 183         return 2
 184
 185     def axi_slave_idx(self, idx, name, ifacenum):
 186         """ generates AXI slave number definition, except
 187             GPIO also has a muxer per bank
 188         """
 189         name = name.upper()
 190         (ret, x) = PBase.axi_slave_idx(self, idx, name, ifacenum)
 191         (ret2, x) = PBase.axi_slave_idx(self, idx, "mux", ifacenum)
 192         return ("%s\n%s" % (ret, ret2), 2)
 193
 194     def mkslow_peripheral(self):
 195         return "        MUX#(%(name)s) mux{0} <- mkmux();\n" + \
 196                "        GPIO#(%(name)s) gpio{0} <- mkgpio();" % \
 197                     {'name': self.name}
 198
 199     def mk_connection(self, count):
 200         print "GPIO mk_conn", self.name, count
 201         res = []
 202         for i, n in enumerate(['gpio', 'mux']):
 203             res.append(PBase.mk_connection(self, count, n))
 204         return '\n'.join(res)
 205
 206     def _mk_connection(self, name=None):
 207         if name.startswith('gpio'):
 208             return "gpio{0}.axi_slave"
 209         if name.startswith('mux'):
 210             return "mux{0}.axi_slave"
 211
 212     def mk_cellconn(self, cellnum, bank, count):
 213         ret = []
 214         bank = bank[4:] # strip off "gpio"
 215         txt = "       pinmux.mux_lines.cell{0}_mux(mux{1}.mux_config.mux[{2}]);"
 216         return txt.format(cellnum, bank, count)
 217
 218
 219 axi_slave_declarations = """\
 220 typedef  0  SlowMaster;
 221 {0}
 222 typedef  TAdd#(LastGen_slave_num,`ifdef CLINT       1 `else 0 `endif )
 223               CLINT_slave_num;
 224 typedef  TAdd#(CLINT_slave_num  ,`ifdef PLIC        1 `else 0 `endif )
 225               Plic_slave_num;
 226 typedef  TAdd#(Plic_slave_num   ,`ifdef AXIEXP      1 `else 0 `endif )
 227               AxiExp1_slave_num;
 228 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
 229 """
 230
 231 pinmux_cellrule = """\
 232     rule connect_select_lines_pinmux;
 233 {0}
 234     endrule
 235 """
 236
 237
 238 class CallFn(object):
 239     def __init__(self, peripheral, name):
 240         self.peripheral = peripheral
 241         self.name = name
 242
 243     def __call__(self, *args):
 244         #print "__call__", self.name, self.peripheral.slow, args
 245         if not self.peripheral.slow:
 246             return ''
 247         return getattr(self.peripheral.slow, self.name)(*args[1:])
 248
 249
 250 class PeripheralIface(object):
 251     def __init__(self, ifacename):
 252         self.slow = None
 253         slow = slowfactory.getcls(ifacename)
 254         print "Iface", ifacename, slow
 255         if slow:
 256             self.slow = slow(ifacename)
 257         for fname in ['slowimport', 'slowifdecl', 'mkslow_peripheral',
 258                       'mk_connection']:
 259             fn = CallFn(self, fname)
 260             setattr(self, fname, types.MethodType(fn, self))
 261
 262         #print "PeripheralIface"
 263         #print dir(self)
 264
 265     def axi_reg_def(self, start, count):
 266         if not self.slow:
 267             return ('', 0)
 268         return self.slow.axi_reg_def(start, self.ifacename, count)
 269
 270     def axi_slave_idx(self, start, count):
 271         if not self.slow:
 272             return ('', 0)
 273         return self.slow.axi_slave_idx(start, self.ifacename, count)
 274
 275     def axi_addr_map(self, count):
 276         if not self.slow:
 277             return ''
 278         return self.slow.axi_addr_map(self.ifacename, count)
 279
 280
 281 class PeripheralInterfaces(object):
 282     def __init__(self):
 283         pass
 284
 285     def slowimport(self, *args):
 286         ret = []
 287         for (name, count) in self.ifacecount:
 288             #print "slowimport", name, self.data[name].slowimport
 289             ret.append(self.data[name].slowimport())
 290         return '\n'.join(list(filter(None, ret)))
 291
 292     def slowifdecl(self, *args):
 293         ret = []
 294         for (name, count) in self.ifacecount:
 295             for i in range(count):
 296                 ret.append(self.data[name].slowifdecl().format(i, name))
 297         return '\n'.join(list(filter(None, ret)))
 298
 299     def axi_reg_def(self, *args):
 300         ret = []
 301         start = 0x00011100  # start of AXI peripherals address
 302         for (name, count) in self.ifacecount:
 303             for i in range(count):
 304                 x = self.data[name].axi_reg_def(start, i)
 305                 #print ("ifc", name, x)
 306                 (rdef, offs) = x
 307                 ret.append(rdef)
 308                 start += offs
 309         return '\n'.join(list(filter(None, ret)))
 310
 311     def axi_slave_idx(self, *args):
 312         ret = []
 313         start = 0
 314         for (name, count) in self.ifacecount:
 315             for i in range(count):
 316                 (rdef, offs) = self.data[name].axi_slave_idx(start, i)
 317                 #print ("ifc", name, rdef, offs)
 318                 ret.append(rdef)
 319                 start += offs
 320         ret.append("typedef %d LastGen_slave_num" % (start - 1))
 321         decls = '\n'.join(list(filter(None, ret)))
 322         return axi_slave_declarations.format(decls)
 323
 324     def axi_addr_map(self, *args):
 325         ret = []
 326         for (name, count) in self.ifacecount:
 327             for i in range(count):
 328                 ret.append(self.data[name].axi_addr_map(i))
 329         return '\n'.join(list(filter(None, ret)))
 330
 331     def mkslow_peripheral(self, *args):
 332         ret = []
 333         for (name, count) in self.ifacecount:
 334             for i in range(count):
 335                 x = self.data[name].mkslow_peripheral()
 336                 print name, count, x
 337                 ret.append(x.format(i))
 338         return '\n'.join(list(filter(None, ret)))
 339
 340     def mk_connection(self, *args):
 341         ret = []
 342         for (name, count) in self.ifacecount:
 343             for i in range(count):
 344                 print "mk_conn", name, i
 345                 txt = self.data[name].mk_connection(i)
 346                 if name == 'gpioa':
 347                     print "txt", txt
 348                     print self.data[name].mk_connection
 349                 ret.append(txt)
 350         return '\n'.join(list(filter(None, ret)))
 351
 352     def mk_cellconn(self):
 353         ret = []
 354         cellcount = 0
 355         for (name, count) in self.ifacecount:
 356             for i in range(count):
 357                 txt = self.data[name].mk_cellcon(cellcount, name, i)
 358                 cellcount += 1
 359                 ret.append(txt)
 360         ret = '\n'.join(list(filter(None, ret)))
 361         return pinmux_cellrule.format(ret)
 362
 363 class PFactory(object):
 364     def getcls(self, name):
 365         for k, v in {'uart': uart,
 366                 'rs232': rs232,
 367                 'twi': twi,
 368                 'qspi': qspi,
 369                 'pwm': pwm,
 370                 'gpio': gpio
 371                 }.items():
 372             if name.startswith(k):
 373                 return v
 374         return None
 375
 376
 377 slowfactory = PFactory()
 378
 379 if __name__ == '__main__':
 380     p = uart('uart')
 381     print p.slowimport()
 382     print p.slowifdecl()
 383     i = PeripheralIface('uart')
 384     print i, i.slow
 385     i = PeripheralIface('gpioa')
 386     print i, i.slow