src/bsv/peripheral_gen.py

   1 import types
   2 from copy import deepcopy
   3
   4
   5 class PBase(object):
   6     def __init__(self, name):
   7         self.name = name
   8
   9     def axibase(self, name, ifacenum):
  10         name = name.upper()
  11         return "%(name)s%(ifacenum)dBase" % locals()
  12
  13     def axiend(self, name, ifacenum):
  14         name = name.upper()
  15         return "%(name)s%(ifacenum)dEnd" % locals()
  16
  17     def axi_reg_def(self, start, name, ifacenum):
  18         name = name.upper()
  19         offs = self.num_axi_regs32() * 4 * 16
  20         end = start + offs - 1
  21         bname = self.axibase(name, ifacenum)
  22         bend = self.axiend(name, ifacenum)
  23         comment = "%d 32-bit regs" % self.num_axi_regs32()
  24         return ("    `define %(bname)s 'h%(start)08X\n"
  25                 "    `define %(bend)s  'h%(end)08X // %(comment)s" % locals(),
  26                 offs)
  27
  28     def axi_slave_name(self, name, ifacenum):
  29         name = name.upper()
  30         return "{0}{1}_slave_num".format(name, ifacenum)
  31
  32     def axi_slave_idx(self, idx, name, ifacenum):
  33         name = self.axi_slave_name(name, ifacenum)
  34         return ("typedef {0} {1};".format(idx, name), 1)
  35
  36     def axi_addr_map(self, name, ifacenum):
  37         bname = self.axibase(name, ifacenum)
  38         bend = self.axiend(name, ifacenum)
  39         name = self.axi_slave_name(name, ifacenum)
  40         return """\
  41         if(addr>=`{0} && addr<=`{1})
  42             return tuple2(True,fromInteger(valueOf({2})));
  43         else""".format(bname, bend, name)
  44
  45     def mk_pincon(self, name, count):
  46         # TODO: really should be using bsv.interface_decl.Interfaces
  47         # pin-naming rules.... logic here is hard-coded to duplicate
  48         # it (see Interface.__init__ outen)
  49         ret = []
  50         for p in self.peripheral.pinspecs:
  51             typ = p['type']
  52             pname = p['name']
  53             #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
  54             n = name  # "{0}{1}".format(self.name, self.mksuffix(name, count))
  55             ret.append("    //%s %s" % (n, str(p)))
  56             sname = self.peripheral.pname(pname).format(count)
  57             ps = "pinmux.peripheral_side.%s" % sname
  58             if typ == 'out' or typ == 'inout':
  59                 ret.append("    rule con_%s%d_%s_out;" % (name, count, pname))
  60                 fname = self.pinname_out(pname)
  61                 if fname:
  62                     if p.get('outen'):
  63                         ps_ = ps + '_out'
  64                     else:
  65                         ps_ = ps
  66                     if not n.startswith('gpio'): # XXX EURGH! horrible hack
  67                       n_ = "{0}{1}".format(n, count)
  68                     else:
  69                       n_ = n
  70                     ret.append("      {0}({1}.{2});".format(ps_, n_, fname))
  71                 fname = None
  72                 if p.get('outen'):
  73                     fname = self.pinname_outen(pname)
  74                 if fname:
  75                     if isinstance(fname, str):
  76                         fname = "{0}{1}.{2}".format(n, count, fname)
  77                     fname = self.pinname_tweak(pname, 'outen', fname)
  78                     ret.append("      {0}_outen({1});".format(ps, fname))
  79                 ret.append("    endrule")
  80             if typ == 'in' or typ == 'inout':
  81                 fname = self.pinname_in(pname)
  82                 if fname:
  83                     if p.get('outen'):
  84                         ps_ = ps + '_in'
  85                     else:
  86                         ps_ = ps
  87                     ret.append(
  88                         "    rule con_%s%d_%s_in;" %
  89                         (name, count, pname))
  90                     n_ = "{0}{1}".format(n, count)
  91                     ret.append("      {1}.{2}({0});".format(ps_, n_, fname))
  92                     ret.append("    endrule")
  93         return '\n'.join(ret)
  94
  95     def mk_cellconn(self, *args):
  96         return ''
  97
  98     def mkslow_peripheral(self, size=0):
  99         return ''
 100
 101     def mksuffix(self, name, i):
 102         return i
 103
 104     def __mk_connection(self, con, aname):
 105         txt = "        mkConnection (slow_fabric.v_to_slaves\n" + \
 106             "                    [fromInteger(valueOf({1}))],\n" + \
 107             "                    {0});"
 108
 109         print "PBase __mk_connection", self.name, aname
 110         if not con:
 111             return ''
 112         return txt.format(con, aname)
 113
 114     def mk_connection(self, count, name=None):
 115         if name is None:
 116             name = self.name
 117         print "PBase mk_conn", self.name, count
 118         aname = self.axi_slave_name(name, count)
 119         #dname = self.mksuffix(name, count)
 120         #dname = "{0}{1}".format(name, dname)
 121         con = self._mk_connection(name, count).format(count, aname)
 122         return self.__mk_connection(con, aname)
 123
 124     def _mk_connection(self, name=None, count=0):
 125         return ''
 126
 127     def pinname_out(self, pname):
 128         return ''
 129
 130     def pinname_in(self, pname):
 131         return ''
 132
 133     def pinname_outen(self, pname):
 134         return ''
 135
 136     def pinname_tweak(self, pname, typ, txt):
 137         return txt
 138
 139
 140 class uart(PBase):
 141
 142     def slowimport(self):
 143         return "          import Uart16550         :: *;"
 144
 145     def slowifdecl(self):
 146         return "            interface RS232_PHY_Ifc uart{0}_coe;\n" + \
 147                "            method Bit#(1) uart{0}_intr;"
 148
 149     def num_axi_regs32(self):
 150         return 8
 151
 152     def mkslow_peripheral(self, size=0):
 153         return "        Uart16550_AXI4_Lite_Ifc uart{0} <- \n" + \
 154                "                mkUart16550(clocked_by uart_clock,\n" + \
 155                "                    reset_by uart_reset, sp_clock, sp_reset);"
 156
 157     def _mk_connection(self, name=None, count=0):
 158         return "uart{0}.slave_axi_uart"
 159
 160     def pinname_out(self, pname):
 161         return {'tx': 'coe_rs232.sout'}.get(pname, '')
 162
 163     def pinname_in(self, pname):
 164         return {'rx': 'coe_rs232.sin'}.get(pname, '')
 165
 166
 167 class rs232(PBase):
 168
 169     def slowimport(self):
 170         return "        import Uart_bs::*;\n" + \
 171                "        import RS232_modified::*;"
 172
 173     def slowifdecl(self):
 174         return "            interface RS232 uart{0}_coe;"
 175
 176     def num_axi_regs32(self):
 177         return 2
 178
 179     def mkslow_peripheral(self, size=0):
 180         return "        //Ifc_Uart_bs uart{0} <-" + \
 181                "        //       mkUart_bs(clocked_by uart_clock,\n" + \
 182                "        //          reset_by uart_reset,sp_clock, sp_reset);" +\
 183                "        Ifc_Uart_bs uart{0} <-" + \
 184                "                mkUart_bs(clocked_by sp_clock,\n" + \
 185                "                    reset_by sp_reset, sp_clock, sp_reset);"
 186
 187     def _mk_connection(self, name=None, count=0):
 188         return "uart{0}.slave_axi_uart"
 189
 190     def pinname_out(self, pname):
 191         return {'tx': 'coe_rs232.sout'}.get(pname, '')
 192
 193     def pinname_in(self, pname):
 194         return {'rx': 'coe_rs232.sin'}.get(pname, '')
 195
 196
 197 class twi(PBase):
 198
 199     def slowimport(self):
 200         return "        import I2C_top           :: *;"
 201
 202     def slowifdecl(self):
 203         return "            interface I2C_out twi{0}_out;\n" + \
 204                "            method Bit#(1) twi{0}_isint;"
 205
 206     def num_axi_regs32(self):
 207         return 8
 208
 209     def mkslow_peripheral(self, size=0):
 210         return "        I2C_IFC twi{0} <- mkI2CController();"
 211
 212     def _mk_connection(self, name=None, count=0):
 213         return "twi{0}.slave_i2c_axi"
 214
 215     def pinname_out(self, pname):
 216         return {'sda': 'out.sda_out',
 217                 'scl': 'out.scl_out'}.get(pname, '')
 218
 219     def pinname_in(self, pname):
 220         return {'sda': 'out.sda_in',
 221                 'scl': 'out.scl_in'}.get(pname, '')
 222
 223     def pinname_outen(self, pname):
 224         return {'sda': 'out.sda_out_en',
 225                 'scl': 'out.scl_out_en'}.get(pname, '')
 226
 227     def pinname_tweak(self, pname, typ, txt):
 228         if typ == 'outen':
 229             return "pack({0})".format(txt)
 230         return txt
 231
 232
 233 class qspi(PBase):
 234
 235     def slowimport(self):
 236         return "        import qspi              :: *;"
 237
 238     def slowifdecl(self):
 239         return "            interface QSPI_out qspi{0}_out;\n" + \
 240                "            method Bit#(1) qspi{0}_isint;"
 241
 242     def num_axi_regs32(self):
 243         return 13
 244
 245     def mkslow_peripheral(self, size=0):
 246         return "        Ifc_qspi qspi{0} <-  mkqspi();"
 247
 248     def _mk_connection(self, name=None, count=0):
 249         return "qspi{0}.slave"
 250
 251     def pinname_out(self, pname):
 252         return {'ck': 'out.clk_o',
 253                 'nss': 'out.ncs_o',
 254                 'io0': 'out.io_o[0]',
 255                 'io1': 'out.io_o[1]',
 256                 'io2': 'out.io_o[2]',
 257                 'io3': 'out.io_o[3]',
 258                 }.get(pname, '')
 259
 260     def pinname_outen(self, pname):
 261         return {'ck': 1,
 262                 'nss': 1,
 263                 'io0': 'out.io_enable[0]',
 264                 'io1': 'out.io_enable[1]',
 265                 'io2': 'out.io_enable[2]',
 266                 'io3': 'out.io_enable[3]',
 267                 }.get(pname, '')
 268
 269     def mk_pincon(self, name, count):
 270         ret = [PBase.mk_pincon(self, name, count)]
 271         # special-case for gpio in, store in a temporary vector
 272         plen = len(self.peripheral.pinspecs)
 273         ret.append("    // XXX NSS and CLK are hard-coded master")
 274         ret.append("    // TODO: must add qspi slave-mode")
 275         ret.append("    // all ins done in one rule from 4-bitfield")
 276         ret.append("    rule con_%s%d_io_in;" % (name, count))
 277         ret.append("       {0}{1}.out.io_i({{".format(name, count))
 278         for i, p in enumerate(self.peripheral.pinspecs):
 279             typ = p['type']
 280             pname = p['name']
 281             if not pname.startswith('io'):
 282                 continue
 283             idx = pname[1:]
 284             n = name
 285             sname = self.peripheral.pname(pname).format(count)
 286             ps = "pinmux.peripheral_side.%s_in" % sname
 287             comma = '' if i == 5 else ','
 288             ret.append("            {0}{1}".format(ps, comma))
 289         ret.append("        });")
 290         ret.append("    endrule")
 291         return '\n'.join(ret)
 292
 293
 294 class pwm(PBase):
 295
 296     def slowimport(self):
 297         return "        import pwm::*;"
 298
 299     def slowifdecl(self):
 300         return "        interface PWMIO pwm{0}_io;"
 301
 302     def num_axi_regs32(self):
 303         return 4
 304
 305     def mkslow_peripheral(self, size=0):
 306         return "        Ifc_PWM_bus pwm{0} <- mkPWM_bus(sp_clock);"
 307
 308     def _mk_connection(self, name=None, count=0):
 309         return "pwm{0}.axi4_slave"
 310
 311     def pinname_out(self, pname):
 312         return {'out': 'pwm_io.pwm_o'}.get(pname, '')
 313
 314
 315 class gpio(PBase):
 316
 317     def slowimport(self):
 318         return "     import pinmux::*;\n" + \
 319                "     import mux::*;\n" + \
 320                "     import gpio::*;\n"
 321
 322     def slowifdecl(self):
 323         size = len(self.peripheral.pinspecs)
 324         return "        interface GPIO_config#(%d) pad_config{0};" % size
 325
 326     def num_axi_regs32(self):
 327         return 2
 328
 329     def axi_slave_idx(self, idx, name, ifacenum):
 330         """ generates AXI slave number definition, except
 331             GPIO also has a muxer per bank
 332         """
 333         name = name.upper()
 334         mname = 'mux' + name[4:]
 335         mname = mname.upper()
 336         print "AXIslavenum", name,  mname
 337         (ret, x) = PBase.axi_slave_idx(self, idx, name, ifacenum)
 338         (ret2, x) = PBase.axi_slave_idx(self, idx, mname, ifacenum)
 339         return ("%s\n%s" % (ret, ret2), 2)
 340
 341     def mkslow_peripheral(self, size=0):
 342         print "gpioslow", self.peripheral,  dir(self.peripheral)
 343         size = len(self.peripheral.pinspecs)
 344         return "        MUX#(%d) mux{0} <- mkmux();\n" % size + \
 345                "        GPIO#(%d) gpio{0} <- mkgpio();" % size
 346
 347     def mk_connection(self, count):
 348         print "GPIO mk_conn", self.name, count
 349         res = []
 350         dname = self.mksuffix(self.name, count)
 351         for i, n in enumerate(['gpio' + dname, 'mux' + dname]):
 352             res.append(PBase.mk_connection(self, count, n))
 353         return '\n'.join(res)
 354
 355     def _mk_connection(self, name=None, count=0):
 356         n = self.mksuffix(name, count)
 357         if name.startswith('gpio'):
 358             return "gpio{0}.axi_slave".format(n)
 359         if name.startswith('mux'):
 360             return "mux{0}.axi_slave".format(n)
 361
 362     def mksuffix(self, name, i):
 363         if name.startswith('mux'):
 364             return name[3:]
 365         return name[4:]
 366
 367     def mk_cellconn(self, cellnum, name, count):
 368         ret = []
 369         bank = self.mksuffix(name, count)
 370         txt = "       pinmux.mux_lines.cell{0}_mux(mux{1}.mux_config.mux[{2}]);"
 371         for p in self.peripheral.pinspecs:
 372             ret.append(txt.format(cellnum, bank, p['name'][1:]))
 373             cellnum += 1
 374         return ("\n".join(ret), cellnum)
 375
 376     def pinname_out(self, pname):
 377         return "func.gpio_out[{0}]".format(pname[1:])
 378
 379     def pinname_outen(self, pname):
 380         return {'sda': 'out.sda_outen',
 381                 'scl': 'out.scl_outen'}.get(pname, '')
 382
 383     def mk_pincon(self, name, count):
 384         ret = [PBase.mk_pincon(self, name, count)]
 385         # special-case for gpio in, store in a temporary vector
 386         plen = len(self.peripheral.pinspecs)
 387         ret.append("    rule con_%s%d_in;" % (name, count))
 388         ret.append("       Vector#({0},Bit#(1)) temp;".format(plen))
 389         for p in self.peripheral.pinspecs:
 390             typ = p['type']
 391             pname = p['name']
 392             idx = pname[1:]
 393             n = name
 394             sname = self.peripheral.pname(pname).format(count)
 395             ps = "pinmux.peripheral_side.%s_in" % sname
 396             ret.append("        temp[{0}]={1};".format(idx, ps))
 397         ret.append("        {0}.func.gpio_in(temp);".format(name))
 398         ret.append("    endrule")
 399         return '\n'.join(ret)
 400
 401
 402 axi_slave_declarations = """\
 403 typedef  0  SlowMaster;
 404 {0}
 405 typedef  TAdd#(LastGen_slave_num,`ifdef CLINT       1 `else 0 `endif )
 406               CLINT_slave_num;
 407 typedef  TAdd#(CLINT_slave_num  ,`ifdef PLIC        1 `else 0 `endif )
 408               Plic_slave_num;
 409 typedef  TAdd#(Plic_slave_num   ,`ifdef AXIEXP      1 `else 0 `endif )
 410               AxiExp1_slave_num;
 411 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
 412 """
 413
 414 pinmux_cellrule = """\
 415     rule connect_select_lines_pinmux;
 416 {0}
 417     endrule
 418 """
 419
 420
 421 class CallFn(object):
 422     def __init__(self, peripheral, name):
 423         self.peripheral = peripheral
 424         self.name = name
 425
 426     def __call__(self, *args):
 427         #print "__call__", self.name, self.peripheral.slow, args
 428         if not self.peripheral.slow:
 429             return ''
 430         return getattr(self.peripheral.slow, self.name)(*args[1:])
 431
 432
 433 class PeripheralIface(object):
 434     def __init__(self, ifacename):
 435         self.slow = None
 436         slow = slowfactory.getcls(ifacename)
 437         print "Iface", ifacename, slow
 438         if slow:
 439             self.slow = slow(ifacename)
 440             self.slow.peripheral = self
 441         for fname in ['slowimport', 'slowifdecl', 'mkslow_peripheral',
 442                       'mk_connection', 'mk_cellconn', 'mk_pincon']:
 443             fn = CallFn(self, fname)
 444             setattr(self, fname, types.MethodType(fn, self))
 445
 446         #print "PeripheralIface"
 447         #print dir(self)
 448
 449     def mksuffix(self, name, i):
 450         if self.slow is None:
 451             return i
 452         return self.slow.mksuffix(name, i)
 453
 454     def axi_reg_def(self, start, count):
 455         if not self.slow:
 456             return ('', 0)
 457         return self.slow.axi_reg_def(start, self.ifacename, count)
 458
 459     def axi_slave_idx(self, start, count):
 460         if not self.slow:
 461             return ('', 0)
 462         return self.slow.axi_slave_idx(start, self.ifacename, count)
 463
 464     def axi_addr_map(self, count):
 465         if not self.slow:
 466             return ''
 467         return self.slow.axi_addr_map(self.ifacename, count)
 468
 469
 470 class PeripheralInterfaces(object):
 471     def __init__(self):
 472         pass
 473
 474     def slowimport(self, *args):
 475         ret = []
 476         for (name, count) in self.ifacecount:
 477             #print "slowimport", name, self.data[name].slowimport
 478             ret.append(self.data[name].slowimport())
 479         return '\n'.join(list(filter(None, ret)))
 480
 481     def slowifdecl(self, *args):
 482         ret = []
 483         for (name, count) in self.ifacecount:
 484             for i in range(count):
 485                 ret.append(self.data[name].slowifdecl().format(i, name))
 486         return '\n'.join(list(filter(None, ret)))
 487
 488     def axi_reg_def(self, *args):
 489         ret = []
 490         start = 0x00011100  # start of AXI peripherals address
 491         for (name, count) in self.ifacecount:
 492             for i in range(count):
 493                 x = self.data[name].axi_reg_def(start, i)
 494                 #print ("ifc", name, x)
 495                 (rdef, offs) = x
 496                 ret.append(rdef)
 497                 start += offs
 498         return '\n'.join(list(filter(None, ret)))
 499
 500     def axi_slave_idx(self, *args):
 501         ret = []
 502         start = 0
 503         for (name, count) in self.ifacecount:
 504             for i in range(count):
 505                 (rdef, offs) = self.data[name].axi_slave_idx(start, i)
 506                 #print ("ifc", name, rdef, offs)
 507                 ret.append(rdef)
 508                 start += offs
 509         ret.append("typedef %d LastGen_slave_num;" % (start - 1))
 510         decls = '\n'.join(list(filter(None, ret)))
 511         return axi_slave_declarations.format(decls)
 512
 513     def axi_addr_map(self, *args):
 514         ret = []
 515         for (name, count) in self.ifacecount:
 516             for i in range(count):
 517                 ret.append(self.data[name].axi_addr_map(i))
 518         return '\n'.join(list(filter(None, ret)))
 519
 520     def mkslow_peripheral(self, *args):
 521         ret = []
 522         for (name, count) in self.ifacecount:
 523             for i in range(count):
 524                 print "mkslow", name, count
 525                 x = self.data[name].mkslow_peripheral()
 526                 print name, count, x
 527                 suffix = self.data[name].mksuffix(name, i)
 528                 ret.append(x.format(suffix))
 529         return '\n'.join(list(filter(None, ret)))
 530
 531     def mk_connection(self, *args):
 532         ret = []
 533         for (name, count) in self.ifacecount:
 534             for i in range(count):
 535                 print "mk_conn", name, i
 536                 txt = self.data[name].mk_connection(i)
 537                 if name == 'gpioa':
 538                     print "txt", txt
 539                     print self.data[name].mk_connection
 540                 ret.append(txt)
 541         return '\n'.join(list(filter(None, ret)))
 542
 543     def mk_cellconn(self):
 544         ret = []
 545         cellcount = 0
 546         for (name, count) in self.ifacecount:
 547             for i in range(count):
 548                 res = self.data[name].mk_cellconn(cellcount, name, i)
 549                 if not res:
 550                     continue
 551                 (txt, cellcount) = res
 552                 ret.append(txt)
 553         ret = '\n'.join(list(filter(None, ret)))
 554         return pinmux_cellrule.format(ret)
 555
 556     def mk_pincon(self):
 557         ret = []
 558         for (name, count) in self.ifacecount:
 559             for i in range(count):
 560                 txt = self.data[name].mk_pincon(name, i)
 561                 ret.append(txt)
 562         return '\n'.join(list(filter(None, ret)))
 563
 564
 565 class PFactory(object):
 566     def getcls(self, name):
 567         for k, v in {'uart': uart,
 568                      'rs232': rs232,
 569                      'twi': twi,
 570                      'qspi': qspi,
 571                      'pwm': pwm,
 572                      'gpio': gpio
 573                      }.items():
 574             if name.startswith(k):
 575                 return v
 576         return None
 577
 578
 579 slowfactory = PFactory()
 580
 581 if __name__ == '__main__':
 582     p = uart('uart')
 583     print p.slowimport()
 584     print p.slowifdecl()
 585     i = PeripheralIface('uart')
 586     print i, i.slow
 587     i = PeripheralIface('gpioa')
 588     print i, i.slow