src/bsv/peripheral_gen.py

   1 import types
   2 from copy import deepcopy
   3
   4
   5 class PBase(object):
   6     def __init__(self, name):
   7         self.name = name
   8
   9     def slowifdeclmux(self):
  10         return ''
  11
  12     def slowimport(self):
  13         return ''
  14
  15     def num_axi_regs32(self):
  16         return 0
  17
  18     def slowifdecl(self):
  19         return ''
  20
  21     def axibase(self, name, ifacenum):
  22         name = name.upper()
  23         return "%(name)s%(ifacenum)dBase" % locals()
  24
  25     def axiend(self, name, ifacenum):
  26         name = name.upper()
  27         return "%(name)s%(ifacenum)dEnd" % locals()
  28
  29     def axi_reg_def(self, start, name, ifacenum):
  30         name = name.upper()
  31         offs = self.num_axi_regs32() * 4 * 16
  32         if offs == 0:
  33             return ('', 0)
  34         end = start + offs - 1
  35         bname = self.axibase(name, ifacenum)
  36         bend = self.axiend(name, ifacenum)
  37         comment = "%d 32-bit regs" % self.num_axi_regs32()
  38         return ("    `define %(bname)s 'h%(start)08X\n"
  39                 "    `define %(bend)s  'h%(end)08X // %(comment)s" % locals(),
  40                 offs)
  41
  42     def axi_slave_name(self, name, ifacenum):
  43         name = name.upper()
  44         return "{0}{1}_slave_num".format(name, ifacenum)
  45
  46     def axi_slave_idx(self, idx, name, ifacenum):
  47         name = self.axi_slave_name(name, ifacenum)
  48         return ("typedef {0} {1};".format(idx, name), 1)
  49
  50     def axi_addr_map(self, name, ifacenum):
  51         bname = self.axibase(name, ifacenum)
  52         bend = self.axiend(name, ifacenum)
  53         name = self.axi_slave_name(name, ifacenum)
  54         return """\
  55         if(addr>=`{0} && addr<=`{1})
  56             return tuple2(True,fromInteger(valueOf({2})));
  57         else""".format(bname, bend, name)
  58
  59     def mk_pincon(self, name, count):
  60         # TODO: really should be using bsv.interface_decl.Interfaces
  61         # pin-naming rules.... logic here is hard-coded to duplicate
  62         # it (see Interface.__init__ outen)
  63         ret = []
  64         for p in self.peripheral.pinspecs:
  65             typ = p['type']
  66             pname = p['name']
  67             #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
  68             n = name  # "{0}{1}".format(self.name, self.mksuffix(name, count))
  69             ret.append("    //%s %s" % (n, str(p)))
  70             sname = self.peripheral.pname(pname).format(count)
  71             ps = "pinmux.peripheral_side.%s" % sname
  72             if typ == 'out' or typ == 'inout':
  73                 ret.append("    rule con_%s%d_%s_out;" % (name, count, pname))
  74                 fname = self.pinname_out(pname)
  75                 if not n.startswith('gpio'): # XXX EURGH! horrible hack
  76                   n_ = "{0}{1}".format(n, count)
  77                 else:
  78                   n_ = n
  79                 if fname:
  80                     if p.get('outen'):
  81                         ps_ = ps + '_out'
  82                     else:
  83                         ps_ = ps
  84                     ret.append("      {0}({1}.{2});".format(ps_, n_, fname))
  85                 fname = None
  86                 if p.get('outen'):
  87                     fname = self.pinname_outen(pname)
  88                 if fname:
  89                     if isinstance(fname, str):
  90                         fname = "{0}.{1}".format(n_, fname)
  91                     fname = self.pinname_tweak(pname, 'outen', fname)
  92                     ret.append("      {0}_outen({1});".format(ps, fname))
  93                 ret.append("    endrule")
  94             if typ == 'in' or typ == 'inout':
  95                 fname = self.pinname_in(pname)
  96                 if fname:
  97                     if p.get('outen'):
  98                         ps_ = ps + '_in'
  99                     else:
 100                         ps_ = ps
 101                     ret.append(
 102                         "    rule con_%s%d_%s_in;" %
 103                         (name, count, pname))
 104                     n_ = "{0}{1}".format(n, count)
 105                     n_ = '{0}.{1}'.format(n_, fname)
 106                     n_ = self.ifname_tweak(pname, 'in', n_)
 107                     ret.append("      {1}({0});".format(ps_, n_))
 108                     ret.append("    endrule")
 109         return '\n'.join(ret)
 110
 111     def mk_cellconn(self, *args):
 112         return ''
 113
 114     def mkslow_peripheral(self, size=0):
 115         return ''
 116
 117     def mksuffix(self, name, i):
 118         return i
 119
 120     def __mk_connection(self, con, aname):
 121         txt = "        mkConnection (slow_fabric.v_to_slaves\n" + \
 122             "                    [fromInteger(valueOf({1}))],\n" + \
 123             "                    {0});"
 124
 125         print "PBase __mk_connection", self.name, aname
 126         if not con:
 127             return ''
 128         return txt.format(con, aname)
 129
 130     def mk_connection(self, count, name=None):
 131         if name is None:
 132             name = self.name
 133         print "PBase mk_conn", self.name, count
 134         aname = self.axi_slave_name(name, count)
 135         #dname = self.mksuffix(name, count)
 136         #dname = "{0}{1}".format(name, dname)
 137         con = self._mk_connection(name, count).format(count, aname)
 138         return self.__mk_connection(con, aname)
 139
 140     def _mk_connection(self, name=None, count=0):
 141         return ''
 142
 143     def pinname_out(self, pname):
 144         return ''
 145
 146     def pinname_in(self, pname):
 147         return ''
 148
 149     def pinname_outen(self, pname):
 150         return ''
 151
 152     def ifname_tweak(self, pname, typ, txt):
 153         return txt
 154
 155     def pinname_tweak(self, pname, typ, txt):
 156         return txt
 157
 158
 159 class uart(PBase):
 160
 161     def slowimport(self):
 162         return "          import Uart_bs         :: *;\n" + \
 163                "          import RS232_modified::*;"
 164
 165     def slowifdecl(self):
 166         return "            interface RS232 uart{0}_coe;\n" + \
 167                "            method Bit#(1) uart{0}_intr;"
 168
 169     def num_axi_regs32(self):
 170         return 8
 171
 172     def mkslow_peripheral(self, size=0):
 173         return "        Ifc_Uart_bs uart{0} <- \n" + \
 174                "                mkUart_bs(clocked_by sp_clock,\n" + \
 175                "                    reset_by uart_reset, sp_clock, sp_reset);"
 176
 177     def _mk_connection(self, name=None, count=0):
 178         return "uart{0}.slave_axi_uart"
 179
 180     def pinname_out(self, pname):
 181         return {'tx': 'coe_rs232.sout'}.get(pname, '')
 182
 183     def pinname_in(self, pname):
 184         return {'rx': 'coe_rs232.sin'}.get(pname, '')
 185
 186
 187 class qquart(PBase):
 188
 189     def slowimport(self):
 190         return "          import Uart16550         :: *;"
 191
 192     def slowifdecl(self):
 193         return "            interface RS232_PHY_Ifc uart{0}_coe;\n" + \
 194                "            method Bit#(1) uart{0}_intr;"
 195
 196     def num_axi_regs32(self):
 197         return 8
 198
 199     def mkslow_peripheral(self, size=0):
 200         return "        Uart16550_AXI4_Lite_Ifc uart{0} <- \n" + \
 201                "                mkUart16550(clocked_by sp_clock,\n" + \
 202                "                    reset_by uart_reset, sp_clock, sp_reset);"
 203
 204     def _mk_connection(self, name=None, count=0):
 205         return "uart{0}.slave_axi_uart"
 206
 207     def pinname_out(self, pname):
 208         return {'tx': 'coe_rs232.sout'}.get(pname, '')
 209
 210     def pinname_in(self, pname):
 211         return {'rx': 'coe_rs232.sin'}.get(pname, '')
 212
 213
 214 class rs232(PBase):
 215
 216     def slowimport(self):
 217         return "        import Uart_bs::*;\n" + \
 218                "        import RS232_modified::*;"
 219
 220     def slowifdecl(self):
 221         return "            interface RS232 uart{0}_coe;"
 222
 223     def num_axi_regs32(self):
 224         return 2
 225
 226     def mkslow_peripheral(self, size=0):
 227         return "        //Ifc_Uart_bs uart{0} <-" + \
 228                "        //       mkUart_bs(clocked_by uart_clock,\n" + \
 229                "        //          reset_by uart_reset,sp_clock, sp_reset);" +\
 230                "        Ifc_Uart_bs uart{0} <-" + \
 231                "                mkUart_bs(clocked_by sp_clock,\n" + \
 232                "                    reset_by sp_reset, sp_clock, sp_reset);"
 233
 234     def _mk_connection(self, name=None, count=0):
 235         return "uart{0}.slave_axi_uart"
 236
 237     def pinname_out(self, pname):
 238         return {'tx': 'coe_rs232.sout'}.get(pname, '')
 239
 240     def pinname_in(self, pname):
 241         return {'rx': 'coe_rs232.sin'}.get(pname, '')
 242
 243
 244 class twi(PBase):
 245
 246     def slowimport(self):
 247         return "        import I2C_top           :: *;"
 248
 249     def slowifdecl(self):
 250         return "            interface I2C_out twi{0}_out;\n" + \
 251                "            method Bit#(1) twi{0}_isint;"
 252
 253     def num_axi_regs32(self):
 254         return 8
 255
 256     def mkslow_peripheral(self, size=0):
 257         return "        I2C_IFC twi{0} <- mkI2CController();"
 258
 259     def _mk_connection(self, name=None, count=0):
 260         return "twi{0}.slave_i2c_axi"
 261
 262     def pinname_out(self, pname):
 263         return {'sda': 'out.sda_out',
 264                 'scl': 'out.scl_out'}.get(pname, '')
 265
 266     def pinname_in(self, pname):
 267         return {'sda': 'out.sda_in',
 268                 'scl': 'out.scl_in'}.get(pname, '')
 269
 270     def pinname_outen(self, pname):
 271         return {'sda': 'out.sda_out_en',
 272                 'scl': 'out.scl_out_en'}.get(pname, '')
 273
 274     def pinname_tweak(self, pname, typ, txt):
 275         if typ == 'outen':
 276             return "pack({0})".format(txt)
 277         return txt
 278
 279
 280 class eint(PBase):
 281
 282     def slowimport(self):
 283         size = len(self.peripheral.pinspecs)
 284         return "    `define NUM_EINTS %d" % size
 285
 286     def slowifdeclmux(self):
 287         size = len(self.peripheral.pinspecs)
 288         return "    method Action external_int(Bit#(%d) in);" % size
 289
 290     def mkslow_peripheral(self, size=0):
 291         size = len(self.peripheral.pinspecs)
 292         return "        Wire#(Bit#(%d)) wr_interrupt <- mkWire();" % size
 293
 294
 295     def axi_slave_name(self, name, ifacenum):
 296         return ''
 297
 298     def axi_slave_idx(self, idx, name, ifacenum):
 299         return ('', 0)
 300
 301     def axi_addr_map(self, name, ifacenum):
 302         return ''
 303
 304     def ifname_tweak(self, pname, typ, txt):
 305         if typ != 'in':
 306             return txt
 307         print "ifnameweak", pname, typ, txt
 308         return "wr_interrupt[{0}] <= ".format(pname)
 309
 310     def mk_pincon(self, name, count):
 311         ret = [PBase.mk_pincon(self, name, count)]
 312         size = len(self.peripheral.pinspecs)
 313         ret.append(eint_pincon_template.format(size))
 314         ret.append("    rule con_%s%d_io_in;" % (name,  count))
 315         ret.append("    wr_interrupt({")
 316         for idx,  p in enumerate(self.peripheral.pinspecs):
 317             pname = p['name']
 318             sname = self.peripheral.pname(pname).format(count)
 319             ps = "pinmux.peripheral_side.%s" % sname
 320             comma = '' if idx == size-1 else ','
 321             ret.append("             {0}{1}".format(ps,  comma))
 322         ret.append("        });")
 323         ret.append("    endrule")
 324
 325         return '\n'.join(ret)
 326
 327
 328 eint_pincon_template = '''\
 329     // TODO: offset i by the number of eints already used
 330     for(Integer i=0;i<{0};i=i+ 1)begin
 331       rule connect_int_to_plic(wr_interrupt[i]==1);
 332                 ff_gateway_queue[i].enq(1);
 333                 plic.ifc_external_irq[i].irq_frm_gateway(True);
 334       endrule
 335     end
 336 '''
 337
 338
 339 class spi(PBase):
 340
 341     def slowimport(self):
 342         return "        import qspi              :: *;"
 343
 344     def slowifdecl(self):
 345         return "            interface QSPI_out spi{0}_out;\n" + \
 346                "            method Bit#(1) spi{0}_isint;"
 347
 348     def num_axi_regs32(self):
 349         return 13
 350
 351     def mkslow_peripheral(self):
 352         return "        Ifc_qspi spi{0} <-  mkqspi();"
 353
 354     def _mk_connection(self, name=None, count=0):
 355         return "spi{0}.slave"
 356
 357     def pinname_out(self, pname):
 358         return {'clk': 'out.clk_o',
 359                 'nss': 'out.ncs_o',
 360                 'mosi': 'out.io_o[0]',
 361                 'miso': 'out.io_o[1]',
 362                 }.get(pname, '')
 363
 364     def pinname_outen(self, pname):
 365         return {'clk': 1,
 366                 'nss': 1,
 367                 'mosi': 'out.io_enable[0]',
 368                 'miso': 'out.io_enable[1]',
 369                 }.get(pname, '')
 370
 371     def mk_pincon(self, name, count):
 372         ret = [PBase.mk_pincon(self, name, count)]
 373         # special-case for gpio in, store in a temporary vector
 374         plen = len(self.peripheral.pinspecs)
 375         ret.append("    // XXX NSS and CLK are hard-coded master")
 376         ret.append("    // TODO: must add spi slave-mode")
 377         ret.append("    // all ins done in one rule from 4-bitfield")
 378         ret.append("    rule con_%s%d_io_in;" % (name, count))
 379         ret.append("       {0}{1}.out.io_i({{".format(name, count))
 380         for idx, pname in enumerate(['mosi', 'miso']):
 381             sname = self.peripheral.pname(pname).format(count)
 382             ps = "pinmux.peripheral_side.%s_in" % sname
 383             ret.append("            {0},".format(ps))
 384         ret.append("            1'b0,1'b0")
 385         ret.append("        });")
 386         ret.append("    endrule")
 387         return '\n'.join(ret)
 388
 389
 390 class qspi(PBase):
 391
 392     def slowimport(self):
 393         return "        import qspi              :: *;"
 394
 395     def slowifdecl(self):
 396         return "            interface QSPI_out qspi{0}_out;\n" + \
 397                "            method Bit#(1) qspi{0}_isint;"
 398
 399     def num_axi_regs32(self):
 400         return 13
 401
 402     def mkslow_peripheral(self, size=0):
 403         return "        Ifc_qspi qspi{0} <-  mkqspi();"
 404
 405     def _mk_connection(self, name=None, count=0):
 406         return "qspi{0}.slave"
 407
 408     def pinname_out(self, pname):
 409         return {'ck': 'out.clk_o',
 410                 'nss': 'out.ncs_o',
 411                 'io0': 'out.io_o[0]',
 412                 'io1': 'out.io_o[1]',
 413                 'io2': 'out.io_o[2]',
 414                 'io3': 'out.io_o[3]',
 415                 }.get(pname, '')
 416
 417     def pinname_outen(self, pname):
 418         return {'ck': 1,
 419                 'nss': 1,
 420                 'io0': 'out.io_enable[0]',
 421                 'io1': 'out.io_enable[1]',
 422                 'io2': 'out.io_enable[2]',
 423                 'io3': 'out.io_enable[3]',
 424                 }.get(pname, '')
 425
 426     def mk_pincon(self, name, count):
 427         ret = [PBase.mk_pincon(self, name, count)]
 428         # special-case for gpio in, store in a temporary vector
 429         plen = len(self.peripheral.pinspecs)
 430         ret.append("    // XXX NSS and CLK are hard-coded master")
 431         ret.append("    // TODO: must add qspi slave-mode")
 432         ret.append("    // all ins done in one rule from 4-bitfield")
 433         ret.append("    rule con_%s%d_io_in;" % (name, count))
 434         ret.append("       {0}{1}.out.io_i({{".format(name, count))
 435         for i, p in enumerate(self.peripheral.pinspecs):
 436             typ = p['type']
 437             pname = p['name']
 438             if not pname.startswith('io'):
 439                 continue
 440             idx = pname[1:]
 441             n = name
 442             sname = self.peripheral.pname(pname).format(count)
 443             ps = "pinmux.peripheral_side.%s_in" % sname
 444             comma = '' if i == 5 else ','
 445             ret.append("            {0}{1}".format(ps, comma))
 446         ret.append("        });")
 447         ret.append("    endrule")
 448         return '\n'.join(ret)
 449
 450
 451 class pwm(PBase):
 452
 453     def slowimport(self):
 454         return "        import pwm::*;"
 455
 456     def slowifdecl(self):
 457         return "        interface PWMIO pwm{0}_io;"
 458
 459     def num_axi_regs32(self):
 460         return 4
 461
 462     def mkslow_peripheral(self, size=0):
 463         return "        Ifc_PWM_bus pwm{0} <- mkPWM_bus(sp_clock);"
 464
 465     def _mk_connection(self, name=None, count=0):
 466         return "pwm{0}.axi4_slave"
 467
 468     def pinname_out(self, pname):
 469         return {'out': 'pwm_io.pwm_o'}.get(pname, '')
 470
 471
 472 class gpio(PBase):
 473
 474     def slowimport(self):
 475         return "     import pinmux::*;\n" + \
 476                "     import mux::*;\n" + \
 477                "     import gpio::*;\n"
 478
 479     def slowifdeclmux(self):
 480         size = len(self.peripheral.pinspecs)
 481         return "    interface GPIO_config#(%d) pad_config{0};" % size
 482
 483     def num_axi_regs32(self):
 484         return 2
 485
 486     def axi_slave_idx(self, idx, name, ifacenum):
 487         """ generates AXI slave number definition, except
 488             GPIO also has a muxer per bank
 489         """
 490         name = name.upper()
 491         mname = 'mux' + name[4:]
 492         mname = mname.upper()
 493         print "AXIslavenum", name,  mname
 494         (ret, x) = PBase.axi_slave_idx(self, idx, name, ifacenum)
 495         (ret2, x) = PBase.axi_slave_idx(self, idx+1, mname, ifacenum)
 496         return ("%s\n%s" % (ret, ret2), 2)
 497
 498     def mkslow_peripheral(self, size=0):
 499         print "gpioslow", self.peripheral,  dir(self.peripheral)
 500         size = len(self.peripheral.pinspecs)
 501         return "        MUX#(%d) mux{0} <- mkmux();\n" % size + \
 502                "        GPIO#(%d) gpio{0} <- mkgpio();" % size
 503
 504     def mk_connection(self, count):
 505         print "GPIO mk_conn", self.name, count
 506         res = []
 507         dname = self.mksuffix(self.name, count)
 508         for i, n in enumerate(['gpio' + dname, 'mux' + dname]):
 509             res.append(PBase.mk_connection(self, count, n))
 510         return '\n'.join(res)
 511
 512     def _mk_connection(self, name=None, count=0):
 513         n = self.mksuffix(name, count)
 514         if name.startswith('gpio'):
 515             return "gpio{0}.axi_slave".format(n)
 516         if name.startswith('mux'):
 517             return "mux{0}.axi_slave".format(n)
 518
 519     def mksuffix(self, name, i):
 520         if name.startswith('mux'):
 521             return name[3:]
 522         return name[4:]
 523
 524     def mk_cellconn(self, cellnum, name, count):
 525         ret = []
 526         bank = self.mksuffix(name, count)
 527         txt = "       pinmux.mux_lines.cell{0}_mux(mux{1}.mux_config.mux[{2}]);"
 528         for p in self.peripheral.pinspecs:
 529             ret.append(txt.format(cellnum, bank, p['name'][1:]))
 530             cellnum += 1
 531         return ("\n".join(ret), cellnum)
 532
 533     def pinname_out(self, pname):
 534         return "func.gpio_out[{0}]".format(pname[1:])
 535
 536     def pinname_outen(self, pname):
 537         return "func.gpio_out_en[{0}]".format(pname[1:])
 538
 539     def mk_pincon(self, name, count):
 540         ret = [PBase.mk_pincon(self, name, count)]
 541         # special-case for gpio in, store in a temporary vector
 542         plen = len(self.peripheral.pinspecs)
 543         ret.append("    rule con_%s%d_in;" % (name, count))
 544         ret.append("       Vector#({0},Bit#(1)) temp;".format(plen))
 545         for p in self.peripheral.pinspecs:
 546             typ = p['type']
 547             pname = p['name']
 548             idx = pname[1:]
 549             n = name
 550             sname = self.peripheral.pname(pname).format(count)
 551             ps = "pinmux.peripheral_side.%s_in" % sname
 552             ret.append("        temp[{0}]={1};".format(idx, ps))
 553         ret.append("        {0}.func.gpio_in(temp);".format(name))
 554         ret.append("    endrule")
 555         return '\n'.join(ret)
 556
 557
 558 axi_slave_declarations = """\
 559 typedef  0  SlowMaster;
 560 {0}
 561 typedef  TAdd#(LastGen_slave_num,`ifdef CLINT       1 `else 0 `endif )
 562               CLINT_slave_num;
 563 typedef  TAdd#(CLINT_slave_num  ,`ifdef PLIC        1 `else 0 `endif )
 564               Plic_slave_num;
 565 typedef  TAdd#(Plic_slave_num   ,`ifdef AXIEXP      1 `else 0 `endif )
 566               AxiExp1_slave_num;
 567 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
 568 """
 569
 570 pinmux_cellrule = """\
 571     rule connect_select_lines_pinmux;
 572 {0}
 573     endrule
 574 """
 575
 576
 577 class CallFn(object):
 578     def __init__(self, peripheral, name):
 579         self.peripheral = peripheral
 580         self.name = name
 581
 582     def __call__(self, *args):
 583         #print "__call__", self.name, self.peripheral.slow, args
 584         if not self.peripheral.slow:
 585             return ''
 586         return getattr(self.peripheral.slow, self.name)(*args[1:])
 587
 588
 589 class PeripheralIface(object):
 590     def __init__(self, ifacename):
 591         self.slow = None
 592         slow = slowfactory.getcls(ifacename)
 593         print "Iface", ifacename, slow
 594         if slow:
 595             self.slow = slow(ifacename)
 596             self.slow.peripheral = self
 597         for fname in ['slowimport', 'slowifdecl', 'slowifdeclmux',
 598                       'mkslow_peripheral',
 599                       'mk_connection', 'mk_cellconn', 'mk_pincon']:
 600             fn = CallFn(self, fname)
 601             setattr(self, fname, types.MethodType(fn, self))
 602
 603         #print "PeripheralIface"
 604         #print dir(self)
 605
 606     def mksuffix(self, name, i):
 607         if self.slow is None:
 608             return i
 609         return self.slow.mksuffix(name, i)
 610
 611     def axi_reg_def(self, start, count):
 612         if not self.slow:
 613             return ('', 0)
 614         return self.slow.axi_reg_def(start, self.ifacename, count)
 615
 616     def axi_slave_idx(self, start, count):
 617         if not self.slow:
 618             return ('', 0)
 619         return self.slow.axi_slave_idx(start, self.ifacename, count)
 620
 621     def axi_addr_map(self, count):
 622         if not self.slow:
 623             return ''
 624         return self.slow.axi_addr_map(self.ifacename, count)
 625
 626
 627 class PeripheralInterfaces(object):
 628     def __init__(self):
 629         pass
 630
 631     def slowimport(self, *args):
 632         ret = []
 633         for (name, count) in self.ifacecount:
 634             #print "slowimport", name, self.data[name].slowimport
 635             ret.append(self.data[name].slowimport())
 636         return '\n'.join(list(filter(None, ret)))
 637
 638     def slowifdeclmux(self, *args):
 639         ret = []
 640         for (name, count) in self.ifacecount:
 641             for i in range(count):
 642                 ret.append(self.data[name].slowifdeclmux().format(i, name))
 643         return '\n'.join(list(filter(None, ret)))
 644
 645     def slowifdecl(self, *args):
 646         ret = []
 647         for (name, count) in self.ifacecount:
 648             for i in range(count):
 649                 ret.append(self.data[name].slowifdecl().format(i, name))
 650         return '\n'.join(list(filter(None, ret)))
 651
 652     def axi_reg_def(self, *args):
 653         ret = []
 654         start = 0x00011100  # start of AXI peripherals address
 655         for (name, count) in self.ifacecount:
 656             for i in range(count):
 657                 x = self.data[name].axi_reg_def(start, i)
 658                 #print ("ifc", name, x)
 659                 (rdef, offs) = x
 660                 ret.append(rdef)
 661                 start += offs
 662         return '\n'.join(list(filter(None, ret)))
 663
 664     def axi_slave_idx(self, *args):
 665         ret = []
 666         start = 0
 667         for (name, count) in self.ifacecount:
 668             for i in range(count):
 669                 (rdef, offs) = self.data[name].axi_slave_idx(start, i)
 670                 #print ("ifc", name, rdef, offs)
 671                 ret.append(rdef)
 672                 start += offs
 673         ret.append("typedef %d LastGen_slave_num;" % (start - 1))
 674         decls = '\n'.join(list(filter(None, ret)))
 675         return axi_slave_declarations.format(decls)
 676
 677     def axi_addr_map(self, *args):
 678         ret = []
 679         for (name, count) in self.ifacecount:
 680             for i in range(count):
 681                 ret.append(self.data[name].axi_addr_map(i))
 682         return '\n'.join(list(filter(None, ret)))
 683
 684     def mkslow_peripheral(self, *args):
 685         ret = []
 686         for (name, count) in self.ifacecount:
 687             for i in range(count):
 688                 print "mkslow", name, count
 689                 x = self.data[name].mkslow_peripheral()
 690                 print name, count, x
 691                 suffix = self.data[name].mksuffix(name, i)
 692                 ret.append(x.format(suffix))
 693         return '\n'.join(list(filter(None, ret)))
 694
 695     def mk_connection(self, *args):
 696         ret = []
 697         for (name, count) in self.ifacecount:
 698             for i in range(count):
 699                 print "mk_conn", name, i
 700                 txt = self.data[name].mk_connection(i)
 701                 if name == 'gpioa':
 702                     print "txt", txt
 703                     print self.data[name].mk_connection
 704                 ret.append(txt)
 705         return '\n'.join(list(filter(None, ret)))
 706
 707     def mk_cellconn(self):
 708         ret = []
 709         cellcount = 0
 710         for (name, count) in self.ifacecount:
 711             for i in range(count):
 712                 res = self.data[name].mk_cellconn(cellcount, name, i)
 713                 if not res:
 714                     continue
 715                 (txt, cellcount) = res
 716                 ret.append(txt)
 717         ret = '\n'.join(list(filter(None, ret)))
 718         return pinmux_cellrule.format(ret)
 719
 720     def mk_pincon(self):
 721         ret = []
 722         for (name, count) in self.ifacecount:
 723             for i in range(count):
 724                 txt = self.data[name].mk_pincon(name, i)
 725                 ret.append(txt)
 726         return '\n'.join(list(filter(None, ret)))
 727
 728
 729 class PFactory(object):
 730     def getcls(self, name):
 731         for k, v in {'uart': uart,
 732                      'rs232': rs232,
 733                      'twi': twi,
 734                      'qspi': qspi,
 735                      'spi': spi,
 736                      'pwm': pwm,
 737                      'eint': eint,
 738                      'gpio': gpio
 739                      }.items():
 740             if name.startswith(k):
 741                 return v
 742         return None
 743
 744
 745 slowfactory = PFactory()
 746
 747 if __name__ == '__main__':
 748     p = uart('uart')
 749     print p.slowimport()
 750     print p.slowifdecl()
 751     i = PeripheralIface('uart')
 752     print i, i.slow
 753     i = PeripheralIface('gpioa')
 754     print i, i.slow