src/bsv/peripheral_gen.py

   1 import types
   2 from copy import deepcopy
   3
   4
   5 class PBase(object):
   6     def __init__(self, name):
   7         self.name = name
   8
   9     def slowifdeclmux(self):
  10         return ''
  11
  12     def slowimport(self):
  13         return ''
  14
  15     def num_axi_regs32(self):
  16         return 0
  17
  18     def slowifdecl(self):
  19         return ''
  20
  21     def axibase(self, name, ifacenum):
  22         name = name.upper()
  23         return "%(name)s%(ifacenum)dBase" % locals()
  24
  25     def axiend(self, name, ifacenum):
  26         name = name.upper()
  27         return "%(name)s%(ifacenum)dEnd" % locals()
  28
  29     def axi_reg_def(self, start, name, ifacenum):
  30         name = name.upper()
  31         offs = self.num_axi_regs32() * 4 * 16
  32         if offs == 0:
  33             return ('', 0)
  34         end = start + offs - 1
  35         bname = self.axibase(name, ifacenum)
  36         bend = self.axiend(name, ifacenum)
  37         comment = "%d 32-bit regs" % self.num_axi_regs32()
  38         return ("    `define %(bname)s 'h%(start)08X\n"
  39                 "    `define %(bend)s  'h%(end)08X // %(comment)s" % locals(),
  40                 offs)
  41
  42     def axi_slave_name(self, name, ifacenum):
  43         name = name.upper()
  44         return "{0}{1}_slave_num".format(name, ifacenum)
  45
  46     def axi_slave_idx(self, idx, name, ifacenum):
  47         name = self.axi_slave_name(name, ifacenum)
  48         return ("typedef {0} {1};".format(idx, name), 1)
  49
  50     def axi_addr_map(self, name, ifacenum):
  51         bname = self.axibase(name, ifacenum)
  52         bend = self.axiend(name, ifacenum)
  53         name = self.axi_slave_name(name, ifacenum)
  54         return """\
  55         if(addr>=`{0} && addr<=`{1})
  56             return tuple2(True,fromInteger(valueOf({2})));
  57         else""".format(bname, bend, name)
  58
  59     def mk_pincon(self, name, count):
  60         # TODO: really should be using bsv.interface_decl.Interfaces
  61         # pin-naming rules.... logic here is hard-coded to duplicate
  62         # it (see Interface.__init__ outen)
  63         ret = []
  64         for p in self.peripheral.pinspecs:
  65             typ = p['type']
  66             pname = p['name']
  67             #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
  68             n = name  # "{0}{1}".format(self.name, self.mksuffix(name, count))
  69             ret.append("    //%s %s" % (n, str(p)))
  70             sname = self.peripheral.pname(pname).format(count)
  71             ps = "pinmux.peripheral_side.%s" % sname
  72             if typ == 'out' or typ == 'inout':
  73                 ret.append("    rule con_%s%d_%s_out;" % (name, count, pname))
  74                 fname = self.pinname_out(pname)
  75                 if not n.startswith('gpio'): # XXX EURGH! horrible hack
  76                   n_ = "{0}{1}".format(n, count)
  77                 else:
  78                   n_ = n
  79                 if fname:
  80                     if p.get('outen'):
  81                         ps_ = ps + '_out'
  82                     else:
  83                         ps_ = ps
  84                     ret.append("      {0}({1}.{2});".format(ps_, n_, fname))
  85                 fname = None
  86                 if p.get('outen'):
  87                     fname = self.pinname_outen(pname)
  88                 if fname:
  89                     if isinstance(fname, str):
  90                         fname = "{0}.{1}".format(n_, fname)
  91                     fname = self.pinname_tweak(pname, 'outen', fname)
  92                     ret.append("      {0}_outen({1});".format(ps, fname))
  93                 ret.append("    endrule")
  94             if typ == 'in' or typ == 'inout':
  95                 fname = self.pinname_in(pname)
  96                 if fname:
  97                     if p.get('outen'):
  98                         ps_ = ps + '_in'
  99                     else:
 100                         ps_ = ps
 101                     ret.append(
 102                         "    rule con_%s%d_%s_in;" %
 103                         (name, count, pname))
 104                     n_ = "{0}{1}".format(n, count)
 105                     ret.append("      {1}.{2}({0});".format(ps_, n_, fname))
 106                     ret.append("    endrule")
 107         return '\n'.join(ret)
 108
 109     def mk_cellconn(self, *args):
 110         return ''
 111
 112     def mkslow_peripheral(self, size=0):
 113         return ''
 114
 115     def mksuffix(self, name, i):
 116         return i
 117
 118     def __mk_connection(self, con, aname):
 119         txt = "        mkConnection (slow_fabric.v_to_slaves\n" + \
 120             "                    [fromInteger(valueOf({1}))],\n" + \
 121             "                    {0});"
 122
 123         print "PBase __mk_connection", self.name, aname
 124         if not con:
 125             return ''
 126         return txt.format(con, aname)
 127
 128     def mk_connection(self, count, name=None):
 129         if name is None:
 130             name = self.name
 131         print "PBase mk_conn", self.name, count
 132         aname = self.axi_slave_name(name, count)
 133         #dname = self.mksuffix(name, count)
 134         #dname = "{0}{1}".format(name, dname)
 135         con = self._mk_connection(name, count).format(count, aname)
 136         return self.__mk_connection(con, aname)
 137
 138     def _mk_connection(self, name=None, count=0):
 139         return ''
 140
 141     def pinname_out(self, pname):
 142         return ''
 143
 144     def pinname_in(self, pname):
 145         return ''
 146
 147     def pinname_outen(self, pname):
 148         return ''
 149
 150     def pinname_tweak(self, pname, typ, txt):
 151         return txt
 152
 153
 154 class uart(PBase):
 155
 156     def slowimport(self):
 157         return "          import Uart_bs         :: *;\n" + \
 158                "          import RS232_modified::*;"
 159
 160     def slowifdecl(self):
 161         return "            interface RS232 uart{0}_coe;\n" + \
 162                "            method Bit#(1) uart{0}_intr;"
 163
 164     def num_axi_regs32(self):
 165         return 8
 166
 167     def mkslow_peripheral(self, size=0):
 168         return "        Ifc_Uart_bs uart{0} <- \n" + \
 169                "                mkUart_bs(clocked_by sp_clock,\n" + \
 170                "                    reset_by uart_reset, sp_clock, sp_reset);"
 171
 172     def _mk_connection(self, name=None, count=0):
 173         return "uart{0}.slave_axi_uart"
 174
 175     def pinname_out(self, pname):
 176         return {'tx': 'coe_rs232.sout'}.get(pname, '')
 177
 178     def pinname_in(self, pname):
 179         return {'rx': 'coe_rs232.sin'}.get(pname, '')
 180
 181
 182 class qquart(PBase):
 183
 184     def slowimport(self):
 185         return "          import Uart16550         :: *;"
 186
 187     def slowifdecl(self):
 188         return "            interface RS232_PHY_Ifc uart{0}_coe;\n" + \
 189                "            method Bit#(1) uart{0}_intr;"
 190
 191     def num_axi_regs32(self):
 192         return 8
 193
 194     def mkslow_peripheral(self, size=0):
 195         return "        Uart16550_AXI4_Lite_Ifc uart{0} <- \n" + \
 196                "                mkUart16550(clocked_by sp_clock,\n" + \
 197                "                    reset_by uart_reset, sp_clock, sp_reset);"
 198
 199     def _mk_connection(self, name=None, count=0):
 200         return "uart{0}.slave_axi_uart"
 201
 202     def pinname_out(self, pname):
 203         return {'tx': 'coe_rs232.sout'}.get(pname, '')
 204
 205     def pinname_in(self, pname):
 206         return {'rx': 'coe_rs232.sin'}.get(pname, '')
 207
 208
 209 class rs232(PBase):
 210
 211     def slowimport(self):
 212         return "        import Uart_bs::*;\n" + \
 213                "        import RS232_modified::*;"
 214
 215     def slowifdecl(self):
 216         return "            interface RS232 uart{0}_coe;"
 217
 218     def num_axi_regs32(self):
 219         return 2
 220
 221     def mkslow_peripheral(self, size=0):
 222         return "        //Ifc_Uart_bs uart{0} <-" + \
 223                "        //       mkUart_bs(clocked_by uart_clock,\n" + \
 224                "        //          reset_by uart_reset,sp_clock, sp_reset);" +\
 225                "        Ifc_Uart_bs uart{0} <-" + \
 226                "                mkUart_bs(clocked_by sp_clock,\n" + \
 227                "                    reset_by sp_reset, sp_clock, sp_reset);"
 228
 229     def _mk_connection(self, name=None, count=0):
 230         return "uart{0}.slave_axi_uart"
 231
 232     def pinname_out(self, pname):
 233         return {'tx': 'coe_rs232.sout'}.get(pname, '')
 234
 235     def pinname_in(self, pname):
 236         return {'rx': 'coe_rs232.sin'}.get(pname, '')
 237
 238
 239 class twi(PBase):
 240
 241     def slowimport(self):
 242         return "        import I2C_top           :: *;"
 243
 244     def slowifdecl(self):
 245         return "            interface I2C_out twi{0}_out;\n" + \
 246                "            method Bit#(1) twi{0}_isint;"
 247
 248     def num_axi_regs32(self):
 249         return 8
 250
 251     def mkslow_peripheral(self, size=0):
 252         return "        I2C_IFC twi{0} <- mkI2CController();"
 253
 254     def _mk_connection(self, name=None, count=0):
 255         return "twi{0}.slave_i2c_axi"
 256
 257     def pinname_out(self, pname):
 258         return {'sda': 'out.sda_out',
 259                 'scl': 'out.scl_out'}.get(pname, '')
 260
 261     def pinname_in(self, pname):
 262         return {'sda': 'out.sda_in',
 263                 'scl': 'out.scl_in'}.get(pname, '')
 264
 265     def pinname_outen(self, pname):
 266         return {'sda': 'out.sda_out_en',
 267                 'scl': 'out.scl_out_en'}.get(pname, '')
 268
 269     def pinname_tweak(self, pname, typ, txt):
 270         if typ == 'outen':
 271             return "pack({0})".format(txt)
 272         return txt
 273
 274
 275 class eint(PBase):
 276
 277     def mkslow_peripheral(self, size=0):
 278         size = len(self.peripheral.pinspecs)
 279         return "        Wire#(Bit#(%d)) wr_interrupt <- mkWire();" % size
 280
 281
 282     def axi_slave_name(self, name, ifacenum):
 283         return ''
 284
 285     def axi_slave_idx(self, idx, name, ifacenum):
 286         return ('', 0)
 287
 288     def axi_addr_map(self, name, ifacenum):
 289         return ''
 290
 291     def _pinname_out(self, pname):
 292         return {'sda': 'out.sda_out',
 293                 'scl': 'out.scl_out'}.get(pname, '')
 294
 295     def _pinname_in(self, pname):
 296         return {'sda': 'out.sda_in',
 297                 'scl': 'out.scl_in'}.get(pname, '')
 298
 299     def _pinname_outen(self, pname):
 300         return {'sda': 'out.sda_out_en',
 301                 'scl': 'out.scl_out_en'}.get(pname, '')
 302
 303     def mk_pincon(self, name, count):
 304         size = len(self.peripheral.pinspecs)
 305         ret = []
 306         ret.append(eint_pincon_template.format(size))
 307
 308         ret.append("    rule con_%s%d_io_out;" % (name, count))
 309         for idx, p in enumerate(self.peripheral.pinspecs):
 310             pname = p['name']
 311             sname = self.peripheral.pname(pname).format(count)
 312             ps = "pinmux.peripheral_side.%s_out" % sname
 313             ret.append("        wr_interript[{0}] <= {1};".format(idx, ps))
 314         for idx, p in enumerate(self.peripheral.pinspecs):
 315             pname = p['name']
 316             sname = self.peripheral.pname(pname).format(count)
 317             ps = "pinmux.peripheral_side.%s_out_en" % sname
 318             ret.append("        {0} <= 1'b1;".format(ps))
 319         ret.append("    endrule")
 320         return '\n'.join(ret)
 321
 322
 323 eint_pincon_template = '''\
 324     // TODO: offset i by the number of eints already used
 325     for(Integer i=0;i<{0};i=i+ 1)begin
 326       rule connect_int_to_plic(wr_interrupt[i]==1);
 327                 ff_gateway_queue[i].enq(1);
 328                 plic.ifc_external_irq[i].irq_frm_gateway(True);
 329       endrule
 330     end
 331 '''
 332
 333
 334 class spi(PBase):
 335
 336     def slowimport(self):
 337         return "        import qspi              :: *;"
 338
 339     def slowifdecl(self):
 340         return "            interface QSPI_out spi{0}_out;\n" + \
 341                "            method Bit#(1) spi{0}_isint;"
 342
 343     def num_axi_regs32(self):
 344         return 13
 345
 346     def mkslow_peripheral(self):
 347         return "        Ifc_qspi spi{0} <-  mkqspi();"
 348
 349     def _mk_connection(self, name=None, count=0):
 350         return "spi{0}.slave"
 351
 352     def pinname_out(self, pname):
 353         return {'clk': 'out.clk_o',
 354                 'nss': 'out.ncs_o',
 355                 'mosi': 'out.io_o[0]',
 356                 'miso': 'out.io_o[1]',
 357                 }.get(pname, '')
 358
 359     def pinname_outen(self, pname):
 360         return {'clk': 1,
 361                 'nss': 1,
 362                 'mosi': 'out.io_enable[0]',
 363                 'miso': 'out.io_enable[1]',
 364                 }.get(pname, '')
 365
 366     def mk_pincon(self, name, count):
 367         ret = [PBase.mk_pincon(self, name, count)]
 368         # special-case for gpio in, store in a temporary vector
 369         plen = len(self.peripheral.pinspecs)
 370         ret.append("    // XXX NSS and CLK are hard-coded master")
 371         ret.append("    // TODO: must add spi slave-mode")
 372         ret.append("    // all ins done in one rule from 4-bitfield")
 373         ret.append("    rule con_%s%d_io_in;" % (name, count))
 374         ret.append("       {0}{1}.out.io_i({{".format(name, count))
 375         for idx, pname in enumerate(['mosi', 'miso']):
 376             sname = self.peripheral.pname(pname).format(count)
 377             ps = "pinmux.peripheral_side.%s_in" % sname
 378             ret.append("            {0},".format(ps))
 379         ret.append("            1'b0,1'b0")
 380         ret.append("        });")
 381         ret.append("    endrule")
 382         return '\n'.join(ret)
 383
 384
 385 class qspi(PBase):
 386
 387     def slowimport(self):
 388         return "        import qspi              :: *;"
 389
 390     def slowifdecl(self):
 391         return "            interface QSPI_out qspi{0}_out;\n" + \
 392                "            method Bit#(1) qspi{0}_isint;"
 393
 394     def num_axi_regs32(self):
 395         return 13
 396
 397     def mkslow_peripheral(self, size=0):
 398         return "        Ifc_qspi qspi{0} <-  mkqspi();"
 399
 400     def _mk_connection(self, name=None, count=0):
 401         return "qspi{0}.slave"
 402
 403     def pinname_out(self, pname):
 404         return {'ck': 'out.clk_o',
 405                 'nss': 'out.ncs_o',
 406                 'io0': 'out.io_o[0]',
 407                 'io1': 'out.io_o[1]',
 408                 'io2': 'out.io_o[2]',
 409                 'io3': 'out.io_o[3]',
 410                 }.get(pname, '')
 411
 412     def pinname_outen(self, pname):
 413         return {'ck': 1,
 414                 'nss': 1,
 415                 'io0': 'out.io_enable[0]',
 416                 'io1': 'out.io_enable[1]',
 417                 'io2': 'out.io_enable[2]',
 418                 'io3': 'out.io_enable[3]',
 419                 }.get(pname, '')
 420
 421     def mk_pincon(self, name, count):
 422         ret = [PBase.mk_pincon(self, name, count)]
 423         # special-case for gpio in, store in a temporary vector
 424         plen = len(self.peripheral.pinspecs)
 425         ret.append("    // XXX NSS and CLK are hard-coded master")
 426         ret.append("    // TODO: must add qspi slave-mode")
 427         ret.append("    // all ins done in one rule from 4-bitfield")
 428         ret.append("    rule con_%s%d_io_in;" % (name, count))
 429         ret.append("       {0}{1}.out.io_i({{".format(name, count))
 430         for i, p in enumerate(self.peripheral.pinspecs):
 431             typ = p['type']
 432             pname = p['name']
 433             if not pname.startswith('io'):
 434                 continue
 435             idx = pname[1:]
 436             n = name
 437             sname = self.peripheral.pname(pname).format(count)
 438             ps = "pinmux.peripheral_side.%s_in" % sname
 439             comma = '' if i == 5 else ','
 440             ret.append("            {0}{1}".format(ps, comma))
 441         ret.append("        });")
 442         ret.append("    endrule")
 443         return '\n'.join(ret)
 444
 445
 446 class pwm(PBase):
 447
 448     def slowimport(self):
 449         return "        import pwm::*;"
 450
 451     def slowifdecl(self):
 452         return "        interface PWMIO pwm{0}_io;"
 453
 454     def num_axi_regs32(self):
 455         return 4
 456
 457     def mkslow_peripheral(self, size=0):
 458         return "        Ifc_PWM_bus pwm{0} <- mkPWM_bus(sp_clock);"
 459
 460     def _mk_connection(self, name=None, count=0):
 461         return "pwm{0}.axi4_slave"
 462
 463     def pinname_out(self, pname):
 464         return {'out': 'pwm_io.pwm_o'}.get(pname, '')
 465
 466
 467 class gpio(PBase):
 468
 469     def slowimport(self):
 470         return "     import pinmux::*;\n" + \
 471                "     import mux::*;\n" + \
 472                "     import gpio::*;\n"
 473
 474     def slowifdeclmux(self):
 475         size = len(self.peripheral.pinspecs)
 476         return "    interface GPIO_config#(%d) pad_config{0};" % size
 477
 478     def num_axi_regs32(self):
 479         return 2
 480
 481     def axi_slave_idx(self, idx, name, ifacenum):
 482         """ generates AXI slave number definition, except
 483             GPIO also has a muxer per bank
 484         """
 485         name = name.upper()
 486         mname = 'mux' + name[4:]
 487         mname = mname.upper()
 488         print "AXIslavenum", name,  mname
 489         (ret, x) = PBase.axi_slave_idx(self, idx, name, ifacenum)
 490         (ret2, x) = PBase.axi_slave_idx(self, idx+1, mname, ifacenum)
 491         return ("%s\n%s" % (ret, ret2), 2)
 492
 493     def mkslow_peripheral(self, size=0):
 494         print "gpioslow", self.peripheral,  dir(self.peripheral)
 495         size = len(self.peripheral.pinspecs)
 496         return "        MUX#(%d) mux{0} <- mkmux();\n" % size + \
 497                "        GPIO#(%d) gpio{0} <- mkgpio();" % size
 498
 499     def mk_connection(self, count):
 500         print "GPIO mk_conn", self.name, count
 501         res = []
 502         dname = self.mksuffix(self.name, count)
 503         for i, n in enumerate(['gpio' + dname, 'mux' + dname]):
 504             res.append(PBase.mk_connection(self, count, n))
 505         return '\n'.join(res)
 506
 507     def _mk_connection(self, name=None, count=0):
 508         n = self.mksuffix(name, count)
 509         if name.startswith('gpio'):
 510             return "gpio{0}.axi_slave".format(n)
 511         if name.startswith('mux'):
 512             return "mux{0}.axi_slave".format(n)
 513
 514     def mksuffix(self, name, i):
 515         if name.startswith('mux'):
 516             return name[3:]
 517         return name[4:]
 518
 519     def mk_cellconn(self, cellnum, name, count):
 520         ret = []
 521         bank = self.mksuffix(name, count)
 522         txt = "       pinmux.mux_lines.cell{0}_mux(mux{1}.mux_config.mux[{2}]);"
 523         for p in self.peripheral.pinspecs:
 524             ret.append(txt.format(cellnum, bank, p['name'][1:]))
 525             cellnum += 1
 526         return ("\n".join(ret), cellnum)
 527
 528     def pinname_out(self, pname):
 529         return "func.gpio_out[{0}]".format(pname[1:])
 530
 531     def pinname_outen(self, pname):
 532         return "func.gpio_out_en[{0}]".format(pname[1:])
 533
 534     def mk_pincon(self, name, count):
 535         ret = [PBase.mk_pincon(self, name, count)]
 536         # special-case for gpio in, store in a temporary vector
 537         plen = len(self.peripheral.pinspecs)
 538         ret.append("    rule con_%s%d_in;" % (name, count))
 539         ret.append("       Vector#({0},Bit#(1)) temp;".format(plen))
 540         for p in self.peripheral.pinspecs:
 541             typ = p['type']
 542             pname = p['name']
 543             idx = pname[1:]
 544             n = name
 545             sname = self.peripheral.pname(pname).format(count)
 546             ps = "pinmux.peripheral_side.%s_in" % sname
 547             ret.append("        temp[{0}]={1};".format(idx, ps))
 548         ret.append("        {0}.func.gpio_in(temp);".format(name))
 549         ret.append("    endrule")
 550         return '\n'.join(ret)
 551
 552
 553 axi_slave_declarations = """\
 554 typedef  0  SlowMaster;
 555 {0}
 556 typedef  TAdd#(LastGen_slave_num,`ifdef CLINT       1 `else 0 `endif )
 557               CLINT_slave_num;
 558 typedef  TAdd#(CLINT_slave_num  ,`ifdef PLIC        1 `else 0 `endif )
 559               Plic_slave_num;
 560 typedef  TAdd#(Plic_slave_num   ,`ifdef AXIEXP      1 `else 0 `endif )
 561               AxiExp1_slave_num;
 562 typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
 563 """
 564
 565 pinmux_cellrule = """\
 566     rule connect_select_lines_pinmux;
 567 {0}
 568     endrule
 569 """
 570
 571
 572 class CallFn(object):
 573     def __init__(self, peripheral, name):
 574         self.peripheral = peripheral
 575         self.name = name
 576
 577     def __call__(self, *args):
 578         #print "__call__", self.name, self.peripheral.slow, args
 579         if not self.peripheral.slow:
 580             return ''
 581         return getattr(self.peripheral.slow, self.name)(*args[1:])
 582
 583
 584 class PeripheralIface(object):
 585     def __init__(self, ifacename):
 586         self.slow = None
 587         slow = slowfactory.getcls(ifacename)
 588         print "Iface", ifacename, slow
 589         if slow:
 590             self.slow = slow(ifacename)
 591             self.slow.peripheral = self
 592         for fname in ['slowimport', 'slowifdecl', 'slowifdeclmux',
 593                       'mkslow_peripheral',
 594                       'mk_connection', 'mk_cellconn', 'mk_pincon']:
 595             fn = CallFn(self, fname)
 596             setattr(self, fname, types.MethodType(fn, self))
 597
 598         #print "PeripheralIface"
 599         #print dir(self)
 600
 601     def mksuffix(self, name, i):
 602         if self.slow is None:
 603             return i
 604         return self.slow.mksuffix(name, i)
 605
 606     def axi_reg_def(self, start, count):
 607         if not self.slow:
 608             return ('', 0)
 609         return self.slow.axi_reg_def(start, self.ifacename, count)
 610
 611     def axi_slave_idx(self, start, count):
 612         if not self.slow:
 613             return ('', 0)
 614         return self.slow.axi_slave_idx(start, self.ifacename, count)
 615
 616     def axi_addr_map(self, count):
 617         if not self.slow:
 618             return ''
 619         return self.slow.axi_addr_map(self.ifacename, count)
 620
 621
 622 class PeripheralInterfaces(object):
 623     def __init__(self):
 624         pass
 625
 626     def slowimport(self, *args):
 627         ret = []
 628         for (name, count) in self.ifacecount:
 629             #print "slowimport", name, self.data[name].slowimport
 630             ret.append(self.data[name].slowimport())
 631         return '\n'.join(list(filter(None, ret)))
 632
 633     def slowifdeclmux(self, *args):
 634         ret = []
 635         for (name, count) in self.ifacecount:
 636             for i in range(count):
 637                 ret.append(self.data[name].slowifdeclmux().format(i, name))
 638         return '\n'.join(list(filter(None, ret)))
 639
 640     def slowifdecl(self, *args):
 641         ret = []
 642         for (name, count) in self.ifacecount:
 643             for i in range(count):
 644                 ret.append(self.data[name].slowifdecl().format(i, name))
 645         return '\n'.join(list(filter(None, ret)))
 646
 647     def axi_reg_def(self, *args):
 648         ret = []
 649         start = 0x00011100  # start of AXI peripherals address
 650         for (name, count) in self.ifacecount:
 651             for i in range(count):
 652                 x = self.data[name].axi_reg_def(start, i)
 653                 #print ("ifc", name, x)
 654                 (rdef, offs) = x
 655                 ret.append(rdef)
 656                 start += offs
 657         return '\n'.join(list(filter(None, ret)))
 658
 659     def axi_slave_idx(self, *args):
 660         ret = []
 661         start = 0
 662         for (name, count) in self.ifacecount:
 663             for i in range(count):
 664                 (rdef, offs) = self.data[name].axi_slave_idx(start, i)
 665                 #print ("ifc", name, rdef, offs)
 666                 ret.append(rdef)
 667                 start += offs
 668         ret.append("typedef %d LastGen_slave_num;" % (start - 1))
 669         decls = '\n'.join(list(filter(None, ret)))
 670         return axi_slave_declarations.format(decls)
 671
 672     def axi_addr_map(self, *args):
 673         ret = []
 674         for (name, count) in self.ifacecount:
 675             for i in range(count):
 676                 ret.append(self.data[name].axi_addr_map(i))
 677         return '\n'.join(list(filter(None, ret)))
 678
 679     def mkslow_peripheral(self, *args):
 680         ret = []
 681         for (name, count) in self.ifacecount:
 682             for i in range(count):
 683                 print "mkslow", name, count
 684                 x = self.data[name].mkslow_peripheral()
 685                 print name, count, x
 686                 suffix = self.data[name].mksuffix(name, i)
 687                 ret.append(x.format(suffix))
 688         return '\n'.join(list(filter(None, ret)))
 689
 690     def mk_connection(self, *args):
 691         ret = []
 692         for (name, count) in self.ifacecount:
 693             for i in range(count):
 694                 print "mk_conn", name, i
 695                 txt = self.data[name].mk_connection(i)
 696                 if name == 'gpioa':
 697                     print "txt", txt
 698                     print self.data[name].mk_connection
 699                 ret.append(txt)
 700         return '\n'.join(list(filter(None, ret)))
 701
 702     def mk_cellconn(self):
 703         ret = []
 704         cellcount = 0
 705         for (name, count) in self.ifacecount:
 706             for i in range(count):
 707                 res = self.data[name].mk_cellconn(cellcount, name, i)
 708                 if not res:
 709                     continue
 710                 (txt, cellcount) = res
 711                 ret.append(txt)
 712         ret = '\n'.join(list(filter(None, ret)))
 713         return pinmux_cellrule.format(ret)
 714
 715     def mk_pincon(self):
 716         ret = []
 717         for (name, count) in self.ifacecount:
 718             for i in range(count):
 719                 txt = self.data[name].mk_pincon(name, i)
 720                 ret.append(txt)
 721         return '\n'.join(list(filter(None, ret)))
 722
 723
 724 class PFactory(object):
 725     def getcls(self, name):
 726         for k, v in {'uart': uart,
 727                      'rs232': rs232,
 728                      'twi': twi,
 729                      'qspi': qspi,
 730                      'spi': spi,
 731                      'pwm': pwm,
 732                      'eint': eint,
 733                      'gpio': gpio
 734                      }.items():
 735             if name.startswith(k):
 736                 return v
 737         return None
 738
 739
 740 slowfactory = PFactory()
 741
 742 if __name__ == '__main__':
 743     p = uart('uart')
 744     print p.slowimport()
 745     print p.slowifdecl()
 746     i = PeripheralIface('uart')
 747     print i, i.slow
 748     i = PeripheralIface('gpioa')
 749     print i, i.slow