7d33d6f387d29e888cdf87d24f0663d7e67c5661
1 # ================================== Steps to add peripherals ============
2 # Step-1: create interface declaration for the peripheral to be added.
3 # Remember these are interfaces defined for the pinmux and hence
4 # will be opposite to those defined at the peripheral.
5 # For eg. the output TX from the UART will be input (method Action)
7 # These changes will have to be done in interface_decl.py
8 # Step-2 define the wires that will be required to transfer data from the
9 # peripheral interface to the IO cell and vice-versa. Create a
10 # mkDWire for each input/output between the peripheral and the
11 # pinmux. Also create an implicit wire of GenericIOType for each cell
12 # that can be connected to a each bit from the peripheral.
13 # These changes will have to be done in wire_def.py
14 # Step-3: create the definitions for each of the methods defined above.
15 # These changes will have to be done in interface_decl.py
16 # ========================================================================
18 # default module imports
24 # project module imports
25 from bsv
.interface_decl
import Interfaces
, mux_interface
, io_interface
26 from parse
import Parse
27 from bsv
.actual_pinmux
import init
28 from bsv
.bus_transactors
import axi4_lite
32 This BSV file has been generated by the PinMux tool available at:
33 https://bitbucket.org/casl/pinmux.
35 Authors: Neel Gala, Luke
36 Date of generation: ''' + time
.strftime("%c") + '''
39 header
= copyright
+ '''
49 def pinmuxgen(pth
=None, verify
=True):
50 """ populating the file with the code
53 p
= Parse(pth
, verify
)
54 iocells
= Interfaces()
55 iocells
.ifaceadd('io', p
.N_IO
, io_interface
, 0)
56 ifaces
= Interfaces(pth
)
57 #ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
62 bp
= os
.path
.join(pth
, bp
)
63 if not os
.path
.exists(bp
):
65 bl
= os
.path
.join(bp
, 'bsv_lib')
66 if not os
.path
.exists(bl
):
69 cwd
= os
.path
.split(__file__
)[0]
71 # copy over template and library files
72 shutil
.copyfile(os
.path
.join(cwd
, 'Makefile.template'),
73 os
.path
.join(bp
, 'Makefile'))
74 cwd
= os
.path
.join(cwd
, 'bsv_lib')
75 for fname
in ['AXI4_Lite_Types.bsv', 'Semi_FIFOF.bsv',
76 'gpio.bsv', 'mux.bsv']:
77 shutil
.copyfile(os
.path
.join(cwd
, fname
),
78 os
.path
.join(bl
, fname
))
80 bus
= os
.path
.join(bp
, 'busenable.bsv')
81 pmp
= os
.path
.join(bp
, 'pinmux.bsv')
82 ptp
= os
.path
.join(bp
, 'PinTop.bsv')
83 bvp
= os
.path
.join(bp
, 'bus.bsv')
84 idef
= os
.path
.join(bp
, 'instance_defines.bsv')
85 slow
= os
.path
.join(bp
, 'slow_peripherals.bsv')
86 slowt
= os
.path
.join(cwd
, 'slow_peripherals_template.bsv')
88 write_pmp(pmp
, p
, ifaces
, iocells
)
89 write_ptp(ptp
, p
, ifaces
)
90 write_bvp(bvp
, p
, ifaces
)
91 write_bus(bus
, p
, ifaces
)
92 write_instances(idef
, p
, ifaces
)
93 write_slow(slow
, slowt
, p
, ifaces
)
96 def write_slow(slow
, template
, p
, ifaces
):
97 """ write out the slow_peripherals.bsv file.
98 joins all the peripherals together into one AXI Lite interface
100 with
open(template
) as bsv_file
:
101 template
= bsv_file
.read()
102 imports
= ifaces
.slowimport()
103 ifdecl
= ifaces
.slowifdecl()
104 with
open(slow
, "w") as bsv_file
:
105 bsv_file
.write(template
.format(imports
, ifdecl
))
108 def write_bus(bus
, p
, ifaces
):
109 # package and interface declaration followed by
110 # the generic io_cell definition
111 with
open(bus
, "w") as bsv_file
:
112 ifaces
.busfmt(bsv_file
)
115 def write_pmp(pmp
, p
, ifaces
, iocells
):
116 # package and interface declaration followed by
117 # the generic io_cell definition
118 with
open(pmp
, "w") as bsv_file
:
119 bsv_file
.write(header
)
121 cell_bit_width
= 'Bit#(%d)' % p
.cell_bitwidth
123 interface MuxSelectionLines;
125 // declare the method which will capture the user pin-mux
126 // selection values.The width of the input is dependent on the number
127 // of muxes happening per IO. For now we have a generalized width
128 // where each IO will have the same number of muxes.''')
130 for cell
in p
.muxed_cells
:
131 bsv_file
.write(mux_interface
.ifacefmt(cell
[0], cell_bit_width
))
133 bsv_file
.write("\n endinterface\n")
137 interface IOCellSide;
138 // declare the interface to the IO cells.
139 // Each IO cell will have 1 input field (output from pin mux)
140 // and an output and out-enable field (input to pinmux)''')
142 # == create method definitions for all iocell interfaces ==#
143 iocells
.ifacefmt(bsv_file
)
145 # ===== finish interface definition and start module definition=======
146 bsv_file
.write("\n endinterface\n")
148 # ===== io cell definition =======
151 interface PeripheralSide;
152 // declare the interface to the peripherals
153 // Each peripheral's function will be either an input, output
154 // or be bi-directional. an input field will be an output from the
155 // peripheral and an output field will be an input to the peripheral.
156 // Bi-directional functions also have an output-enable (which
157 // again comes *in* from the peripheral)''')
158 # ==============================================================
160 # == create method definitions for all peripheral interfaces ==#
161 ifaces
.ifacefmt(bsv_file
)
162 bsv_file
.write("\n endinterface\n")
164 # ===== finish interface definition and start module definition=======
167 interface Ifc_pinmux;
168 // this interface controls how each IO cell is routed. setting
169 // any given IO cell's mux control value will result in redirection
170 // of not just the input or output to different peripheral functions
171 // but also the *direction* control - if appropriate - as well.
172 interface MuxSelectionLines mux_lines;
174 // this interface contains the inputs, outputs and direction-control
175 // lines for all peripherals. GPIO is considered to also be just
176 // a peripheral because it also has in, out and direction-control.
177 interface PeripheralSide peripheral_side;
179 // this interface is to be linked to the individual IO cells.
180 // if looking at a "non-muxed" GPIO design, basically the
181 // IO cell input, output and direction-control wires are cut
182 // (giving six pairs of dangling wires, named left and right)
183 // these iocells are routed in their place on one side ("left")
184 // and the matching *GPIO* peripheral interfaces in/out/dir
185 // connect to the OTHER side ("right"). the result is that
186 // the muxer settings end up controlling the routing of where
187 // the I/O from the IOcell actually goes.
188 interface IOCellSide iocell_side;
191 module mkpinmux(Ifc_pinmux);
193 # ====================================================================
195 # ======================= create wire and registers =================#
197 // the followins wires capture the pin-mux selection
198 // values for each mux assigned to a CELL
200 for cell
in p
.muxed_cells
:
201 bsv_file
.write(mux_interface
.wirefmt(
202 cell
[0], cell_bit_width
))
204 iocells
.wirefmt(bsv_file
)
205 ifaces
.wirefmt(bsv_file
)
208 # ====================================================================
209 # ========================= Actual pinmuxing ========================#
211 /*====== This where the muxing starts for each io-cell======*/
212 Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
214 bsv_file
.write(p
.pinmux
)
216 /*============================================================*/
218 # ====================================================================
219 # ================= interface definitions for each method =============#
221 interface mux_lines = interface MuxSelectionLines
223 for cell
in p
.muxed_cells
:
225 mux_interface
.ifacedef(
226 cell
[0], cell_bit_width
))
227 bsv_file
.write("\n endinterface;")
230 interface iocell_side = interface IOCellSide
232 iocells
.ifacedef(bsv_file
)
233 bsv_file
.write("\n endinterface;")
236 interface peripheral_side = interface PeripheralSide
238 ifaces
.ifacedef(bsv_file
)
239 bsv_file
.write("\n endinterface;")
241 bsv_file
.write(footer
)
242 print("BSV file successfully generated: bsv_src/pinmux.bsv")
243 # ======================================================================
246 def write_ptp(ptp
, p
, ifaces
):
247 with
open(ptp
, 'w') as bsv_file
:
248 bsv_file
.write(copyright
+ '''
251 interface Ifc_PintTop;
252 method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
253 method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
254 interface PeripheralSide peripheral_side;
257 module mkPinTop(Ifc_PintTop);
258 // instantiate the pin-mux module here
259 Ifc_pinmux pinmux <-mkpinmux;
261 // declare the registers which will be used to mux the IOs
262 '''.format(p
.ADDR_WIDTH
, p
.DATA_WIDTH
))
264 cell_bit_width
= str(p
.cell_bitwidth
)
265 for cell
in p
.muxed_cells
:
267 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
268 cell_bit_width
, cell
[0]))
271 // rule to connect the registers to the selection lines of the
273 rule connect_selection_registers;''')
275 for cell
in p
.muxed_cells
:
277 pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell
[0]))
281 // method definitions for the write user interface
282 method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
284 case (addr[{0}:{1}])'''.format(p
.upper_offset
, p
.lower_offset
,
285 p
.ADDR_WIDTH
, p
.DATA_WIDTH
))
287 for cell
in p
.muxed_cells
:
289 {0}: rg_muxio_{1}<=truncate(data);'''.format(index
, cell
[0]))
299 // method definitions for the read user interface
300 method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
303 case (addr[{0}:{1}])'''.format(p
.upper_offset
, p
.lower_offset
,
304 p
.ADDR_WIDTH
, p
.DATA_WIDTH
))
306 for cell
in p
.muxed_cells
:
308 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index
, cell
[0]))
314 return tuple2(err,data);
316 interface peripheral_side=pinmux.peripheral_side;
322 def write_bvp(bvp
, p
, ifaces
):
323 # ######## Generate bus transactors ################
324 gpiocfg
= '\t\tinterface GPIO_config#({4}) bank{3}_config;\n' \
325 '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) bank{3}_slave;'
326 muxcfg
= '\t\tinterface MUX_config#({4}) muxb{3}_config;\n' \
327 '\t\tinterface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxb{3}_slave;'
329 gpiodec
= '\tGPIO#({0}) mygpio{1} <- mkgpio();'
330 muxdec
= '\tMUX#({0}) mymux{1} <- mkmux();'
331 gpioifc
= '\tinterface bank{0}_config=mygpio{0}.pad_config;\n' \
332 '\tinterface bank{0}_slave=mygpio{0}.axi_slave;'
333 muxifc
= '\tinterface muxb{0}_config=mymux{0}.mux_config;\n' \
334 '\tinterface muxb{0}_slave=mymux{0}.axi_slave;'
335 with
open(bvp
, 'w') as bsv_file
:
336 # assume here that all muxes have a 1:1 gpio
340 iks
= sorted(ifaces
.keys())
342 if not iname
.startswith('gpio'): # TODO: declare other interfaces
346 npins
= len(ifc
.pinspecs
)
347 cfg
.append(gpiocfg
.format(p
.ADDR_WIDTH
, p
.DATA_WIDTH
,
350 cfg
.append(muxcfg
.format(p
.ADDR_WIDTH
, p
.DATA_WIDTH
,
353 decl
.append(gpiodec
.format(npins
, bank
))
354 decl
.append(muxdec
.format(npins
, bank
))
355 idec
.append(gpioifc
.format(bank
))
356 idec
.append(muxifc
.format(bank
))
358 print (ifaces
.items())
359 print (dir(ifaces
['gpioa']))
360 print (ifaces
['gpioa'].pinspecs
)
361 gpiodecl
= '\n'.join(decl
) + '\n' + '\n'.join(idec
)
362 gpiocfg
= '\n'.join(cfg
)
363 bsv_file
.write(axi4_lite
.format(gpiodecl
, gpiocfg
))
364 # ##################################################
367 def write_instances(idef
, p
, ifaces
):
368 with
open(idef
, 'w') as bsv_file
:
374 bsv_file
.write(txt
.format(p
.ADDR_WIDTH
, p
.DATA_WIDTH
))