src/bus_transactors.py

   1
   2 axi4_lite = '''
   3 package bus;
   4
   5   /*=== Project imports ===*/
   6   import AXI4_Lite_Types::*;
   7   import PinTop::*;
   8   import pinmux::*;
   9   import Semi_FIFOF::*;
  10   /*======================*/
  11
  12   interface Ifc_bus;
  13     interface AXI4_Lite_Slave_IFC #({0}, {1}, 0) axi_side;
  14     interface PeripheralSide peripheral_side;
  15   endinterface
  16
  17   module mkbus(Ifc_bus);
  18     Ifc_PintTop pintop <-mkPinTop;
  19     AXI4_Lite_Slave_Xactor_IFC#({0}, {1}, 0) slave_xactor <-
  20                                                     mkAXI4_Lite_Slave_Xactor();
  21     rule read_transaction;
  22       let req<-pop_o(slave_xactor.o_rd_addr);
  23       let {{err,data}}=pintop.read(req.araddr);
  24       AXI4_Lite_Rd_Data#({0}, 0) r = AXI4_Lite_Rd_Data {{
  25                                   rresp: err?AXI4_LITE_SLVERR:AXI4_LITE_OKAY,
  26                                   rdata: zeroExtend(data) , ruser: 0}};
  27       slave_xactor.i_rd_data.enq(r);
  28     endrule
  29
  30     rule write_transaction;
  31       let addr_req<-pop_o(slave_xactor.o_wr_addr);
  32       let data_req<-pop_o(slave_xactor.o_wr_data);
  33       let err<-pintop.write(addr_req.awaddr, data_req.wdata);
  34       let b = AXI4_Lite_Wr_Resp {{bresp: err?AXI4_LITE_SLVERR:AXI4_LITE_OKAY,
  35                                 buser: ?}};
  36       slave_xactor.i_wr_resp.enq (b);
  37     endrule
  38     interface axi_side= slave_xactor.axi_side;
  39     interface peripheral_side=pintop.peripheral_side;
  40   endmodule
  41 endpackage
  42 '''