src/decoder/power_major_decoder.py

   1 from nmigen import Module, Elaboratable, Signal
   2 import csv
   3 import os
   4 from power_enums import (Function, InternalOp, In1Sel, In2Sel, In3Sel,
   5                          OutSel, RC, LdstLen, CryIn)
   6
   7
   8 # names of the fields in major.csv that don't correspond to an enum
   9 single_bit_flags = ['CR in', 'CR out', 'inv A', 'inv out',
  10                     'cry out', 'BR', 'sgn ext', 'upd', 'rsrv', '32b',
  11                     'sgn', 'lk', 'sgl pipe']
  12
  13
  14 def get_signal_name(name):
  15     return name.lower().replace(' ', '_')
  16
  17
  18 def get_csv(name):
  19     file_dir = os.path.dirname(os.path.realpath(__file__))
  20     with open(os.path.join(file_dir, name)) as csvfile:
  21         reader = csv.DictReader(csvfile)
  22         return list(reader)
  23
  24
  25 major_opcodes = get_csv("major.csv")
  26
  27
  28 class PowerMajorDecoder(Elaboratable):
  29     def __init__(self):
  30         self.opcode_in = Signal(6, reset_less=True)
  31
  32         self.function_unit = Signal(Function, reset_less=True)
  33         self.internal_op = Signal(InternalOp, reset_less=True)
  34         self.in1_sel = Signal(In1Sel, reset_less=True)
  35         self.in2_sel = Signal(In2Sel, reset_less=True)
  36         self.in3_sel = Signal(In3Sel, reset_less=True)
  37         self.out_sel = Signal(OutSel, reset_less=True)
  38         self.ldst_len = Signal(LdstLen, reset_less=True)
  39         self.rc_sel = Signal(RC, reset_less=True)
  40         self.cry_in = Signal(CryIn, reset_less=True)
  41         for bit in single_bit_flags:
  42             name = get_signal_name(bit)
  43             setattr(self, name,
  44                     Signal(reset_less=True, name=name))
  45
  46     def elaborate(self, platform):
  47         m = Module()
  48         comb = m.d.comb
  49
  50         with m.Switch(self.opcode_in):
  51             for row in major_opcodes:
  52                 opcode = int(row['opcode'])
  53                 with m.Case(opcode):
  54                     comb += self.function_unit.eq(Function[row['unit']])
  55                     comb += self.internal_op.eq(InternalOp[row['internal op']])
  56                     comb += self.in1_sel.eq(In1Sel[row['in1']])
  57                     comb += self.in2_sel.eq(In2Sel[row['in2']])
  58                     comb += self.in3_sel.eq(In3Sel[row['in3']])
  59                     comb += self.out_sel.eq(OutSel[row['out']])
  60                     comb += self.ldst_len.eq(LdstLen[row['ldst len']])
  61                     comb += self.rc_sel.eq(RC[row['rc']])
  62                     comb += self.cry_in.eq(CryIn[row['cry in']])
  63                     for bit in single_bit_flags:
  64                         sig = getattr(self, get_signal_name(bit))
  65                         comb += sig.eq(int(row[bit]))
  66         return m
  67
  68     def ports(self):
  69         regular =[self.opcode_in,
  70                   self.function_unit,
  71                   self.in1_sel,
  72                   self.in2_sel,
  73                   self.in3_sel,
  74                   self.out_sel,
  75                   self.ldst_len,
  76                   self.rc_sel,
  77                   self.internal_op]
  78         single_bit_ports = [getattr(self, get_signal_name(x))
  79                             for x in single_bit_flags]
  80         return regular + single_bit_ports