src/decoder/test/test_power_decoder.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay
   3 from nmigen.test.utils import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import sys
   6 import os
   7 import unittest
   8 sys.path.append("../")
   9 from power_decoder import (PowerDecoder)
  10 from power_enums import (Function, InternalOp, In1Sel, In2Sel, In3Sel,
  11                          OutSel, RC, LdstLen, CryIn, single_bit_flags,
  12                          get_signal_name, get_csv)
  13
  14
  15 class DecoderTestCase(FHDLTestCase):
  16
  17     def run_tst(self, bitsel, csvname, suffix=None, opint=True):
  18         m = Module()
  19         comb = m.d.comb
  20         opcode = Signal(32)
  21         function_unit = Signal(Function)
  22         internal_op = Signal(InternalOp)
  23         in1_sel = Signal(In1Sel)
  24         in2_sel = Signal(In2Sel)
  25         in3_sel = Signal(In3Sel)
  26         out_sel = Signal(OutSel)
  27         rc_sel = Signal(RC)
  28         ldst_len = Signal(LdstLen)
  29         cry_in = Signal(CryIn)
  30
  31         opcodes = get_csv(csvname)
  32         m.submodules.dut = dut = PowerDecoder(32, opcodes, bitsel=bitsel,
  33                                               opint=opint, suffix=suffix)
  34         comb += [dut.opcode_in.eq(opcode),
  35                  function_unit.eq(dut.op.function_unit),
  36                  in1_sel.eq(dut.op.in1_sel),
  37                  in2_sel.eq(dut.op.in2_sel),
  38                  in3_sel.eq(dut.op.in3_sel),
  39                  out_sel.eq(dut.op.out_sel),
  40                  rc_sel.eq(dut.op.rc_sel),
  41                  ldst_len.eq(dut.op.ldst_len),
  42                  cry_in.eq(dut.op.cry_in),
  43                  internal_op.eq(dut.op.internal_op)]
  44
  45         sim = Simulator(m)
  46
  47         def process():
  48             for row in dut.opcodes:
  49                 if not row['unit']:
  50                     continue
  51                 op = row['opcode']
  52                 if not opint: # HACK: convert 001---10 to 0b00100010
  53                     op = "0b" + op.replace('-', '0')
  54                 print ("opint", opint, row['opcode'], op)
  55                 yield opcode.eq(0)
  56                 yield opcode[bitsel[0]:bitsel[1]].eq(int(op, 0))
  57                 yield Delay(1e-6)
  58                 signals = [(function_unit, Function, 'unit'),
  59                            (internal_op, InternalOp, 'internal op'),
  60                            (in1_sel, In1Sel, 'in1'),
  61                            (in2_sel, In2Sel, 'in2'),
  62                            (in3_sel, In3Sel, 'in3'),
  63                            (out_sel, OutSel, 'out'),
  64                            (rc_sel, RC, 'rc'),
  65                            (cry_in, CryIn, 'cry in'),
  66                            (ldst_len, LdstLen, 'ldst len')]
  67                 for sig, enm, name in signals:
  68                     result = yield sig
  69                     expected = enm[row[name]]
  70                     msg = f"{sig.name} == {enm(result)}, expected: {expected}"
  71                     self.assertEqual(enm(result), expected, msg)
  72                 for bit in single_bit_flags:
  73                     sig = getattr(dut.op, get_signal_name(bit))
  74                     result = yield sig
  75                     expected = int(row[bit])
  76                     msg = f"{sig.name} == {result}, expected: {expected}"
  77                     self.assertEqual(expected, result, msg)
  78         sim.add_process(process)
  79         prefix = os.path.splitext(csvname)[0]
  80         with sim.write_vcd("%s.vcd" % prefix, "%s.gtkw" % prefix, traces=[
  81                 opcode, function_unit, internal_op,
  82                 in1_sel, in2_sel]):
  83             sim.run()
  84
  85     def generate_ilang(self, bitsel, csvname, opint=True, suffix=None):
  86         prefix = os.path.splitext(csvname)[0]
  87         if suffix:
  88             prefix += ".%s" % str(suffix).replace(" ", "")[1:-1]
  89         dut = PowerDecoder(32, get_csv(csvname), bitsel=bitsel,
  90                            opint=opint, suffix=suffix)
  91         vl = rtlil.convert(dut, ports=dut.ports())
  92         with open("%s_decoder.il" % prefix, "w") as f:
  93             f.write(vl)
  94
  95     def test_major(self):
  96         self.run_tst((26, 32), "major.csv")
  97         self.generate_ilang((26, 32), "major.csv")
  98
  99     # def test_minor_19(self):
 100     #     self.run_tst(10, "minor_19.csv", suffix=(0, 5))
 101     #     self.generate_ilang(10, "minor_19.csv", suffix=(0, 5))
 102
 103     # def test_minor_19_00000(self):
 104     #     self.run_tst(10, "minor_19_00000.csv")
 105     #     self.generate_ilang(10, "minor_19_00000.csv")
 106
 107     # def test_minor_30(self):
 108     #     self.run_tst(4, "minor_30.csv")
 109     #     self.generate_ilang(4, "minor_30.csv")
 110
 111     # def test_minor_31(self):
 112     #     self.run_tst(10, "minor_31.csv", suffix=(0, 5))
 113     #     self.generate_ilang(10, "minor_31.csv", suffix=(0, 5))
 114
 115     # #def test_minor_31_prefix(self):
 116     # #    self.run_tst(10, "minor_31.csv", suffix=(5, 10))
 117     # #    self.generate_ilang(10, "minor_31.csv", suffix=(5, 10))
 118
 119     # def test_extra(self):
 120     #     self.run_tst(32, "extra.csv", opint=False)
 121     #     self.generate_ilang(32, "extra.csv", opint=False)
 122
 123
 124 if __name__ == "__main__":
 125     unittest.main()