9955b66665e5b28e00aa1394b2d440cb4220f488
1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
3 from nmigen
.test
.utils
import FHDLTestCase
4 from nmigen
.cli
import rtlil
9 from power_decoder
import (PowerDecoder
)
10 from power_enums
import (Function
, InternalOp
, In1Sel
, In2Sel
, In3Sel
,
11 OutSel
, RC
, LdstLen
, CryIn
, single_bit_flags
,
15 class DecoderTestCase(FHDLTestCase
):
16 def run_test(self
, width
, csvname
, opint
=True):
19 opcode
= Signal(width
)
20 function_unit
= Signal(Function
)
21 internal_op
= Signal(InternalOp
)
22 in1_sel
= Signal(In1Sel
)
23 in2_sel
= Signal(In2Sel
)
24 in3_sel
= Signal(In3Sel
)
25 out_sel
= Signal(OutSel
)
27 ldst_len
= Signal(LdstLen
)
28 cry_in
= Signal(CryIn
)
30 m
.submodules
.dut
= dut
= PowerDecoder(width
, csvname
, opint
)
31 comb
+= [dut
.opcode_in
.eq(opcode
),
32 function_unit
.eq(dut
.op
.function_unit
),
33 in1_sel
.eq(dut
.op
.in1_sel
),
34 in2_sel
.eq(dut
.op
.in2_sel
),
35 in3_sel
.eq(dut
.op
.in3_sel
),
36 out_sel
.eq(dut
.op
.out_sel
),
37 rc_sel
.eq(dut
.op
.rc_sel
),
38 ldst_len
.eq(dut
.op
.ldst_len
),
39 cry_in
.eq(dut
.op
.cry_in
),
40 internal_op
.eq(dut
.op
.internal_op
)]
45 for row
in dut
.opcodes
:
49 if not opint
: # HACK: convert 001---10 to 0b00100010
50 op
= "0b" + op
.replace('-', '0')
51 print ("opint", opint
, row
['opcode'], op
)
52 yield opcode
.eq(int(op
, 0))
54 signals
= [(function_unit
, Function
, 'unit'),
55 (internal_op
, InternalOp
, 'internal op'),
56 (in1_sel
, In1Sel
, 'in1'),
57 (in2_sel
, In2Sel
, 'in2'),
58 (in3_sel
, In3Sel
, 'in3'),
59 (out_sel
, OutSel
, 'out'),
61 (cry_in
, CryIn
, 'cry in'),
62 (ldst_len
, LdstLen
, 'ldst len')]
63 for sig
, enm
, name
in signals
:
65 expected
= enm
[row
[name
]]
66 msg
= f
"{sig.name} == {enm(result)}, expected: {expected}"
67 self
.assertEqual(enm(result
), expected
, msg
)
68 for bit
in single_bit_flags
:
69 sig
= getattr(dut
.op
, get_signal_name(bit
))
71 expected
= int(row
[bit
])
72 msg
= f
"{sig.name} == {result}, expected: {expected}"
73 self
.assertEqual(expected
, result
, msg
)
74 sim
.add_process(process
)
75 with sim
.write_vcd("test.vcd", "test.gtkw", traces
=[
76 opcode
, function_unit
, internal_op
,
80 def generate_ilang(self
, width
, csvname
, opint
=True):
81 prefix
= os
.path
.splitext(csvname
)[0]
82 dut
= PowerDecoder(width
, csvname
, opint
)
83 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
84 with
open("%s_decoder.il" % prefix
, "w") as f
:
88 self
.run_test(6, "major.csv")
89 self
.generate_ilang(6, "major.csv")
91 def test_minor_19(self
):
92 self
.run_test(3, "minor_19.csv")
93 self
.generate_ilang(3, "minor_19.csv")
95 def test_minor_30(self
):
96 self
.run_test(4, "minor_30.csv")
97 self
.generate_ilang(4, "minor_30.csv")
99 def test_minor_31(self
):
100 self
.run_test(10, "minor_31.csv")
101 self
.generate_ilang(10, "minor_31.csv")
103 def test_minor_31(self
):
104 self
.run_test(32, "extra.csv", False)
105 self
.generate_ilang(32, "extra.csv", False)
107 if __name__
== "__main__":