src/ieee754/fpdiv/div2.py

   1 """IEEE Floating Point Divider
   2
   3 Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
   4 """
   5
   6 from nmigen import Module, Signal, Elaboratable
   7 from nmigen.cli import main, verilog
   8
   9 from ieee754.fpcommon.fpbase import FPState
  10 from ieee754.fpcommon.postcalc import FPAddStage1Data
  11 from .div0 import FPDivStage0Data # XXX TODO: replace
  12
  13
  14 class FPDivStage2Mod(FPState, Elaboratable):
  15     """ Second stage of div: preparation for normalisation.
  16     """
  17
  18     def __init__(self, pspec):
  19         self.pspec = pspec
  20         self.i = self.ispec()
  21         self.o = self.ospec()
  22
  23     def ispec(self):
  24         # TODO: DivPipeCoreInterstageData
  25         return FPDivStage0Data(self.pspec) # Q/Rem in...
  26
  27     def ospec(self):
  28         # XXX REQUIRED.  MUST NOT BE CHANGED.  this is the format
  29         # required for ongoing processing (normalisation, correction etc.)
  30         return FPAddStage1Data(self.pspec) # out to post-process
  31
  32     def process(self, i):
  33         return self.o
  34
  35     def setup(self, m, i):
  36         """ links module to inputs and outputs
  37         """
  38         m.submodules.div1 = self
  39         #m.submodules.div1_out_overflow = self.o.of
  40
  41         m.d.comb += self.i.eq(i)
  42
  43     def elaborate(self, platform):
  44         m = Module()
  45
  46         # copies sign and exponent and mantissa (mantissa to be overridden
  47         # below)
  48         m.d.comb += self.o.z.eq(self.i.z)
  49
  50         # TODO: this is "phase 3" of divide (the very end of the pipeline)
  51         # takes the Q and R data (whatever) and performs
  52         # last-stage guard/round/sticky and copies mantissa into z.
  53         # post-processing stages take care of things from that point.
  54
  55         # NOTE: this phase does NOT do ACTUAL DIV processing, it ONLY
  56         # does "conversion" *out* of the Q/REM last stage
  57
  58         with m.If(~self.i.out_do_z):
  59             mw = self.o.z.m_width
  60             m.d.comb += [
  61                 self.o.z.m.eq(self.i.product[mw+2:]),
  62                 self.o.of.m0.eq(self.i.product[mw+2]),
  63                 self.o.of.guard.eq(self.i.product[mw+1]),
  64                 self.o.of.round_bit.eq(self.i.product[mw]),
  65                 self.o.of.sticky.eq(self.i.product[0:mw].bool())
  66             ]
  67
  68         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
  69         m.d.comb += self.o.oz.eq(self.i.oz)
  70         m.d.comb += self.o.ctx.eq(self.i.ctx)
  71
  72         return m
  73
  74
  75 class FPDivStage2(FPState):
  76
  77     def __init__(self, pspec):
  78         FPState.__init__(self, "divider_1")
  79         self.mod = FPDivStage2Mod(pspec)
  80         self.out_z = FPNumBaseRecord(pspec, False)
  81         self.out_of = Overflow()
  82         self.norm_stb = Signal()
  83
  84     def setup(self, m, i):
  85         """ links module to inputs and outputs
  86         """
  87         self.mod.setup(m, i)
  88
  89         m.d.sync += self.norm_stb.eq(0) # sets to zero when not in div1 state
  90
  91         m.d.sync += self.out_of.eq(self.mod.out_of)
  92         m.d.sync += self.out_z.eq(self.mod.out_z)
  93         m.d.sync += self.norm_stb.eq(1)
  94
  95     def action(self, m):
  96         m.next = "normalise_1"
  97