src/ieee754/fpdiv/pipeline.py

   1 """IEEE Floating Point Divider Pipeline
   2
   3 Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
   4
   5 Stack looks like this:
   6
   7 scnorm   - FPDIVSpecialCasesDeNorm ispec FPADDBaseData
   8 ------                             ospec FPSCData
   9
  10                 StageChain: FPDIVSpecialCasesMod,
  11                             FPAddDeNormMod
  12
  13 pipediv0 - FPDivStagesSetup        ispec FPSCData
  14 --------                           ospec DivPipeCoreInterstageData
  15
  16                 StageChain: FPDivStage0Mod,
  17                             DivPipeSetupStage,
  18                             DivPipeCalculateStage,
  19                             ...
  20                             DivPipeCalculateStage
  21
  22 pipediv1 - FPDivStagesIntermediate ispec DivPipeCoreInterstageData
  23 --------                           ospec DivPipeCoreInterstageData
  24
  25                 StageChain: DivPipeCalculateStage,
  26                             ...
  27                             DivPipeCalculateStage
  28 ...
  29 ...
  30
  31 pipediv5 - FPDivStageFinal         ispec FPDivStage0Data
  32 --------                           ospec FPAddStage1Data
  33
  34                 StageChain: DivPipeCalculateStage,
  35                             ...
  36                             DivPipeCalculateStage,
  37                             DivPipeFinalStage,
  38                             FPDivStage2Mod
  39
  40 normpack - FPNormToPack            ispec FPAddStage1Data
  41 --------                           ospec FPPackData
  42
  43                 StageChain: Norm1ModSingle,
  44                             RoundMod,
  45                             CorrectionsMod,
  46                             PackMod
  47
  48 the number of combinatorial StageChains (n_comb_stages) in
  49 FPDivStages is an argument arranged to get the length of the whole
  50 pipeline down to sane numbers.
  51
  52 the reason for keeping the number of stages down is that for every
  53 pipeline clock delay, a corresponding ReservationStation is needed.
  54 if there are 24 pipeline stages, we need a whopping TWENTY FOUR
  55 RS's.  that's far too many.  6 is just about an acceptable number.
  56 even 8 is starting to get alarmingly high.
  57 """
  58
  59 from nmigen import Module
  60 from nmigen.cli import main, verilog
  61
  62 from nmutil.singlepipe import ControlBase
  63 from nmutil.concurrentunit import ReservationStations, num_bits
  64
  65 from ieee754.fpcommon.getop import FPADDBaseData
  66 from ieee754.fpcommon.denorm import FPSCData
  67 from ieee754.fpcommon.pack import FPPackData
  68 from ieee754.fpcommon.normtopack import FPNormToPack
  69 from ieee754.fpdiv.specialcases import FPDIVSpecialCasesDeNorm
  70 from ieee754.fpdiv.divstages import (FPDivStagesSetup,
  71                                      FPDivStagesIntermediate,
  72                                      FPDivStagesFinal)
  73 from ieee754.pipeline import PipelineSpec
  74
  75
  76 class FPDIVBasePipe(ControlBase):
  77     def __init__(self, pspec):
  78         ControlBase.__init__(self)
  79         self.pspec = pspec
  80
  81     def elaborate(self, platform):
  82         m = ControlBase.elaborate(self, platform)
  83
  84         pipechain = []
  85         n_stages = 6      # TODO (depends on width)
  86         n_comb_stages = 3  # TODO (depends on how many RS's we want)
  87         stage_idx = 0
  88         # to which the answer: "as few as possible"
  89         # is required.  too many ReservationStations
  90         # means "big problems".
  91
  92         for i in range(n_stages):
  93
  94             # needs to convert input from pipestart ospec
  95             if i == 0:
  96                 kls = FPDivStagesSetup
  97                 n_comb_stages -= 1  # reduce due to work done at start
  98
  99             # needs to convert output to pipeend ispec
 100             elif i == n_stages - 1:
 101                 kls = FPDivStagesFinal
 102                 n_comb_stages -= 1  # FIXME - reduce due to work done at end?
 103
 104             # intermediary stage
 105             else:
 106                 kls = FPDivStagesIntermediate
 107
 108             pipechain.append(kls(self.pspec, n_comb_stages, stage_idx))
 109             stage_idx += n_comb_stages # increment so that each CalcStage
 110                                        # gets a (correct) unique index
 111
 112         # start and end: unpack/specialcases then normalisation/packing
 113         pipestart = FPDIVSpecialCasesDeNorm(self.pspec)
 114         pipeend = FPNormToPack(self.pspec)
 115
 116         # add submodules
 117         m.submodules.scnorm = pipestart
 118         for i, p in enumerate(pipechain):
 119             setattr(m.submodules, "pipediv%d" % i, p)
 120         m.submodules.normpack = pipeend
 121
 122         # ControlBase.connect creates the "eqs" needed to connect each pipe
 123         m.d.comb += self.connect([pipestart] + pipechain + [pipeend])
 124
 125         return m
 126
 127
 128 class FPDIVMuxInOut(ReservationStations):
 129     """ Reservation-Station version of FPDIV pipeline.
 130
 131         * fan-in on inputs (an array of FPADDBaseData: a,b,mid)
 132         * N-stage divider pipeline
 133         * fan-out on outputs (an array of FPPackData: z,mid)
 134
 135         Fan-in and Fan-out are combinatorial.
 136
 137         :op_wid: - set this to the width of an operator which can
 138                    then be used to change the behaviour of the pipeline.
 139     """
 140
 141     def __init__(self, width, num_rows, op_wid=0):
 142         self.id_wid = num_bits(width)
 143         self.pspec = PipelineSpec(width, self.id_wid, op_wid)
 144         # XXX TODO - a class (or function?) that takes the pspec (right here)
 145         # and creates... "something".  that "something" MUST have an eq function
 146         # new_pspec = deepcopy(self.pspec)
 147         # new_pspec.opkls = DivPipeCoreOperation
 148         # self.alu = FPDIVBasePipe(new_pspec)
 149         self.alu = FPDIVBasePipe(self.pspec)
 150         ReservationStations.__init__(self, num_rows)
 151
 152     def i_specfn(self):
 153         return FPADDBaseData(self.pspec)
 154
 155     def o_specfn(self):
 156         return FPPackData(self.pspec)