src/ieee754/fpdiv/pipeline.py

   1 """IEEE Floating Point Divider Pipeline
   2
   3 Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
   4
   5 Stack looks like this:
   6
   7 scnorm   - FPDIVSpecialCasesDeNorm ispec FPADDBaseData
   8 ------                             ospec FPSCData
   9
  10                 StageChain: FPDIVSpecialCasesMod,
  11                             FPAddDeNormMod
  12
  13 pipediv0 - FPDivStagesSetup        ispec FPSCData
  14 --------                           ospec DivPipeInterstageData
  15
  16                 StageChain: FPDivStage0Mod,
  17                             DivPipeSetupStage,
  18                             DivPipeCalculateStage,
  19                             ...
  20                             DivPipeCalculateStage
  21
  22 pipediv1 - FPDivStagesIntermediate ispec DivPipeInterstageData
  23 --------                           ospec DivPipeInterstageData
  24
  25                 StageChain: DivPipeCalculateStage,
  26                             ...
  27                             DivPipeCalculateStage
  28 ...
  29 ...
  30
  31 pipediv5 - FPDivStageFinal         ispec FPDivStage0Data
  32 --------                           ospec FPAddStage1Data
  33
  34                 StageChain: DivPipeCalculateStage,
  35                             ...
  36                             DivPipeCalculateStage,
  37                             DivPipeFinalStage,
  38                             FPDivStage2Mod
  39
  40 normpack - FPNormToPack            ispec FPAddStage1Data
  41 --------                           ospec FPPackData
  42
  43                 StageChain: Norm1ModSingle,
  44                             RoundMod,
  45                             CorrectionsMod,
  46                             PackMod
  47
  48 the number of combinatorial StageChains (n_comb_stages) in
  49 FPDivStages is an argument arranged to get the length of the whole
  50 pipeline down to sane numbers.
  51
  52 the reason for keeping the number of stages down is that for every
  53 pipeline clock delay, a corresponding ReservationStation is needed.
  54 if there are 24 pipeline stages, we need a whopping TWENTY FOUR
  55 RS's.  that's far too many.  6 is just about an acceptable number.
  56 even 8 is starting to get alarmingly high.
  57 """
  58
  59 from nmigen import Module
  60 from nmigen.cli import main, verilog
  61
  62 from nmutil.singlepipe import ControlBase
  63 from nmutil.concurrentunit import ReservationStations, num_bits
  64
  65 from ieee754.fpcommon.getop import FPADDBaseData
  66 from ieee754.fpcommon.denorm import FPSCData
  67 from ieee754.fpcommon.fpbase import FPFormat
  68 from ieee754.fpcommon.pack import FPPackData
  69 from ieee754.fpcommon.normtopack import FPNormToPack
  70 from ieee754.fpdiv.specialcases import FPDIVSpecialCasesDeNorm
  71 from ieee754.fpdiv.divstages import (FPDivStagesSetup,
  72                                      FPDivStagesIntermediate,
  73                                      FPDivStagesFinal)
  74 from ieee754.pipeline import PipelineSpec
  75 from ieee754.div_rem_sqrt_rsqrt.core import DivPipeCoreConfig
  76
  77
  78 class FPDIVBasePipe(ControlBase):
  79     def __init__(self, pspec):
  80         self.pspec = pspec
  81         ControlBase.__init__(self)
  82
  83         pipechain = []
  84         # to which the answer: "as few as possible"
  85         # is required.  too many ReservationStations
  86         # means "big problems".
  87
  88         # get number of stages, set up loop.
  89         n_stages = pspec.core_config.n_stages
  90         n_comb_stages = self.pspec.n_comb_stages
  91         print ("n_stages", n_stages)
  92         stage_idx = 0
  93
  94         end = False
  95         while not end:
  96
  97             # needs to convert input from pipestart ospec
  98             if stage_idx == 0:
  99                 kls = FPDivStagesSetup # does n_comb_stages-1 calcs as well
 100
 101             # needs to convert output to pipeend ispec
 102             elif stage_idx + n_comb_stages >= n_stages:
 103                 kls = FPDivStagesFinal # does n_comb_stages-1 calcs as well
 104                 end = True
 105                 n_comb_stages = n_stages - stage_idx
 106
 107             # intermediary stage
 108             else:
 109                 kls = FPDivStagesIntermediate # does n_comb_stages calcs
 110
 111             # create (in each pipe) a StageChain n_comb_stages in length
 112             pipechain.append(kls(self.pspec, n_comb_stages, stage_idx))
 113             stage_idx += n_comb_stages # increment so that each CalcStage
 114                                        # gets a (correct) unique index
 115
 116         self.pipechain = pipechain
 117
 118         # start and end: unpack/specialcases then normalisation/packing
 119         self.pipestart = pipestart = FPDIVSpecialCasesDeNorm(self.pspec)
 120         self.pipeend = pipeend = FPNormToPack(self.pspec)
 121
 122         self._eqs = self.connect([pipestart] + pipechain + [pipeend])
 123
 124     def elaborate(self, platform):
 125         m = ControlBase.elaborate(self, platform)
 126
 127         # add submodules
 128         m.submodules.scnorm = self.pipestart
 129         for i, p in enumerate(self.pipechain):
 130             setattr(m.submodules, "pipediv%d" % i, p)
 131         m.submodules.normpack = self.pipeend
 132
 133         # ControlBase.connect creates the "eqs" needed to connect each pipe
 134         m.d.comb += self._eqs
 135
 136         return m
 137
 138 def roundup(x, mod):
 139     return x if x % mod == 0 else x + mod - x % mod
 140
 141
 142 class FPDIVMuxInOut(ReservationStations):
 143     """ Reservation-Station version of FPDIV pipeline.
 144
 145         * fan-in on inputs (an array of FPADDBaseData: a,b,mid)
 146         * N-stage divider pipeline
 147         * fan-out on outputs (an array of FPPackData: z,mid)
 148
 149         Fan-in and Fan-out are combinatorial.
 150
 151         :op_wid: - set this to the width of an operator which can
 152                    then be used to change the behaviour of the pipeline.
 153     """
 154
 155     def __init__(self, width, num_rows, op_wid=1):
 156         self.id_wid = num_bits(width)
 157         self.pspec = PipelineSpec(width, self.id_wid, op_wid)
 158         # get the standard mantissa width, store in the pspec HOWEVER...
 159         fmt = FPFormat.standard(width)
 160         log2_radix = 3     # tested options so far: 1, 2 and 3.
 161         n_comb_stages = 3  # TODO (depends on how many RS's we want)
 162
 163         # ...5 extra bits on the mantissa: MSB is zero, MSB-1 is 1
 164         # then there is guard, round and sticky at the LSB end.
 165         # also: round up to nearest radix
 166         if width == 16:
 167             extra = 5
 168         elif width == 32:
 169             extra = 6
 170         elif width == 64:
 171             extra = 5
 172         fmt.m_width = roundup(fmt.m_width + extra, log2_radix)
 173         print ("width", fmt.m_width)
 174
 175         cfg = DivPipeCoreConfig(fmt.m_width, fmt.fraction_width, log2_radix)
 176
 177         self.pspec.fpformat = fmt
 178         self.pspec.log2_radix = log2_radix
 179         self.pspec.n_comb_stages = n_comb_stages
 180         self.pspec.core_config = cfg
 181
 182         # XXX TODO - a class (or function?) that takes the pspec (right here)
 183         # and creates... "something".  that "something" MUST have an eq function
 184         # new_pspec = deepcopy(self.pspec)
 185         # new_pspec.opkls = DivPipeCoreOperation
 186         # self.alu = FPDIVBasePipe(new_pspec)
 187         self.alu = FPDIVBasePipe(self.pspec)
 188         ReservationStations.__init__(self, num_rows)
 189
 190     def i_specfn(self):
 191         return FPADDBaseData(self.pspec)
 192
 193     def o_specfn(self):
 194         return FPPackData(self.pspec)