src/iommu/axi_rab/axi_buffer_rab.py

   1 # this file has been generated by sv2nmigen
   2
   3 from nmigen import Signal, Module, Const, Cat, Elaboratable
   4
   5
   6 class axi_buffer_rab(Elaboratable):
   7
   8     def __init__(self):
   9         self.clk = Signal()  # input
  10         self.rstn = Signal()  # input
  11         self.data_out = Signal(DATA_WIDTH)  # output
  12         self.valid_out = Signal()  # output
  13         self.ready_in = Signal()  # input
  14         self.valid_in = Signal()  # input
  15         self.data_in = Signal(DATA_WIDTH)  # input
  16         self.ready_out = Signal()  # output
  17
  18     def elaborate(self, platform=None):
  19         m = Module()
  20         m.d.comb += self.full.eq(self.None)
  21         m.d.comb += self.data_out.eq(self.None)
  22         m.d.comb += self.valid_out.eq(self.None)
  23         m.d.comb += self.ready_out.eq(self.None)
  24         return m
  25
  26 # // Copyright 2018 ETH Zurich and University of Bologna.
  27 # // Copyright and related rights are licensed under the Solderpad Hardware
  28 # // License, Version 0.51 (the "License"); you may not use this file except in
  29 # // compliance with the License.  You may obtain a copy of the License at
  30 # // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
  31 # // or agreed to in writing, software, hardware and materials distributed under
  32 # // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
  33 # // CONDITIONS OF ANY KIND, either express or implied. See the License for the
  34 # // specific language governing permissions and limitations under the License.
  35 #
  36 # //import CfMath::log2;
  37 #
  38 # module axi_buffer_rab
  39 #  //#(
  40 #  //  parameter DATA_WIDTH,
  41 #  //  parameter BUFFER_DEPTH
  42 #  //)
  43 #  (
  44 #    input logic                   clk,
  45 #    input logic                   rstn,
  46 #
  47 #    // Downstream port
  48 #    output logic [DATA_WIDTH-1:0] data_out,
  49 #    output logic                  valid_out,
  50 #    input  logic                  ready_in,
  51 #
  52 #    // Upstream port
  53 #    input  logic                  valid_in,
  54 #    input  logic [DATA_WIDTH-1:0] data_in,
  55 #    output logic                  ready_out
  56 #  );
  57 #
  58 #  localparam integer LOG_BUFFER_DEPTH = log2(BUFFER_DEPTH);
  59 #
  60 #    // Internal data structures
  61 #    reg [LOG_BUFFER_DEPTH - 1 : 0] pointer_in;   // location to which we last wrote
  62 #    reg [LOG_BUFFER_DEPTH - 1 : 0] pointer_out;  // location from which we last sent
  63 #    reg     [LOG_BUFFER_DEPTH : 0] elements;     // number of elements in the buffer
  64 #    reg       [DATA_WIDTH - 1 : 0] buffer [BUFFER_DEPTH - 1 : 0];
  65 #
  66 #    wire full;
  67 #
  68 #    integer loop1;
  69 #
  70 #    assign full = (elements == BUFFER_DEPTH);
  71 #
  72 #    always @(posedge clk or negedge rstn)
  73 #      begin: elements_sequential
  74 #        if (rstn == 1'b0)
  75 #          elements <= 0;
  76 #        else
  77 #        begin
  78 #          // ------------------
  79 #          // Are we filling up?
  80 #          // ------------------
  81 #          // One out, none in
  82 #          if (ready_in && valid_out && (!valid_in || full))
  83 #            elements <= elements - 1;
  84 #          // None out, one in
  85 #          else if ((!valid_out || !ready_in) && valid_in && !full)
  86 #            elements <= elements + 1;
  87 #          // Else, either one out and one in, or none out and none in - stays unchanged
  88 #        end
  89 #      end
  90 #
  91 #    always @(posedge clk or negedge rstn)
  92 #      begin: buffers_sequential
  93 #        if (rstn == 1'b0)
  94 #        begin
  95 #          for (loop1 = 0 ; loop1 < BUFFER_DEPTH ; loop1 = loop1 + 1)
  96 #            buffer[loop1] <= 0;
  97 #        end
  98 #        else
  99 #        begin
 100 #          // Update the memory
 101 #          if (valid_in && !full)
 102 #            buffer[pointer_in] <= data_in;
 103 #        end
 104 #      end
 105 #
 106 #    always @(posedge clk or negedge rstn)
 107 #      begin: sequential
 108 #        if (rstn == 1'b0)
 109 #        begin
 110 #          pointer_out <= 0;
 111 #          pointer_in <= 0;
 112 #        end
 113 #        else
 114 #        begin
 115 #          // ------------------------------------
 116 #          // Check what to do with the input side
 117 #          // ------------------------------------
 118 #          // We have some input, increase by 1 the input pointer
 119 #          if (valid_in && !full)
 120 #          begin
 121 #            if (pointer_in == $unsigned(BUFFER_DEPTH - 1))
 122 #              pointer_in <= 0;
 123 #            else
 124 #              pointer_in <= pointer_in + 1;
 125 #          end
 126 #          // Else we don't have any input, the input pointer stays the same
 127 #
 128 #          // -------------------------------------
 129 #          // Check what to do with the output side
 130 #          // -------------------------------------
 131 #          // We had pushed one flit out, we can try to go for the next one
 132 #          if (ready_in && valid_out)
 133 #          begin
 134 #            if (pointer_out == $unsigned(BUFFER_DEPTH - 1))
 135 #              pointer_out <= 0;
 136 #            else
 137 #              pointer_out <= pointer_out + 1;
 138 #          end
 139 #          // Else stay on the same output location
 140 #        end
 141 #      end
 142 #
 143 #    // Update output ports
 144 #    assign data_out = buffer[pointer_out];
 145 #    assign valid_out = (elements != 0);
 146 #
 147 #    assign ready_out = ~full;
 148 #
 149 # endmodule
 150 #
 151 #