1 # Copyright (c) 2020 LambdaConcept <contact@lambdaconcept.com>
2 # Copyright (c) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2022 Raptor Engineering, LLC <support@raptorengineering.com>
5 # Based on code from LambaConcept, from the gram example which is BSD-2-License
6 # https://github.com/jeanthom/gram/tree/master/examples
8 # Modifications for the Libre-SOC Project funded by NLnet and NGI POINTER
9 # under EU Grants 871528 and 957073, under the LGPLv3+ License
11 from nmigen
import (Module
, Elaboratable
, DomainRenamer
, Record
,
12 Signal
, Cat
, Const
, ClockSignal
, ResetSignal
)
13 from nmigen
.build
.dsl
import Attrs
14 from nmigen
.cli
import verilog
15 from nmigen
.lib
.cdc
import ResetSynchronizer
16 from nmigen_soc
import wishbone
, memory
17 from nmigen_soc
.memory
import MemoryMap
18 from nmigen
.utils
import log2_int
20 from nmigen_stdio
.serial
import AsyncSerial
23 from nmigen_boards
.resources
.memory
import HyperRAMResource
24 from lambdasoc
.periph
.hyperram
import HyperRAM
, HyperRAMPads
, HyperRAMPHY
26 from lambdasoc
.periph
.intc
import GenericInterruptController
27 from lambdasoc
.periph
.sram
import SRAMPeripheral
28 from lambdasoc
.periph
.timer
import TimerPeripheral
29 from lambdasoc
.periph
import Peripheral
30 from lambdasoc
.soc
.base
import SoC
31 from soc
.bus
.uart_16550
import UART16550
# opencores 16550 uart
32 from soc
.bus
.tercel
import Tercel
# SPI XIP master
33 from soc
.bus
.opencores_ethmac
import EthMAC
# OpenCores 10/100 Ethernet MAC
34 from soc
.bus
.external_core
import ExternalCore
# external libresoc/microwatt
35 from soc
.bus
.wb_downconvert
import WishboneDownConvert
36 from soc
.bus
.syscon
import MicrowattSYSCON
39 from gram
.common
import (PhySettings
, get_cl_cw
, get_sys_latency
,
41 from gram
.core
import gramCore
42 from gram
.phy
.ecp5ddrphy
import ECP5DDRPHY
43 from gram
.phy
.fakephy
import FakePHY
, SDRAM_VERBOSE_STD
, SDRAM_VERBOSE_DBG
44 from gram
.modules
import MT41K256M16
, MT41K64M16
45 from gram
.frontend
.wishbone
import gramWishbone
48 from nmigen
.build
import Resource
49 from nmigen
.build
import Subsignal
50 from nmigen
.build
import Pins
52 # Board (and simulation) platforms
53 from nmigen_boards
.versa_ecp5
import VersaECP5Platform
54 from nmigen_boards
.versa_ecp5
import VersaECP5Platform85
# custom board
55 from nmigen_boards
.ulx3s
import ULX3S_85F_Platform
56 from nmigen_boards
.arty_a7
import ArtyA7_100Platform
57 from nmigen_boards
.test
.blinky
import Blinky
58 from icarusversa
import IcarusVersaPlatform
59 # Clock-Reset Generator (works for all ECP5 platforms)
60 from ecp5_crg
import ECP5CRG
61 from arty_crg
import ArtyA7CRG
66 def sim_ddr3_settings(clk_freq
=100e6
):
67 tck
= 2/(2*2*clk_freq
)
73 cl
, cwl
= get_cl_cw("DDR3", tck
)
74 cl_sys_latency
= get_sys_latency(nphases
, cl
)
75 cwl_sys_latency
= get_sys_latency(nphases
, cwl
)
76 rdcmdphase
, rdphase
= get_sys_phases(nphases
, cl_sys_latency
, cl
)
77 wrcmdphase
, wrphase
= get_sys_phases(nphases
, cwl_sys_latency
, cwl
)
82 dfi_databits
=4*databits
,
87 rdcmdphase
=rdcmdphase
,
88 wrcmdphase
=wrcmdphase
,
91 read_latency
=2 + cl_sys_latency
+ 2 + log2_int(4//nphases
) + 4,
92 write_latency
=cwl_sys_latency
96 class WB64to32Convert(Elaboratable
):
97 """Microwatt IO wishbone slave 64->32 bits converter
99 For timing reasons, this adds a one cycle latch on the way both
100 in and out. This relaxes timing and routing pressure on the "main"
101 memory bus by moving all simple IOs to a slower 32-bit bus.
103 This implementation is rather dumb at the moment, no stash buffer,
104 so we stall whenever that latch is busy. This can be improved.
106 def __init__(self
, master
, slave
):
110 def elaborate(self
, platform
):
112 comb
, sync
= m
.d
.comb
, m
.d
.sync
113 master
, slave
= self
.master
, self
.slave
120 with m
.State("IDLE"):
121 # Clear ACK (and has_top_r) in case it was set
122 sync
+= master
.ack
.eq(0)
123 sync
+= has_top_r
.eq(0)
125 # Do we have a cycle ?
126 with m
.If(master
.cyc
& master
.stb
):
127 # Stall master until we are done, we are't (yet) pipelining
128 # this, it's all slow IOs.
129 sync
+= master
.stall
.eq(1)
131 # Start cycle downstream
132 sync
+= slave
.cyc
.eq(1)
133 sync
+= slave
.stb
.eq(1)
135 # Do we have a top word and/or a bottom word ?
136 comb
+= has_top
.eq(master
.sel
[4:].bool())
137 comb
+= has_bot
.eq(master
.sel
[:4].bool())
138 # record the has_top flag for the next FSM state
139 sync
+= has_top_r
.eq(has_top
)
141 # Copy write enable to IO out, copy address as well,
142 # LSB is set later based on HI/LO
143 sync
+= slave
.we
.eq(master
.we
)
144 sync
+= slave
.adr
.eq(Cat(0, master
.adr
))
146 # If we have a bottom word, handle it first, otherwise
147 # send the top word down. XXX Split the actual mux out
148 # and only generate a control signal.
150 with m
.If(master
.we
):
151 sync
+= slave
.dat_w
.eq(master
.dat_w
[:32])
152 sync
+= slave
.sel
.eq(master
.sel
[:4])
154 # Wait for ack on BOTTOM half
155 m
.next
= "WAIT_ACK_BOT"
158 with m
.If(master
.we
):
159 sync
+= slave
.dat_w
.eq(master
.dat_w
[32:])
160 sync
+= slave
.sel
.eq(master
.sel
[4:])
162 # Bump LSB of address
163 sync
+= slave
.adr
[0].eq(1)
165 # Wait for ack on TOP half
166 m
.next
= "WAIT_ACK_TOP"
169 with m
.State("WAIT_ACK_BOT"):
170 # If we aren't stalled by the device, clear stb
171 if hasattr(slave
, "stall"):
172 with m
.If(~slave
.stall
):
173 sync
+= slave
.stb
.eq(0)
176 with m
.If(slave
.ack
):
177 # If it's a read, latch the data
178 with m
.If(~slave
.we
):
179 sync
+= master
.dat_r
[:32].eq(slave
.dat_r
)
181 # Do we have a "top" part as well ?
182 with m
.If(has_top_r
):
184 with m
.If(master
.we
):
185 sync
+= slave
.dat_w
.eq(master
.dat_w
[32:])
186 sync
+= slave
.sel
.eq(master
.sel
[4:])
188 # Bump address and set STB
189 sync
+= slave
.adr
[0].eq(1)
190 sync
+= slave
.stb
.eq(1)
193 m
.next
= "WAIT_ACK_TOP"
196 # We are done, ack up, clear cyc downstram
197 sync
+= slave
.cyc
.eq(0)
198 sync
+= slave
.stb
.eq(0)
200 # And ack & unstall upstream
201 sync
+= master
.ack
.eq(1)
202 if hasattr(master
, "stall"):
203 sync
+= master
.stall
.eq(0)
208 with m
.State("WAIT_ACK_TOP"):
209 # If we aren't stalled by the device, clear stb
210 if hasattr(slave
, "stall"):
211 with m
.If(~slave
.stall
):
212 sync
+= slave
.stb
.eq(0)
215 with m
.If(slave
.ack
):
216 # If it's a read, latch the data
217 with m
.If(~slave
.we
):
218 sync
+= master
.dat_r
[32:].eq(slave
.dat_r
)
220 # We are done, ack up, clear cyc downstram
221 sync
+= slave
.cyc
.eq(0)
222 sync
+= slave
.stb
.eq(0)
224 # And ack & unstall upstream
225 sync
+= master
.ack
.eq(1)
226 if hasattr(master
, "stall"):
227 sync
+= master
.stall
.eq(0)
235 class DDR3SoC(SoC
, Elaboratable
):
236 def __init__(self
, *,
239 uart_pins
, spi_0_pins
, ethmac_0_pins
,
240 ddr_pins
, ddrphy_addr
, dramcore_addr
, ddr_addr
,
243 spi0_addr
, spi0_cfg_addr
,
244 eth0_cfg_addr
, eth0_irqno
,
250 # wishbone routing is as follows:
261 # arbiter------------------------------------------+
263 # +---decoder----+--------+---------+-------+--------+ |
265 # uart XICS CSRs DRAM XIP SPI HyperRAM EthMAC
267 # set up wishbone bus arbiter and decoder. arbiter routes,
268 # decoder maps local-relative addressed satellites to global addresses
269 self
._arbiter
= wishbone
.Arbiter(addr_width
=30, data_width
=32,
271 features
={"cti", "bte", "stall"})
272 self
._decoder
= wishbone
.Decoder(addr_width
=30, data_width
=32,
274 features
={"cti", "bte", "stall"})
276 # default firmware name
278 firmware
= "firmware/main.bin"
280 # set up clock request generator
282 if fpga
in ['versa_ecp5', 'versa_ecp5_85', 'isim', 'ulx3s']:
285 self
.crg
= ECP5CRG(clk_freq
, pod_bits
)
286 if fpga
in ['arty_a7']:
287 self
.crg
= ArtyA7CRG(clk_freq
)
289 # set up CPU, with 64-to-32-bit downconverters
291 self
.cpu
= ExternalCore(name
="ext_core")
292 cvtdbus
= wishbone
.Interface(addr_width
=30, data_width
=32,
293 granularity
=8, features
={'stall'})
294 cvtibus
= wishbone
.Interface(addr_width
=30, data_width
=32,
295 granularity
=8, features
={'stall'})
296 self
.dbusdowncvt
= WB64to32Convert(self
.cpu
.dbus
, cvtdbus
)
297 self
.ibusdowncvt
= WB64to32Convert(self
.cpu
.ibus
, cvtibus
)
298 self
._arbiter
.add(cvtibus
) # I-Cache Master
299 self
._arbiter
.add(cvtdbus
) # D-Cache Master. TODO JTAG master
300 self
.cvtibus
= cvtibus
301 self
.cvtdbus
= cvtdbus
303 # CPU interrupt controller
304 self
.intc
= GenericInterruptController(width
=len(self
.cpu
.irq
))
306 # SRAM (but actually a ROM, for firmware)
307 if fw_addr
is not None:
308 print ("fw at address %x" % fw_addr
)
310 self
.bootmem
= SRAMPeripheral(size
=0x8000, data_width
=sram_width
,
312 if firmware
is not None:
313 with
open(firmware
, "rb") as f
:
314 words
= iter(lambda: f
.read(sram_width
// 8), b
'')
315 bios
= [int.from_bytes(w
, "little") for w
in words
]
316 self
.bootmem
.init
= bios
317 self
._decoder
.add(self
.bootmem
.bus
, addr
=fw_addr
) # ROM at fw_addr
319 # System Configuration info
320 # offset executable ELF payload at 6 megabyte offset (2<<20)
321 spi_offset
= 2<<20 if (spi_0_pins
is not None) else None
322 dram_offset
= ddr_addr
if (ddr_pins
is not None) else None
323 self
.syscon
= MicrowattSYSCON(sys_clk_freq
=clk_freq
,
324 has_uart
=(uart_pins
is not None),
325 spi_offset
=spi_offset
,
326 dram_addr
=dram_offset
)
327 self
._decoder
.add(self
.syscon
.bus
, addr
=0xc0000000) # at 0xc000_0000
330 # SRAM (read-writeable BRAM)
331 self
.ram
= SRAMPeripheral(size
=4096)
332 self
._decoder
.add(self
.ram
.bus
, addr
=0x8000000) # at 0x8000_0000
334 # UART at 0xC000_2000, convert 32-bit bus down to 8-bit in an odd way
335 if uart_pins
is not None:
336 # sigh actual UART in microwatt is 8-bit
337 self
.uart
= UART16550(data_width
=8, pins
=uart_pins
,
339 # but (see soc.vhdl) 8-bit regs are addressed at 32-bit locations
340 cvtuartbus
= wishbone
.Interface(addr_width
=5, data_width
=32,
343 umap
= MemoryMap(addr_width
=7, data_width
=8, name
="uart_map")
344 cvtuartbus
.memory_map
= umap
345 self
._decoder
.add(cvtuartbus
, addr
=0xc0002000) # 16550 UART addr
346 self
.cvtuartbus
= cvtuartbus
348 # SDRAM module using opencores sdr_ctrl
350 class MT48LC16M16(SDRModule):
356 technology_timings = _TechnologyTimings(tREFI=64e6/8192,
360 speedgrade_timings = {"default": _SpeedgradeTimings(tRP=20,
369 if ddr_pins
is not None: # or fpga == 'sim':
370 ddrmodule
= dram_cls(clk_freq
, "1:2") # match DDR3 ASIC P/N
373 drs
= DomainRenamer("dramsync")
376 self
.ddrphy
= FakePHY(module
=ddrmodule
,
377 settings
=sim_ddr3_settings(clk_freq
),
378 verbosity
=SDRAM_VERBOSE_DBG
,
381 self
.ddrphy
= drs(ECP5DDRPHY(ddr_pins
, sys_clk_freq
=clk_freq
))
382 self
._decoder
.add(self
.ddrphy
.bus
, addr
=ddrphy_addr
)
384 dramcore
= gramCore(phy
=self
.ddrphy
,
385 geom_settings
=ddrmodule
.geom_settings
,
386 timing_settings
=ddrmodule
.timing_settings
,
389 self
.dramcore
= dramcore
391 self
.dramcore
= drs(dramcore
)
392 self
._decoder
.add(self
.dramcore
.bus
, addr
=dramcore_addr
)
394 # map the DRAM onto Wishbone, XXX use stall but set classic below
395 # XXX WHEN ADDING ASYNCBRIDGE IT IS THE **BRIDGE** THAT MUST
396 # XXX HAVE THE STALL SIGNAL, AND THE **BRIDGE** THAT MUST HAVE
397 # XXX stall=stb&~ack APPLIED
398 drambone
= gramWishbone(dramcore
, features
={'stall'})
400 self
.drambone
= drambone
402 self
.drambone
= drs(drambone
)
403 # XXX ADD THE ASYNCBRIDGE NOT THE DRAMBONE.BUS, THEN
404 # XXX ADD DRAMBONE.BUS TO ASYNCBRIDGE
405 self
._decoder
.add(self
.drambone
.bus
, addr
=ddr_addr
)
407 # additional SRAM at address if DRAM is not also at 0x0
408 # (TODO, check Flash, and HyperRAM as well)
409 if ddr_pins
is None or ddr_addr
!= 0x0:
410 print ("SRAM 0x8000 at address 0x0")
412 self
.sram
= SRAMPeripheral(size
=0x8000,
413 data_width
=sram_width
,
415 self
._decoder
.add(self
.sram
.bus
, addr
=0x0) # RAM at 0x0
418 if spi_0_pins
is not None and fpga
in ['sim',
420 'rcs_arctic_tern_bmc_card',
424 # The Lattice ECP5 devices require special handling on the
425 # dedicated SPI clock line, which is shared with the internal
426 # SPI controller used for FPGA bitstream loading.
427 spi0_is_lattice_ecp5_clk
= False
428 if fpga
in ['versa_ecp5',
430 'rcs_arctic_tern_bmc_card',
432 spi0_is_lattice_ecp5_clk
= True
434 # Tercel contains two independent Wishbone regions, a
435 # configuration region and the direct API access region,
436 # Set the SPI 0 access region to 16MB, as the FPGA
437 # bitstream Flash device is unlikely to be larger than this.
438 # The main SPI Flash (SPI 1) should be set to at
439 # least 28 bits (256MB) to allow the use of large 4BA devices.
440 self
.spi0
= Tercel(data_width
=32, spi_region_addr_width
=24,
441 adr_offset
=spi0_addr
,
445 lattice_ecp5_usrmclk
=spi0_is_lattice_ecp5_clk
)
446 self
._decoder
.add(self
.spi0
.bus
, addr
=spi0_addr
)
447 self
._decoder
.add(self
.spi0
.cfg_bus
, addr
=spi0_cfg_addr
)
450 if ethmac_0_pins
is not None and fpga
in ['versa_ecp5',
453 # The OpenCores Ethernet MAC contains two independent Wishbone
454 # interfaces, a slave (configuration) interface and a master (DMA)
456 self
.eth0
= EthMAC(pins
=ethmac_0_pins
)
457 self
._arbiter
.add(self
.eth0
.master_bus
)
458 self
._decoder
.add(self
.eth0
.slave_bus
, addr
=eth0_cfg_addr
)
459 self
.intc
.add_irq(self
.eth0
.irq
, index
=eth0_irqno
)
461 # HyperRAM modules *plural*. Assumes using a Quad PMOD by Piotr
462 # Esden, sold by 1bitsquared, only doing one CS_N enable at the
464 if hyperram_pins
is not None:
465 self
.hyperram
= HyperRAM(io
=hyperram_pins
, phy_kls
=HyperRAMPHY
,
467 latency
=7) # Winbond W956D8MBYA
468 self
._decoder
.add(self
.hyperram
.bus
, addr
=hyperram_addr
)
470 self
.memory_map
= self
._decoder
.bus
.memory_map
472 self
.clk_freq
= clk_freq
475 def elaborate(self
, platform
):
479 # add the peripherals and clock-reset-generator
480 if platform
is not None and hasattr(self
, "crg"):
481 m
.submodules
.sysclk
= self
.crg
483 if hasattr(self
, "sram"):
484 m
.submodules
.sram
= self
.sram
485 if hasattr(self
, "bootmem"):
486 m
.submodules
.bootmem
= self
.bootmem
487 m
.submodules
.syscon
= self
.syscon
488 if hasattr(self
, "ram"):
489 m
.submodules
.ram
= self
.ram
490 if hasattr(self
, "uart"):
491 m
.submodules
.uart
= self
.uart
492 comb
+= self
.uart
.cts_i
.eq(1)
493 comb
+= self
.uart
.dsr_i
.eq(1)
494 comb
+= self
.uart
.ri_i
.eq(0)
495 comb
+= self
.uart
.dcd_i
.eq(1)
496 # sigh connect up the wishbone bus manually to deal with
497 # the mis-match on the data
498 uartbus
= self
.uart
.bus
499 comb
+= uartbus
.adr
.eq(self
.cvtuartbus
.adr
)
500 comb
+= uartbus
.stb
.eq(self
.cvtuartbus
.stb
)
501 comb
+= uartbus
.cyc
.eq(self
.cvtuartbus
.cyc
)
502 comb
+= uartbus
.sel
.eq(self
.cvtuartbus
.sel
)
503 comb
+= uartbus
.we
.eq(self
.cvtuartbus
.we
)
504 comb
+= uartbus
.dat_w
.eq(self
.cvtuartbus
.dat_w
) # drops 8..31
505 comb
+= self
.cvtuartbus
.dat_r
.eq(uartbus
.dat_r
) # drops 8..31
506 comb
+= self
.cvtuartbus
.ack
.eq(uartbus
.ack
)
507 # aaand with the WB4-pipeline-to-WB3-classic mismatch, sigh
508 comb
+= uartbus
.stall
.eq(uartbus
.cyc
& ~uartbus
.ack
)
509 comb
+= self
.cvtuartbus
.stall
.eq(uartbus
.stall
)
510 if hasattr(self
, "cpu"):
511 m
.submodules
.intc
= self
.intc
512 m
.submodules
.extcore
= self
.cpu
513 m
.submodules
.dbuscvt
= self
.dbusdowncvt
514 m
.submodules
.ibuscvt
= self
.ibusdowncvt
515 # create stall sigs, assume wishbone classic
516 #ibus, dbus = self.cvtibus, self.cvtdbus
517 #comb += ibus.stall.eq(ibus.stb & ~ibus.ack)
518 #comb += dbus.stall.eq(dbus.stb & ~dbus.ack)
520 m
.submodules
.arbiter
= self
._arbiter
521 m
.submodules
.decoder
= self
._decoder
522 if hasattr(self
, "ddrphy"):
523 m
.submodules
.ddrphy
= self
.ddrphy
524 m
.submodules
.dramcore
= self
.dramcore
525 m
.submodules
.drambone
= drambone
= self
.drambone
526 # grrr, same problem with drambone: not WB4-pipe compliant
527 # XXX TAKE THIS OUT, REPLACE WITH ASYNCBRIDGE HAVING
528 # XXX asyncbridge.bus.stall.eq(asyncbridge.bus.cyc & ...)
529 comb
+= drambone
.bus
.stall
.eq(drambone
.bus
.cyc
& ~drambone
.bus
.ack
)
531 # add hyperram module
532 if hasattr(self
, "hyperram"):
533 m
.submodules
.hyperram
= hyperram
= self
.hyperram
534 # grrr, same problem with hyperram: not WB4-pipe compliant
535 comb
+= hyperram
.bus
.stall
.eq(hyperram
.bus
.cyc
& ~hyperram
.bus
.ack
)
536 # set 3 top CSn lines to zero for now
537 if self
.fpga
== 'arty_a7':
538 comb
+= hyperram
.phy
.rst_n
.eq(ResetSignal())
540 # add blinky lights so we know FPGA is alive
541 if platform
is not None:
542 m
.submodules
.blinky
= Blinky()
544 # connect the arbiter (of wishbone masters)
545 # to the decoder (addressing wishbone slaves)
546 comb
+= self
._arbiter
.bus
.connect(self
._decoder
.bus
)
548 if hasattr(self
, "cpu"):
549 # wire up the CPU interrupts
550 comb
+= self
.cpu
.irq
.eq(self
.intc
.ip
)
555 # add uart16550 verilog source. assumes a directory
556 # structure where ls2 has been checked out in a common
558 # git clone https://github.com/freecores/uart16550
559 opencores_16550
= "../../uart16550/rtl/verilog"
560 pth
= os
.path
.split(__file__
)[0]
561 pth
= os
.path
.join(pth
, opencores_16550
)
562 fname
= os
.path
.abspath(pth
)
564 self
.uart
.add_verilog_source(fname
, platform
)
566 if hasattr(self
, "spi0"):
568 m
.submodules
.spi0
= spi
= self
.spi0
569 # gonna drive me nuts, this.
570 comb
+= spi
.bus
.stall
.eq(spi
.bus
.cyc
& ~spi
.bus
.ack
)
571 comb
+= spi
.cfg_bus
.stall
.eq(spi
.cfg_bus
.cyc
& ~spi
.cfg_bus
.ack
)
573 # add Tercel verilog source. assumes a directory structure where
574 # microwatt has been checked out in a common subdirectory with:
575 # git clone https://git.libre-soc.org/git/microwatt.git tercel-qspi
576 # git checkout 882ace781e4
577 raptor_tercel
= "../../tercel-qspi/tercel"
578 pth
= os
.path
.split(__file__
)[0]
579 pth
= os
.path
.join(pth
, raptor_tercel
)
580 fname
= os
.path
.abspath(pth
)
582 self
.spi0
.add_verilog_source(fname
, platform
)
584 if hasattr(self
, "eth0"):
585 # add ethernet submodule
586 m
.submodules
.eth0
= ethmac
= self
.eth0
588 # add EthMAC verilog source. assumes a directory
589 # structure where the opencores ethmac has been checked out
590 # in a common subdirectory as:
591 # git clone https://github.com/freecores/ethmac
592 opencores_ethmac
= "../../ethmac/rtl/verilog"
593 pth
= os
.path
.split(__file__
)[0]
594 pth
= os
.path
.join(pth
, opencores_ethmac
)
595 fname
= os
.path
.abspath(pth
)
597 self
.eth0
.add_verilog_source(fname
, platform
)
600 pth
= os
.path
.split(__file__
)[0]
601 pth
= os
.path
.join(pth
, '../external_core_top.v')
602 fname
= os
.path
.abspath(pth
)
603 with
open(fname
) as f
:
604 platform
.add_file(fname
, f
)
609 # puzzlingly the only IO ports needed are peripheral pins,
610 # and at the moment that's just UART tx/rx.
612 ports
+= [self
.uart
.tx_o
, self
.uart
.rx_i
]
613 if hasattr(self
, "hyperram"):
614 ports
+= list(self
.hyperram
.ports())
615 if hasattr(self
, "ddrphy"):
616 if hasattr(self
.ddrphy
, "pads"): # real PHY
617 ports
+= list(self
.ddrphy
.pads
.fields
.values())
618 else: # FakePHY, get at the dfii pads, stops deletion of nets
619 for phase
in self
.dramcore
.dfii
.master
.phases
:
620 print ("dfi master", phase
)
621 ports
+= list(phase
.fields
.values())
622 for phase
in self
.dramcore
.dfii
.slave
.phases
:
623 print ("dfi master", phase
)
624 ports
+= list(phase
.fields
.values())
625 for phase
in self
.dramcore
.dfii
._inti
.phases
:
626 print ("dfi master", phase
)
627 ports
+= list(phase
.fields
.values())
628 ports
+= [ClockSignal(), ResetSignal()]
631 def build_platform(fpga
, firmware
):
633 # create a platform selected from the toolchain.
634 platform_kls
= {'versa_ecp5': VersaECP5Platform
,
635 'versa_ecp5_85': VersaECP5Platform85
,
636 'ulx3s': ULX3S_85F_Platform
,
637 'arty_a7': ArtyA7_100Platform
,
638 'isim': IcarusVersaPlatform
,
641 toolchain
= {'arty_a7': "yosys_nextpnr",
642 'versa_ecp5': 'Trellis',
643 'versa_ecp5_85': 'Trellis',
648 dram_cls
= {'arty_a7': None,
649 'versa_ecp5': MT41K64M16
,
650 'versa_ecp5_85': MT41K64M16
,
651 #'versa_ecp5': MT41K256M16,
656 if platform_kls
is not None:
657 platform
= platform_kls(toolchain
=toolchain
)
658 if fpga
== 'versa_ecp5_85':
659 platform
.speed
= "7" # HACK. speed grade 7, sigh
663 print ("platform", fpga
, firmware
, platform
)
665 # set clock frequency
670 clk_freq
= 55e6
# below 50 mhz, stops DRAM being enabled
671 if fpga
== 'versa_ecp5':
672 clk_freq
= 55e6
# crank right down to test hyperram
673 if fpga
== 'versa_ecp5_85':
674 # 50MHz works. 100MHz works. 55MHz does NOT work.
675 # Stick with multiples of 50MHz...
677 if fpga
== 'arty_a7':
682 # select a firmware address
684 if firmware
is not None:
685 fw_addr
= 0xff00_0000 # firmware at HI address, now
687 print ("fpga", fpga
, "firmware", firmware
)
689 # get UART resource pins
690 if platform
is not None:
691 uart_pins
= platform
.request("uart", 0)
693 uart_pins
= Record([('tx', 1), ('rx', 1)], name
="uart_0")
695 # get DDR resource pins, disable if clock frequency is below 50 mhz for now
697 if (clk_freq
>= 50e6
and platform
is not None and
698 fpga
in ['versa_ecp5', 'versa_ecp5_85', 'arty_a7', 'isim']):
699 ddr_pins
= platform
.request("ddr3", 0,
700 dir={"dq":"-", "dqs":"-"},
701 xdr
={"rst": 1, "clk":4, "a":4,
703 "odt":4, "ras":4, "cas":4, "we":4,
706 # Get SPI resource pins
708 if platform
is not None and \
709 fpga
in ['versa_ecp5', 'versa_ecp5_85', 'isim']:
710 # Override here to get FlashResource out of the way and enable Tercel
711 # direct access to the SPI flash.
712 # each pin needs a separate direction control
715 Subsignal("dq0", Pins("W2", dir="io")),
716 Subsignal("dq1", Pins("V2", dir="io")),
717 Subsignal("dq2", Pins("Y2", dir="io")),
718 Subsignal("dq3", Pins("W1", dir="io")),
719 Subsignal("cs_n", Pins("R2", dir="o")),
720 Attrs(PULLMODE
="NONE", DRIVE
="4", IO_TYPE
="LVCMOS33"))
722 platform
.add_resources(spi_0_ios
)
723 spi_0_pins
= platform
.request("spi_0", 0, dir={"cs_n":"o"},
724 xdr
={"dq0":1, "dq1": 1,
728 if platform
is not None and \
730 # each pin needs a separate direction control
733 Subsignal("dq0", Pins("K17", dir="io")),
734 Subsignal("dq1", Pins("K18", dir="io")),
735 Subsignal("dq2", Pins("L14", dir="io")),
736 Subsignal("dq3", Pins("M14", dir="io")),
737 Subsignal("cs_n", Pins("L13", dir="o")),
738 Subsignal("clk", Pins("L16", dir="o")),
739 Attrs(PULLMODE
="NONE", DRIVE
="4", IO_TYPE
="LVCMOS33"))
741 platform
.add_resources(spi_0_ios
)
742 spi_0_pins
= platform
.request("spi_0", 0)
744 print ("spiflash pins", spi_0_pins
)
746 # Get Ethernet RMII resource pins
748 if False and platform
is not None and \
749 fpga
in ['versa_ecp5', 'versa_ecp5_85', 'isim']:
750 # Mainly on X3 connector, MDIO on X4 due to lack of pins
752 Resource("ethmac_0", 0,
753 Subsignal("mtx_clk", Pins("B19", dir="i")),
754 Subsignal("mtxd", Pins("B12 B9 E6 D6", dir="o")),
755 Subsignal("mtxen", Pins("E7", dir="o")),
756 Subsignal("mtxerr", Pins("D7", dir="o")),
757 Subsignal("mrx_clk", Pins("B11", dir="i")),
758 Subsignal("mrxd", Pins("B6 E9 D9 B8", dir="i")),
759 Subsignal("mrxdv", Pins("C8", dir="i")),
760 Subsignal("mrxerr", Pins("D8", dir="i")),
761 Subsignal("mcoll", Pins("E8", dir="i")),
762 Subsignal("mcrs", Pins("C7", dir="i")),
763 Subsignal("mdc", Pins("B18", dir="o")),
764 Subsignal("md", Pins("A18", dir="io")),
765 Attrs(PULLMODE
="NONE", DRIVE
="8", SLEWRATE
="FAST",
768 platform
.add_resources(ethmac_0_ios
)
769 ethmac_0_pins
= platform
.request("ethmac_0", 0,
770 dir={"mtx_clk":"i", "mtxd":"o",
772 "mtxerr":"o", "mrx_clk":"i",
774 "mrxdv":"i", "mrxerr":"i",
776 "mcrs":"i", "mdc":"o", "md":"io"},
777 xdr
={"mtx_clk": 0, "mtxd": 0,
779 "mtxerr": 0, "mrx_clk": 0,
781 "mrxdv": 0, "mrxerr": 0,
783 "mcrs": 0, "mdc": 0, "md": 0})
784 print ("ethmac pins", ethmac_0_pins
)
789 hyperram_pins
= HyperRAMPads()
790 elif fpga
in ['isim']:
791 hyperram_ios
= HyperRAMResource(0, cs_n
="B13",
792 dq
="E14 C10 B10 E12 D12 A9 D11 D14",
793 rwds
="C14", rst_n
="E13", ck_p
="D13",
794 attrs
=Attrs(IO_TYPE
="LVCMOS33"))
795 platform
.add_resources(hyperram_ios
)
796 hyperram_pins
= platform
.request("hyperram")
797 print ("isim a7 hyperram", hyperram_ios
)
798 # Digilent Arty A7-100t
799 elif platform
is not None and fpga
in ['arty_a7']:
800 hyperram_ios
= HyperRAMResource(0, cs_n
="V12 V14 U12 U14",
801 dq
="D4 D3 F4 F3 G2 H2 D2 E2",
802 rwds
="U13", rst_n
="T13", ck_p
="V10",
803 # ck_n="V11" - for later (DDR)
804 attrs
=Attrs(IOSTANDARD
="LVCMOS33"))
805 platform
.add_resources(hyperram_ios
)
806 hyperram_pins
= platform
.request("hyperram")
807 print ("arty a7 hyperram", hyperram_ios
)
809 elif False and platform
is not None and fpga
in \
810 ['versa_ecp5', 'versa_ecp5_85']:
811 hyperram_ios
= HyperRAMResource(0, cs_n
="B13",
812 dq
="E14 C10 B10 E12 D12 A9 D11 D14",
813 rwds
="C14", rst_n
="E13", ck_p
="D13",
814 attrs
=Attrs(IO_TYPE
="LVCMOS33"))
815 platform
.add_resources(hyperram_ios
)
816 hyperram_pins
= platform
.request("hyperram")
817 print ("versa ecp5 hyperram", hyperram_ios
)
818 print ("hyperram pins", hyperram_pins
)
821 soc
= DDR3SoC(fpga
=fpga
, dram_cls
=dram_cls
,
822 # check microwatt_soc.h for these
823 ddrphy_addr
=0xfff00000, # DRAM_INIT_BASE, PHY address
824 dramcore_addr
=0xc8000000, # DRAM_CTRL_BASE
825 ddr_addr
=0x00000000, # DRAM_BASE
826 spi0_addr
=0xf0000000, # SPI0_BASE
827 spi0_cfg_addr
=0xc0006000, # SPI0_CTRL_BASE
828 eth0_cfg_addr
=0xc0004000, # ETH0_CTRL_BASE (4k)
829 eth0_irqno
=0, # ETH0_IRQ number
830 hyperram_addr
=0xa0000000, # HYPERRAM_BASE
835 spi_0_pins
=spi_0_pins
,
836 ethmac_0_pins
=ethmac_0_pins
,
837 hyperram_pins
=hyperram_pins
,
842 if toolchain
== 'Trellis':
843 # add -abc9 option to yosys synth_ecp5
844 #os.environ['NMIGEN_synth_opts'] = '-abc9 -nowidelut'
845 #os.environ['NMIGEN_synth_opts'] = '-abc9'
846 os
.environ
['NMIGEN_synth_opts'] = '-nowidelut'
848 if platform
is not None:
849 # build and upload it
851 platform
.build(soc
, do_program
=False,
852 do_build
=True, build_dir
="build_simsoc")
854 platform
.build(soc
, do_program
=True)
856 # for now, generate verilog
857 vl
= verilog
.convert(soc
, ports
=soc
.ports())
858 with
open("ls2.v", "w") as f
:
862 # urrr this gets exec()d by the build process without arguments
863 # which screws up. use the arty_a7_ls2.py etc. with no arguments
864 if __name__
== '__main__':
867 if len(sys
.argv
) >= 2:
869 if len(sys
.argv
) >= 3:
870 firmware
= sys
.argv
[2]
871 build_platform(fpga
, firmware
)