1 // See LICENSE for license details.
2 package sifive.blocks.devices.i2c
5 import freechips.rocketchip.config.Field
6 import freechips.rocketchip.subsystem.BaseSubsystem
7 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
9 case object PeripheryI2CKey extends Field[Seq[I2CParams]]
11 trait HasPeripheryI2C { this: BaseSubsystem =>
12 val i2cParams = p(PeripheryI2CKey)
13 val i2c = i2cParams.zipWithIndex.map { case(params, i) =>
14 val name = Some(s"i2c_$i")
15 val i2c = LazyModule(new TLI2C(pbus.beatBytes, params)).suggestName(name)
16 pbus.toVariableWidthSlave(name) { i2c.node }
17 ibus.fromSync := i2c.intnode
22 trait HasPeripheryI2CBundle {
26 trait HasPeripheryI2CModuleImp extends LazyModuleImp with HasPeripheryI2CBundle {
27 val outer: HasPeripheryI2C
28 val i2c = IO(Vec(outer.i2cParams.size, new I2CPort))
30 (i2c zip outer.i2c).foreach { case (io, device) =>
31 io <> device.module.io.port