1 // See LICENSE for license details.
2 package sifive.blocks.devices.pwm
6 import diplomacy.{LazyModule,LazyMultiIOModuleImp}
7 import rocketchip.HasSystemNetworks
8 import uncore.tilelink2.TLFragmenter
9 import util.HeterogeneousBag
11 import sifive.blocks.devices.gpio._
13 class PWMPortIO(val c: PWMParams) extends Bundle {
14 val port = Vec(c.ncmp, Bool()).asOutput
15 override def cloneType: this.type = new PWMPortIO(c).asInstanceOf[this.type]
18 class PWMPinsIO(val c: PWMParams) extends Bundle {
19 val pwm = Vec(c.ncmp, new GPIOPin)
22 class PWMGPIOPort(val c: PWMParams) extends Module {
24 val pwm = new PWMPortIO(c).flip()
25 val pins = new PWMPinsIO(c)
28 GPIOOutputPinCtrl(io.pins.pwm, io.pwm.port.asUInt)
31 case object PeripheryPWMKey extends Field[Seq[PWMParams]]
33 trait HasPeripheryPWM extends HasSystemNetworks {
34 val pwmParams = p(PeripheryPWMKey)
35 val pwms = pwmParams map { params =>
36 val pwm = LazyModule(new TLPWM(peripheryBusBytes, params))
37 pwm.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
38 intBus.intnode := pwm.intnode
43 trait HasPeripheryPWMBundle {
44 val pwms: HeterogeneousBag[PWMPortIO]
46 def PWMtoGPIOPins(dummy: Int = 1): Seq[PWMGPIOPort] = pwms.map { p =>
47 val pin = Module(new PWMGPIOPort(p.c))
53 trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp with HasPeripheryPWMBundle {
54 val outer: HasPeripheryPWM
55 val pwms = IO(HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_))))
57 (pwms zip outer.pwms) foreach { case (io, device) =>
58 io.port := device.module.io.gpio