1 // See LICENSE for license details.
2 package sifive.blocks.devices.xilinxvc707pciex1
5 import diplomacy.LazyModule
6 import rocketchip.{TopNetwork,TopNetworkModule,TopNetworkBundle}
7 import uncore.tilelink2.TLWidthWidget
9 trait PeripheryXilinxVC707PCIeX1 extends TopNetwork {
11 val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1)
12 l2.node := xilinxvc707pcie.master
13 xilinxvc707pcie.slave := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
14 xilinxvc707pcie.control := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
15 intBus.intnode := xilinxvc707pcie.intnode
18 trait PeripheryXilinxVC707PCIeX1Bundle extends TopNetworkBundle {
19 val xilinxvc707pcie = new XilinxVC707PCIeX1IO
22 trait PeripheryXilinxVC707PCIeX1Module extends TopNetworkModule {
23 val outer: PeripheryXilinxVC707PCIeX1
24 val io: PeripheryXilinxVC707PCIeX1Bundle
26 io.xilinxvc707pcie <> outer.xilinxvc707pcie.module.io.port