sorting out div/mod routines, bug in simulator
[nmutil.git] / src / nmutil / byterev.py
1 from nmigen import Signal, Cat
2
3 # TODO: turn this into a module
4 def byte_reverse(m, name, data, length):
5 """byte_reverse: unlike nmigen word_select this takes a dynamic length
6
7 nmigen Signal.word_select may only take a fixed length. we need
8 bigendian byte-reverse, half-word reverse, word and dword reverse.
9 """
10 comb = m.d.comb
11 data_r = Signal.like(data, name=name)
12
13 if isinstance(length, int):
14 j = length
15 rev = []
16 for i in range(j):
17 dest = data_r.word_select(i, 8)
18 res.append(data.word_select(j-1-i, 8))
19 comb += data_r.eq(Cat(*rev))
20 return data_r
21
22 with m.Switch(length):
23 for j in [1,2,4,8]:
24 with m.Case(j):
25 rev = []
26 for i in range(j):
27 rev.append(data.word_select(j-1-i, 8))
28 comb += data_r.eq(Cat(*rev))
29 return data_r
30
31