1 from nmigen
.compat
.sim
import run_simulation
2 from nmigen
.cli
import verilog
, rtlil
3 from nmigen
import Signal
, Module
, Const
, Elaboratable
11 initial begin q=1'b0; q1=1'b1; end
15 {1'b0,1'b0}:begin q=q; q1=q1; end
16 {1'b0,1'b1}: begin q=1'b0; q1=1'b1; end
17 {1'b1,1'b0}:begin q=1'b1; q1=1'b0; end
18 {1'b1,1'b1}: begin q=~q; q1=~q1; end
24 def latchregister(m
, incoming
, outgoing
, settrue
, name
=None):
25 reg
= Signal
.like(incoming
, name
=name
) # make reg same as input. reset OK.
26 with m
.If(settrue
): # pass in some kind of expression/condition here
27 m
.d
.sync
+= reg
.eq(incoming
) # latch input into register
28 m
.d
.comb
+= outgoing
.eq(incoming
) # return input (combinatorial)
30 m
.d
.comb
+= outgoing
.eq(reg
) # return input (combinatorial)
32 def mkname(prefix
, suffix
):
35 return "%s_%s" % (prefix
, suffix
)
37 class SRLatch(Elaboratable
):
38 def __init__(self
, sync
=True, llen
=1, name
=None):
41 s_n
, r_n
= mkname("s", name
), mkname("r", name
)
42 q_n
, qn_n
= mkname("q", name
), mkname("qn", name
)
43 qlq_n
= mkname("qlq", name
)
44 self
.s
= Signal(llen
, name
=s_n
, reset
=0)
45 self
.r
= Signal(llen
, name
=r_n
, reset
=(1<<llen
)-1) # defaults to off
46 self
.q
= Signal(llen
, name
=q_n
, reset_less
=True)
47 self
.qn
= Signal(llen
, name
=qn_n
, reset_less
=True)
48 self
.qlq
= Signal(llen
, name
=qlq_n
, reset_less
=True)
50 def elaborate(self
, platform
):
52 q_int
= Signal(self
.llen
)
54 m
.d
.sync
+= q_int
.eq((q_int
& ~self
.r
) | self
.s
)
56 m
.d
.comb
+= self
.q
.eq(q_int
)
58 m
.d
.comb
+= self
.q
.eq((q_int
& ~self
.r
) | self
.s
)
59 m
.d
.comb
+= self
.qn
.eq(~self
.q
)
60 m
.d
.comb
+= self
.qlq
.eq(self
.q | q_int
) # useful output
65 return self
.s
, self
.r
, self
.q
, self
.qn
93 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
94 with
open("test_srlatch.il", "w") as f
:
97 run_simulation(dut
, sr_sim(dut
), vcd_name
='test_srlatch.vcd')
99 dut
= SRLatch(sync
=False, llen
=4)
100 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
101 with
open("test_srlatch_async.il", "w") as f
:
104 run_simulation(dut
, sr_sim(dut
), vcd_name
='test_srlatch_async.vcd')
106 if __name__
== '__main__':