src/nmutil/latch.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Signal, Module, Elaboratable
   4
   5 """ jk latch
   6
   7 module jk(q,q1,j,k,c);
   8 output q,q1;
   9 input j,k,c;
  10 reg q,q1;
  11 initial begin q=1'b0; q1=1'b1; end
  12 always @ (posedge c)
  13   begin
  14     case({j,k})
  15          {1'b0,1'b0}:begin q=q; q1=q1; end
  16          {1'b0,1'b1}: begin q=1'b0; q1=1'b1; end
  17          {1'b1,1'b0}:begin q=1'b1; q1=1'b0; end
  18          {1'b1,1'b1}: begin q=~q; q1=~q1; end
  19     endcase
  20    end
  21 endmodule
  22 """
  23
  24 def latchregister(m, incoming, outgoing, settrue):
  25     reg = Signal.like(incoming) # make register same as input. reset is OK.
  26     with m.If(settrue):
  27         m.d.sync += reg.eq(incoming)      # latch input into register
  28         m.d.comb += outgoing.eq(incoming) # return input (combinatorial)
  29     with m.Else():
  30         m.d.comb += outgoing.eq(reg) # return input (combinatorial)
  31
  32
  33 class SRLatch(Elaboratable):
  34     def __init__(self, sync=True):
  35         self.sync = sync
  36         self.s = Signal(reset=0)
  37         self.r = Signal(reset=1) # defaults to off
  38         self.q = Signal(reset_less=True)
  39         self.qn = Signal(reset_less=True)
  40         self.qlq = Signal(reset_less=True)
  41
  42     def elaborate(self, platform):
  43         m = Module()
  44         q_int = Signal()
  45
  46         m.d.sync += q_int.eq((q_int & ~self.r) | self.s)
  47         if self.sync:
  48             m.d.comb += self.q.eq(q_int)
  49         else:
  50             m.d.comb += self.q.eq((q_int & ~self.r) | self.s)
  51         m.d.comb += self.qn.eq(~self.q)
  52         m.d.comb += self.qlq.eq(self.q | q_int) # useful output
  53
  54         return m
  55
  56     def ports(self):
  57         return self.s, self.r, self.q, self.qn
  58
  59
  60 def sr_sim(dut):
  61     yield dut.s.eq(0)
  62     yield dut.r.eq(0)
  63     yield
  64     yield
  65     yield
  66     yield dut.s.eq(1)
  67     yield
  68     yield
  69     yield
  70     yield dut.s.eq(0)
  71     yield
  72     yield
  73     yield
  74     yield dut.r.eq(1)
  75     yield
  76     yield
  77     yield
  78     yield dut.r.eq(0)
  79     yield
  80     yield
  81     yield
  82
  83 def test_sr():
  84     dut = SRLatch()
  85     vl = rtlil.convert(dut, ports=dut.ports())
  86     with open("test_srlatch.il", "w") as f:
  87         f.write(vl)
  88
  89     run_simulation(dut, sr_sim(dut), vcd_name='test_srlatch.vcd')
  90
  91     dut = SRLatch(sync=False)
  92     vl = rtlil.convert(dut, ports=dut.ports())
  93     with open("test_srlatch_async.il", "w") as f:
  94         f.write(vl)
  95
  96     run_simulation(dut, sr_sim(dut), vcd_name='test_srlatch_async.vcd')
  97
  98 if __name__ == '__main__':
  99     test_sr()