src/nmutil/test/test_clz.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay
   3
   4 from nmutil.clz import CLZ
   5 import unittest
   6 import math
   7 import random
   8
   9
  10 class CLZTestCase(unittest.TestCase):
  11     def run_tst(self, inputs, width=8):
  12
  13         m = Module()
  14
  15         m.submodules.dut = dut = CLZ(width)
  16         sig_in = Signal.like(dut.sig_in)
  17         count = Signal.like(dut.lz)
  18
  19         m.d.comb += [
  20             dut.sig_in.eq(sig_in),
  21             count.eq(dut.lz)]
  22
  23         sim = Simulator(m)
  24
  25         def process():
  26             for i in inputs:
  27                 yield sig_in.eq(i)
  28                 yield Delay(1e-6)
  29         sim.add_process(process)
  30         with sim.write_vcd("clz.vcd", "clz.gtkw", traces=[
  31                 sig_in, count]):
  32             sim.run()
  33
  34     def test_selected(self):
  35         inputs = [0, 15, 10, 127]
  36         self.run_tst(iter(inputs), width=8)
  37
  38     def test_non_power_2(self):
  39         inputs = [0, 128, 512]
  40         self.run_tst(iter(inputs), width=11)
  41
  42
  43 if __name__ == "__main__":
  44     unittest.main()