src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py

   1 import unittest
   2 from copy import deepcopy
   3
   4 from nmutil.formaltest import FHDLTestCase
   5 from openpower.decoder.isa.caller import SVP64State
   6 from openpower.decoder.isa.test_caller import run_tst
   7 from openpower.decoder.selectable_int import SelectableInt
   8 from openpower.simulator.program import Program
   9 from openpower.insndb.asm import SVP64Asm
  10 from openpower.util import log
  11
  12 def cmpd(x, y):
  13     class CRfield:
  14         def __repr__(self):
  15             return "<lt %d gt %d eq %d>" % (self.lt, self.gt, self.eq)
  16         def __int__(self):
  17             return (CRf.lt<<3) | (CRf.gt<<2) | (CRf.eq<<1)
  18     CRf = CRfield()
  19     CRf.lt = x < y
  20     CRf.gt = x > y
  21     CRf.eq = x == y
  22     return CRf
  23
  24
  25 # example sv.cmpi/ff=lt 0, 1, *10, 5
  26 # see https://bugs.libre-soc.org/show_bug.cgi?id=1183#c3
  27 def sv_cmpi(gpr, CR, vl, ra, si):
  28     i = 0
  29     while i < vl:
  30         CR[i] = cmpd(gpr[ra + i], si)
  31         log("sv_cmpi test", i, gpr[ra + i], si, CR[i], CR[i].lt)
  32         if CR[i].lt:
  33             break
  34         i += 1
  35     return i # new VL
  36
  37
  38 # example sv.minmax/ff=lt 0, 1, *10, 5
  39 # see https://bugs.libre-soc.org/show_bug.cgi?id=676
  40 def sv_maxu(gpr, CR, vl, ra, rb, rt):
  41     i = 0
  42     while i < vl:
  43         CR[0] = cmpd(gpr[ra+i], gpr[rb])
  44         log("sv_maxss test", i, gpr[ra + i], gpr[rb], CR[0], int(CR[0]))
  45         gpr[rt] = gpr[ra+i] if CR[0].lt else gpr[rb]
  46         if not CR[0].gt:
  47             break
  48         i += 1
  49     return i # new VL
  50
  51
  52 class DDFFirstTestCase(FHDLTestCase):
  53
  54     def _check_regs(self, sim, expected):
  55         for i in range(32):
  56             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  57
  58     def test_sv_maxu_ddffirst_single_1(self):
  59         self.sv_maxu_ddffirst_single([1,2,3,4], 0)
  60
  61     def test_sv_maxu_ddffirst_single_1(self):
  62         self.sv_maxu_ddffirst_single([3,4,1,0], 2)
  63
  64     def test_sv_maxu_ddffirst_single_2(self):
  65         self.sv_maxu_ddffirst_single([2,9,8,0], 2)
  66
  67     def test_sv_maxu_ddffirst_single_3(self):
  68         self.sv_maxu_ddffirst_single([2,1,3,0], 99999)
  69
  70     def sv_maxu_ddffirst_single(self, ra, rb):
  71         lst = SVP64Asm(["sv.minmax./ff=le 4, *10, 4, 1" # scalar RB=RT
  72                         ])
  73         lst = list(lst)
  74
  75         # SVSTATE
  76         svstate = SVP64State()
  77         vl = len(ra)  # VL is length of array ra
  78         svstate.vl = vl  # VL
  79         svstate.maxvl = vl  # MAXVL
  80         print("SVSTATE", bin(svstate.asint()))
  81
  82         gprs = [0] * 32
  83         gprs[4] =  rb # (RT&RB) accumulator in r4
  84         for i, ra in enumerate(ra): # vector in ra starts at r10
  85             gprs[10+i] = ra
  86             log("maxu ddff", i, gprs[10+i])
  87
  88         cr_res = [0]*8
  89         res = deepcopy(gprs)
  90
  91         expected_vl = sv_maxu(res, cr_res, vl, 10, 4, 4)
  92         log("sv_maxu", expected_vl, cr_res)
  93
  94         with Program(lst, bigendian=False) as program:
  95             sim = self.run_tst_program(program, initial_regs=gprs,
  96                                        svstate=svstate)
  97             for i in range(4):
  98                 val = sim.gpr(i).value
  99                 res.append(val)
 100                 cr_res.append(0)
 101                 log("i", i, val)
 102             # confirm that the results are as expected
 103
 104             for i, v in enumerate(cr_res[:vl]):
 105                 crf = sim.crl[i].get_range().value
 106                 log("crf", i, res[i], bin(crf), bin(int(v)))
 107                 self.assertEqual(crf, int(v))
 108
 109             for i, v in enumerate(res):
 110                 self.assertEqual(v, res[i])
 111
 112             self.assertEqual(sim.svstate.vl, expected_vl)
 113             self.assertEqual(sim.svstate.maxvl, 4)
 114             self.assertEqual(sim.svstate.srcstep, 0)
 115             self.assertEqual(sim.svstate.dststep, 0)
 116
 117     def test_1(self):
 118         lst = SVP64Asm(["sv.cmpi/ff=lt 0, 1, *10, 5"
 119                         ])
 120         lst = list(lst)
 121
 122         # SVSTATE
 123         svstate = SVP64State()
 124         vl = 3  # VL
 125         svstate.vl = vl  # VL
 126         svstate.maxvl = vl  # MAXVL
 127         print("SVSTATE", bin(svstate.asint()))
 128
 129         gprs = [0] * 32
 130         gprs[10] = 7
 131         gprs[11] = 5
 132         gprs[12] = 12
 133
 134         res = []
 135         cr_res = [0]*8
 136
 137         newvl = sv_cmpi(gprs, cr_res, vl, 10, 5)
 138         log("sv_cmpi", newvl, cr_res)
 139
 140         with Program(lst, bigendian=False) as program:
 141             sim = self.run_tst_program(program, initial_regs=gprs,
 142                                        svstate=svstate)
 143             for i in range(4):
 144                 val = sim.gpr(i).value
 145                 res.append(val)
 146                 cr_res.append(0)
 147                 print("i", i, val)
 148             # confirm that the results are as expected
 149             expected = deepcopy(vec)
 150             expected_vl = 0
 151             for i in range(4):
 152                 # calculate expected result and expected CR field
 153                 result = vec[i] - gprs[8]
 154                 crf = ((result==0)<<1) | ((result > 0)<<2) | ((result < 0) << 3)
 155                 cr_res[i] = crf
 156                 if result <= 0:
 157                     break
 158                 # VLi=0 - test comes FIRST!
 159                 expected[i] = result
 160                 # only write out if successful
 161                 expected_vl += 1
 162
 163             for i, v in enumerate(cr_res):
 164                 crf = sim.crl[i].get_range().value
 165                 print ("crf", i, res[i], bin(crf), bin(v))
 166                 self.assertEqual(crf, v)
 167
 168             for i, v in enumerate(res):
 169                 self.assertEqual(v, expected[i])
 170
 171             self.assertEqual(sim.svstate.vl, expected_vl)
 172             self.assertEqual(sim.svstate.maxvl, 4)
 173             self.assertEqual(sim.svstate.srcstep, 0)
 174             self.assertEqual(sim.svstate.dststep, 0)
 175
 176     def test_sv_addi_ffirst_le(self):
 177         lst = SVP64Asm(["sv.subf./ff=le *0,8,*0"
 178                         ])
 179         lst = list(lst)
 180
 181         # SVSTATE
 182         svstate = SVP64State()
 183         svstate.vl = 4  # VL
 184         svstate.maxvl = 4  # MAXVL
 185         print("SVSTATE", bin(svstate.asint()))
 186
 187         gprs = [0] * 64
 188         gprs[8] = 3
 189         vec = [9, 8, 3, 4]
 190
 191         res = []
 192         cr_res = []
 193         # store GPRs
 194         for i, x in enumerate(vec):
 195             gprs[i] = x
 196
 197         with Program(lst, bigendian=False) as program:
 198             sim = self.run_tst_program(program, initial_regs=gprs,
 199                                        svstate=svstate)
 200             for i in range(4):
 201                 val = sim.gpr(i).value
 202                 res.append(val)
 203                 cr_res.append(0)
 204                 print("i", i, val)
 205             # confirm that the results are as expected
 206             expected = deepcopy(vec)
 207             expected_vl = 0
 208             for i in range(4):
 209                 # calculate expected result and expected CR field
 210                 result = vec[i] - gprs[8]
 211                 crf = ((result==0)<<1) | ((result > 0)<<2) | ((result < 0) << 3)
 212                 cr_res[i] = crf
 213                 if result <= 0:
 214                     break
 215                 # VLi=0 - test comes FIRST!
 216                 expected[i] = result
 217                 # only write out if successful
 218                 expected_vl += 1
 219
 220             for i, v in enumerate(cr_res):
 221                 crf = sim.crl[i].get_range().value
 222                 print ("crf", i, res[i], bin(crf), bin(v))
 223                 self.assertEqual(crf, v)
 224
 225             for i, v in enumerate(res):
 226                 self.assertEqual(v, expected[i])
 227
 228             self.assertEqual(sim.svstate.vl, expected_vl)
 229             self.assertEqual(sim.svstate.maxvl, 4)
 230             self.assertEqual(sim.svstate.srcstep, 0)
 231             self.assertEqual(sim.svstate.dststep, 0)
 232
 233     def test_sv_addi_ffirst(self):
 234         lst = SVP64Asm(["sv.subf./ff=eq *0,8,*0"
 235                         ])
 236         lst = list(lst)
 237
 238         # SVSTATE
 239         svstate = SVP64State()
 240         svstate.vl = 4  # VL
 241         svstate.maxvl = 4  # MAXVL
 242         print("SVSTATE", bin(svstate.asint()))
 243
 244         gprs = [0] * 64
 245         gprs[8] = 3
 246         vec = [9, 8, 3, 4]
 247
 248         res = []
 249         cr_res = []
 250         # store GPRs
 251         for i, x in enumerate(vec):
 252             gprs[i] = x
 253
 254         with Program(lst, bigendian=False) as program:
 255             sim = self.run_tst_program(program, initial_regs=gprs,
 256                                        svstate=svstate)
 257             for i in range(4):
 258                 val = sim.gpr(i).value
 259                 res.append(val)
 260                 cr_res.append(0)
 261                 print("i", i, val)
 262             # confirm that the results are as expected
 263             expected = deepcopy(vec)
 264             for i in range(4):
 265                 result = vec[i] - gprs[8]
 266                 crf = ((result==0)<<1) | ((result > 0)<<2) | ((result < 0) << 3)
 267                 cr_res[i] = crf
 268                 if result == 0:
 269                     break
 270                 # VLi=0 - test comes FIRST!
 271                 expected[i] = result
 272             for i, v in enumerate(cr_res):
 273                 crf = sim.crl[i].get_range().value
 274                 print ("crf", i, res[i], bin(crf), bin(v))
 275                 self.assertEqual(crf, v)
 276
 277             for i, v in enumerate(res):
 278                 self.assertEqual(v, expected[i])
 279
 280             self.assertEqual(sim.svstate.vl, 2)
 281             self.assertEqual(sim.svstate.maxvl, 4)
 282             self.assertEqual(sim.svstate.srcstep, 0)
 283             self.assertEqual(sim.svstate.dststep, 0)
 284
 285     def test_sv_addi_ffirst_rc1(self):
 286         lst = SVP64Asm(["sv.subf/ff=RC1 *0,8,*0"  # RC1 auto-sets EQ (and Rc=1)
 287                         ])
 288         lst = list(lst)
 289
 290         # SVSTATE
 291         svstate = SVP64State()
 292         svstate.vl = 4  # VL
 293         svstate.maxvl = 4  # MAXVL
 294         print("SVSTATE", bin(svstate.asint()))
 295
 296         gprs = [0] * 64
 297         gprs[8] = 3
 298         vec = [9, 8, 3, 4]
 299
 300         res = []
 301         # store GPRs
 302         for i, x in enumerate(vec):
 303             gprs[i] = x
 304
 305         with Program(lst, bigendian=False) as program:
 306             sim = self.run_tst_program(program, initial_regs=gprs,
 307                                        svstate=svstate)
 308             for i in range(4):
 309                 val = sim.gpr(i).value
 310                 res.append(val)
 311                 print("i", i, val)
 312             # confirm that the results are as expected
 313             expected = deepcopy(vec)
 314             for i in range(4):
 315                 result = expected[i] - gprs[8]
 316                 if result == 0:
 317                     break
 318                 # VLi=0 - test comes FIRST!
 319                 expected[i] = result
 320             for i, v in enumerate(res):
 321                 self.assertEqual(v, expected[i])
 322
 323             self.assertEqual(sim.svstate.vl, 2)
 324             self.assertEqual(sim.svstate.maxvl, 4)
 325             self.assertEqual(sim.svstate.srcstep, 0)
 326             self.assertEqual(sim.svstate.dststep, 0)
 327
 328     def test_sv_addi_ffirst_vli(self):
 329         """data-dependent fail-first with VLi=1, the test comes *after* write
 330         """
 331         lst = SVP64Asm(["sv.subf/ff=RC1/vli *0,8,*0"
 332                         ])
 333         lst = list(lst)
 334
 335         # SVSTATE
 336         svstate = SVP64State()
 337         svstate.vl = 4  # VL
 338         svstate.maxvl = 4  # MAXVL
 339         print("SVSTATE", bin(svstate.asint()))
 340
 341         gprs = [0] * 64
 342         gprs[8] = 3
 343         vec = [9, 8, 3, 4]
 344
 345         res = []
 346         # store GPRs
 347         for i, x in enumerate(vec):
 348             gprs[i] = x
 349
 350         with Program(lst, bigendian=False) as program:
 351             sim = self.run_tst_program(program, initial_regs=gprs,
 352                                        svstate=svstate)
 353             for i in range(4):
 354                 val = sim.gpr(i).value
 355                 res.append(val)
 356                 print("i", i, val)
 357             # confirm that the results are as expected
 358             expected = deepcopy(vec)
 359             for i in range(4):
 360                 # VLi=1 - test comes AFTER write!
 361                 expected[i] -= gprs[8]
 362                 if expected[i] == 0:
 363                     break
 364             for i, v in enumerate(res):
 365                 self.assertEqual(v, expected[i])
 366
 367             self.assertEqual(sim.svstate.vl, 3)
 368             self.assertEqual(sim.svstate.maxvl, 4)
 369             self.assertEqual(sim.svstate.srcstep, 0)
 370             self.assertEqual(sim.svstate.dststep, 0)
 371
 372     def run_tst_program(self, prog, initial_regs=None,
 373                         svstate=None,
 374                         initial_mem=None,
 375                         initial_fprs=None):
 376         if initial_regs is None:
 377             initial_regs = [0] * 32
 378         simulator = run_tst(prog, initial_regs, mem=initial_mem,
 379                             initial_fprs=initial_fprs,
 380                             svstate=svstate)
 381
 382         print("GPRs")
 383         simulator.gpr.dump()
 384         print("FPRs")
 385         simulator.fpr.dump()
 386
 387         return simulator
 388
 389
 390 if __name__ == "__main__":
 391     unittest.main()