src/openpower/sv/sv_analysis.py

   1 #!/usr/bin/env python2
   2 #
   3 # NOTE that this program is python2 compatible, please do not stop it
   4 # from working by adding syntax that prevents that.
   5 #
   6 # Initial version written by lkcl Oct 2020
   7 # This program analyses the Power 9 op codes and looks at in/out register uses
   8 # The results are displayed:
   9 #       https://libre-soc.org/openpower/opcode_regs_deduped/
  10 #
  11 # It finds .csv files in the directory isatables/
  12 # then goes through the categories and creates svp64 CSV augmentation
  13 # tables on a per-opcode basis
  14 #
  15 # NOTE: this program is effectively part of the Simple-V Specification.
  16 # it encapsulates the relationships of what can be SVP64-encoded and
  17 # holds all of the information on how to encode and decode SVP64.
  18 # By auto-generating tables that go into the Simple-V Specification
  19 # this program *is* the specification. do not be confused just because
  20 # it is in python: if you do not understand please ask questions and
  21 # help create patches with explanatory comments.
  22
  23 import argparse
  24 import csv
  25 import enum
  26 import os
  27 from os.path import dirname, join
  28 from glob import glob
  29 from collections import defaultdict
  30 from collections import OrderedDict
  31 from openpower.decoder.power_svp64 import SVP64RM
  32 from openpower.decoder.power_enums import find_wiki_file, get_csv
  33 from openpower.util import log
  34
  35
  36 # Ignore those containing: valid test sprs
  37 def glob_valid_csvs(root):
  38     def check_csv(fname):
  39         _, name = os.path.split(fname)
  40         if '-' in name:
  41             return False
  42         if 'valid' in fname:
  43             return False
  44         if 'test' in fname:
  45             return False
  46         if fname.endswith('insndb.csv'):
  47             return False
  48         if fname.endswith('sprs.csv'):
  49             return False
  50         if fname.endswith('minor_19_valid.csv'):
  51             return False
  52         if 'RM' in fname:
  53             return False
  54         return True
  55
  56     yield from filter(check_csv, glob(root))
  57
  58
  59 # Write an array of dictionaries to the CSV file name:
  60 def write_csv(name, items, headers):
  61     file_path = find_wiki_file(name)
  62     with open(file_path, 'w') as csvfile:
  63         writer = csv.DictWriter(csvfile, headers, lineterminator="\n")
  64         writer.writeheader()
  65         writer.writerows(items)
  66
  67 # This will return True if all values are true.
  68 # Not sure what this is about
  69
  70
  71 def blank_key(row):
  72     # for v in row.values():
  73     #    if 'SPR' in v: # skip all SPRs
  74     #        return True
  75     for v in row.values():
  76         if v:
  77             return False
  78     return True
  79
  80 # General purpose registers have names like: RA, RT, R1, ...
  81 # Floating point registers names like: FRT, FRA, FR1, ..., FRTp, ...
  82 # Return True if field is a register
  83
  84
  85 def isreg(field):
  86     return (field.startswith('R') or field.startswith('FR') or
  87             field == 'SPR')
  88
  89
  90 # These are the attributes of the instructions,
  91 # register names
  92 keycolumns = ['unit', 'in1', 'in2', 'in3', 'out', 'CR in', 'CR out',
  93               ]  # don't think we need these: 'ldst len', 'rc', 'lk']
  94
  95 tablecols = ['unit', 'in', 'outcnt', 'CR in', 'CR out', 'imm'
  96              ]  # don't think we need these: 'ldst len', 'rc', 'lk']
  97
  98
  99 def create_key(row):
 100     """ create an equivalent of a database key by which it is possible
 101     to easily categorise an instruction.  later this category is used
 102     to decide what kind of EXTRA encoding is to be done because the
 103     key contains the total number of input and output registers
 104     """
 105     res = OrderedDict()
 106     #print ("row", row)
 107     for key in keycolumns:
 108         # registers IN - special-case: count number of regs RA/RB/RC/RS
 109         if key in ['in1', 'in2', 'in3']:
 110             if 'in' not in res:
 111                 res['in'] = 0
 112             if row['unit'] == 'BRANCH':  # branches must not include Vector SPRs
 113                 continue
 114             if isreg(row[key]):
 115                 res['in'] += 1
 116
 117         # registers OUT
 118         if key == 'out':
 119             # If upd is 1 then increment the count of outputs
 120             if 'outcnt' not in res:
 121                 res['outcnt'] = 0
 122             if isreg(row[key]):
 123                 res['outcnt'] += 1
 124             if row['upd'] == '1':
 125                 res['outcnt'] += 1
 126
 127         # CRs (Condition Register) (CR0 .. CR7)
 128         if key.startswith('CR'):
 129             if row[key].startswith('NONE'):
 130                 res[key] = '0'
 131             else:
 132                 res[key] = '1'
 133             if row['comment'].startswith('cr'):
 134                 res['crop'] = '1'
 135         # unit
 136         if key == 'unit':
 137             if row[key] == 'LDST':  # we care about LDST units
 138                 res[key] = row[key]
 139             else:
 140                 res[key] = 'OTHER'
 141         # LDST len (LoadStore length)
 142         if key.startswith('ldst'):
 143             if row[key].startswith('NONE'):
 144                 res[key] = '0'
 145             else:
 146                 res[key] = '1'
 147         # rc, lk
 148         if key in ['rc', 'lk']:
 149             if row[key] == 'ONE':
 150                 res[key] = '1'
 151             elif row[key] == 'NONE':
 152                 res[key] = '0'
 153             else:
 154                 res[key] = 'R'
 155         if key == 'lk':
 156             res[key] = row[key]
 157
 158     # Convert the numerics 'in' & 'outcnt' to strings
 159     res['in'] = str(res['in'])
 160     res['outcnt'] = str(res['outcnt'])
 161
 162     # constants
 163     if row['in2'].startswith('CONST_'):
 164         res['imm'] = "1"  # row['in2'].split("_")[1]
 165     else:
 166         res['imm'] = ''
 167
 168     return res
 169
 170 #
 171
 172
 173 def dformat(d):
 174     res = []
 175     for k, v in d.items():
 176         res.append("%s: %s" % (k, v))
 177     return ' '.join(res)
 178
 179
 180 def tformat(d):
 181     return "| " + ' | '.join(d) + " |"
 182
 183
 184 def keyname(row):
 185     """converts a key into a readable string. anything null or zero
 186     is skipped, shortening the readable string
 187     """
 188     res = []
 189     if row['unit'] != 'OTHER':
 190         res.append(row['unit'])
 191     if row['in'] != '0':
 192         res.append('%sR' % row['in'])
 193     if row['outcnt'] != '0':
 194         res.append('%sW' % row['outcnt'])
 195     if row['CR in'] == '1' and row['CR out'] == '1':
 196         if 'crop' in row:
 197             res.append("CR=2R1W")
 198         else:
 199             res.append("CRio")
 200     elif row['CR in'] == '1':
 201         res.append("CRi")
 202     elif row['CR out'] == '1':
 203         res.append("CRo")
 204     elif 'imm' in row and row['imm']:
 205         res.append("imm")
 206     return '-'.join(res)
 207
 208
 209 class Format(enum.Enum):
 210     BINUTILS = enum.auto()
 211     VHDL = enum.auto()
 212
 213     @classmethod
 214     def _missing_(cls, value):
 215         return {
 216             "binutils": Format.BINUTILS,
 217             "vhdl": Format.VHDL,
 218         }[value.lower()]
 219
 220     def __str__(self):
 221         return self.name.lower()
 222
 223     def declarations(self, values, lens):
 224         def declaration_binutils(value, width):
 225             yield "/* TODO: implement binutils declaration " \
 226                   "(value=%x, width=%x) */" % (value, width)
 227
 228         def declaration_vhdl(value, width):
 229             yield "    type sv_%s_rom_array_t is " \
 230                 "array(0 to %d) of sv_decode_rom_t;" % (value, width)
 231
 232         for value in values:
 233             if value not in lens:
 234                 todo = ["TODO %s (or no SVP64 augmentation)" % value]
 235                 todo = self.wrap_comment(todo)
 236                 yield from map(lambda line: f"    {line}", todo)
 237             else:
 238                 width = lens[value]
 239                 yield from {
 240                     Format.BINUTILS: declaration_binutils,
 241                     Format.VHDL: declaration_vhdl,
 242                 }[self](value, width)
 243
 244     def definitions(self, entries_svp64, fullcols):
 245         def definitions_vhdl():
 246             for (value, entries) in entries_svp64.items():
 247                 yield ""
 248                 yield "    constant sv_%s_decode_rom_array :" % value
 249                 yield "             sv_%s_rom_array_t := (" % value
 250                 yield "        -- %s" % '  '.join(fullcols)
 251
 252                 for (op, insn, row) in entries:
 253                     yield f"    {op:>13} => ({', '.join(row)}), -- {insn}"
 254
 255                 yield f"    {'others':>13} => sv_illegal_inst"
 256                 yield "    );"
 257                 yield ""
 258
 259         def definitions_binutils():
 260             yield f"/* TODO: implement binutils definitions */"
 261
 262         yield from {
 263             Format.BINUTILS: definitions_binutils,
 264             Format.VHDL: definitions_vhdl,
 265         }[self]()
 266
 267     def wrap_comment(self, lines):
 268         def wrap_comment_binutils(lines):
 269             lines = tuple(lines)
 270             if len(lines) == 1:
 271                 yield "/* %s */" % lines[0]
 272             else:
 273                 yield "/*"
 274                 yield from map(lambda line: " * %s" % line, lines)
 275                 yield " */"
 276
 277         def wrap_comment_vhdl(lines):
 278             yield from map(lambda line: "-- %s" % line, lines)
 279
 280         yield from {
 281             Format.BINUTILS: wrap_comment_binutils,
 282             Format.VHDL: wrap_comment_vhdl,
 283         }[self](lines)
 284
 285
 286 def read_csvs():
 287     csvs = {}
 288     csvs_svp64 = {}
 289     bykey = {}
 290     primarykeys = set()
 291     dictkeys = OrderedDict()
 292     immediates = {}
 293     insns = {}  # dictionary of CSV row, by instruction
 294     insn_to_csv = {}
 295
 296     # Expand that (all .csv files)
 297     pth = find_wiki_file("*.csv")
 298
 299     # Ignore those containing: valid test sprs
 300     for fname in glob_valid_csvs(pth):
 301         csvname = os.path.split(fname)[1]
 302         csvname_ = csvname.split(".")[0]
 303         # csvname is something like: minor_59.csv, fname the whole path
 304         csv = get_csv(fname)
 305         csvs[fname] = csv
 306         csvs_svp64[csvname_] = []
 307         for row in csv:
 308             if blank_key(row):
 309                 continue
 310             #print("row", row)
 311             insn_name = row['comment']
 312             condition = row['CONDITIONS']
 313             # skip instructions that are not suitable
 314             if insn_name.startswith("l") and insn_name.endswith("br"):
 315                 continue  # skip pseudo-alias lxxxbr
 316             if insn_name in ['mcrxr', 'mcrxrx', 'darn']:
 317                 continue
 318             if insn_name in ['bctar', 'bcctr']:  # for now. TODO
 319                 continue
 320             if 'rfid' in insn_name:
 321                 continue
 322             if 'addpcis' in insn_name:  # skip for now
 323                 continue
 324
 325             # sv.bc is being classified as 2P-2S-1D by mistake due to SPRs
 326             if insn_name.startswith('bc'):
 327                 # whoops: remove out reg (SPRs CTR etc)
 328                 row['in1'] = 'NONE'
 329                 row['in2'] = 'NONE'
 330                 row['in3'] = 'NONE'
 331                 row['out'] = 'NONE'
 332
 333             insns[(insn_name, condition)] = row  # accumulate csv data
 334             insn_to_csv[insn_name] = csvname_  # CSV file name by instruction
 335             dkey = create_key(row)
 336             key = tuple(dkey.values())
 337             #print("key=", key, dkey)
 338             dictkeys[key] = dkey
 339             primarykeys.add(key)
 340             if key not in bykey:
 341                 bykey[key] = []
 342             bykey[key].append((csvname, row['opcode'], insn_name, condition,
 343                                row['form'].upper() + '-Form'))
 344
 345             # detect immediates, collate them (useful info)
 346             if row['in2'].startswith('CONST_'):
 347                 imm = row['in2'].split("_")[1]
 348                 if key not in immediates:
 349                     immediates[key] = set()
 350                 immediates[key].add(imm)
 351
 352     primarykeys = list(primarykeys)
 353     primarykeys.sort()
 354
 355     return (csvs, csvs_svp64, primarykeys, bykey, insn_to_csv, insns,
 356             dictkeys, immediates)
 357
 358
 359 def regs_profile(insn, res):
 360     """get a more detailed register profile: 1st operand is RA,
 361     2nd is RB, etc. etc
 362     """
 363     regs = []
 364     for k in ['in1', 'in2', 'in3', 'out', 'CR in', 'CR out']:
 365         if insn[k].startswith('CONST'):
 366             res[k] = ''
 367             regs.append('')
 368         else:
 369             res[k] = insn[k]
 370             if insn[k] == 'RA_OR_ZERO':
 371                 regs.append('RA')
 372             elif insn[k] != 'NONE':
 373                 regs.append(insn[k])
 374             else:
 375                 regs.append('')
 376     return regs
 377
 378
 379 def extra_classifier(insn_name, value, name, res, regs):
 380     """extra_classifier: creates the SVP64.RM EXTRA2/3 classification.
 381     there is very little space (9 bits) to mark register operands
 382     (RT RA RB, BA BB, BFA, FRS etc.) with the "extra" information
 383     needed to tell if *EACH* operand (of which there can be up to five!)
 384     is Vectorised, and whether its numbering is extended into the
 385     0..127 range rather than the limited 3/5 bit of Scalar v3.0 Power ISA.
 386
 387     thus begins the rather tedious but by-rote examination of EVERY
 388     Scalar instruction, working out how best to tell a decoder how to
 389     extend the registers.  EXTRA2 can have up to 4 slots (of 2 bit each)
 390     where due to RM.EXTRA being 9 bits, EXTRA3 can have up to 3 slots
 391     (of 3 bit each).  the index REGNAME says which slot the register
 392     named REGNAME must read its decoding from.  d: means destination,
 393     s: means source.  some are *shared slots* especially LDST update.
 394     some Rc=1 ops have the CR0/CR1 as a co-result which is also
 395     obviously Vectorised if the result is Vectorised.
 396
 397     it is actually quite straightforward but the sheer quantity of
 398     Scalar Power ISA instructions made it prudent to do this in an
 399     intelligent way, almost by-rote, by analysing the register profiles.
 400     """
 401     # for LD/ST FP, use FRT/FRS not RT/RS, and use CR1 not CR0
 402     if insn_name.startswith("lf"):
 403         dRT = 'd:FRT'
 404         dCR = 'd:CR1'
 405     else:
 406         dRT = 'd:RT'
 407         dCR = 'd:CR0'
 408     if insn_name.startswith("stf"):
 409         sRS = 's:FRS'
 410         dCR = 'd:CR1'
 411     else:
 412         sRS = 's:RS'
 413         dCR = 'd:CR0'
 414
 415     # sigh now the fun begins.  this isn't the sanest way to do it
 416     # but the patterns are pretty regular.  we start with the "profile"
 417     # because that determines how much space is available (total num
 418     # regs to decode) then if necessary begin apecialising either
 419     # by the instruction name or through more detailed register
 420     # profiling. example:
 421     #     if regs == ['RA', '', '', 'RT', '', '']:
 422     # is in the order in1  in2  in3 out1 out2 Rc=1
 423
 424     # ********
 425     # start with LD/ST
 426
 427     if value == 'LDSTRM-2P-1S1D':
 428         res['Etype'] = 'EXTRA3'  # RM EXTRA3 type
 429         res['0'] = dRT    # RT: Rdest_EXTRA3
 430         res['1'] = 's:RA'  # RA: Rsrc1_EXTRA3
 431
 432     elif value == 'LDSTRM-2P-1S2D':
 433         res['Etype'] = 'EXTRA3'  # RM EXTRA2 type
 434         res['0'] = dRT          # RT: Rdest_EXTRA3
 435         res['1'] = 'd:RA;s:RA'  # RA: Rdest2_EXTRA3
 436
 437     elif value == 'LDSTRM-2P-2S':
 438         # stw, std, sth, stb
 439         res['Etype'] = 'EXTRA3'  # RM EXTRA3 type
 440         res['0'] = sRS    # RS: Rdest1_EXTRA3
 441         res['1'] = 's:RA'  # RA: Rsrc1_EXTRA3
 442
 443     elif value == 'LDSTRM-2P-2S1D':
 444         if 'st' in insn_name and 'x' not in insn_name:  # stwu/stbu etc
 445             res['Etype'] = 'EXTRA3'  # RM EXTRA2 type
 446             res['0'] = 'd:RA;s:RA'  # RA: Rdest_EXTRA3 /  Rsrc_EXTRA3
 447             res['1'] = sRS    # RS: Rdsrc1_EXTRA3
 448         elif 'st' in insn_name and 'x' in insn_name:  # stwux
 449             res['Etype'] = 'EXTRA3'  # RM EXTRA2 type
 450             # RS: Rdest2_EXTRA2, RA: Rsrc1_EXTRA2 / Rdest
 451             res['0'] = "%s;s:RA;d:RA" % (sRS)
 452             res['1'] = 's:RB'  # RB: Rsrc2_EXTRA2
 453         elif 'u' in insn_name:  # ldux etc.
 454             res['Etype'] = 'EXTRA2'  # RM EXTRA2 type
 455             res['0'] = dRT    # RT: Rdest1_EXTRA2
 456             res['1'] = 's:RA;d:RA'  # RA: Rdest2_EXTRA2
 457             res['2'] = 's:RB'  # RB: Rsrc1_EXTRA2
 458         else:
 459             res['Etype'] = 'EXTRA2'  # RM EXTRA2 type
 460             res['0'] = dRT     # RT: Rdest1_EXTRA2
 461             res['1'] = 's:RA'  # RA: Rsrc1_EXTRA2
 462             res['2'] = 's:RB'  # RB: Rsrc2_EXTRA2
 463
 464     elif value == 'LDSTRM-2P-3S':
 465         res['Etype'] = 'EXTRA2'  # RM EXTRA2 type
 466         if 'cx' in insn_name:
 467             res['0'] = "%s;%s" % (sRS, dCR)  # RS: Rsrc1_EXTRA2 CR0: dest
 468         else:
 469             res['0'] = sRS  # RS: Rsrc1_EXTRA2
 470         res['1'] = 's:RA'  # RA: Rsrc2_EXTRA2
 471         res['2'] = 's:RB'  # RA: Rsrc3_EXTRA2
 472
 473     # **********
 474     # now begins,arithmetic
 475
 476     elif value == 'RM-2P-1S1D':
 477         res['Etype'] = 'EXTRA3'  # RM EXTRA3 type
 478         if insn_name == 'mtspr':
 479             res['0'] = 'd:SPR'  # SPR: Rdest1_EXTRA3
 480             res['1'] = 's:RS'  # RS: Rsrc1_EXTRA3
 481         elif insn_name == 'rlwinm':
 482             # weird one, RA is a dest but not in bits 6:10
 483             res['0'] = 'd:RA;d:CR0'  # RA: Rdest1_EXTRA3
 484             res['1'] = 's:RS'  # RS: Rsrc1_EXTRA3
 485         elif insn_name == 'mfspr':
 486             res['0'] = 'd:RS'  # RS: Rdest1_EXTRA3
 487             res['1'] = 's:SPR'  # SPR: Rsrc1_EXTRA3
 488         elif name == 'CRio' and insn_name == 'mcrf':
 489             res['0'] = 'd:BF'  # BFA: Rdest1_EXTRA3
 490             res['1'] = 's:BFA'  # BFA: Rsrc1_EXTRA3
 491         elif 'mfcr' in insn_name or 'mfocrf' in insn_name:
 492             res['0'] = 'd:RT'  # RT: Rdest1_EXTRA3
 493             res['1'] = 's:CR'  # CR: Rsrc1_EXTRA3
 494         elif regs == ['', '', '', 'RT', 'BI', '']:
 495             res['0'] = 'd:RT'  # RT: Rdest1_EXTRA3
 496             res['1'] = 's:BI'  # BI: Rsrc1_EXTRA3
 497         elif insn_name == 'setb':
 498             res['0'] = 'd:RT'  # RT: Rdest1_EXTRA3
 499             res['1'] = 's:BFA'  # BFA: Rsrc1_EXTRA3
 500         elif insn_name.startswith('cmp'):  # cmpi
 501             res['0'] = 'd:BF'  # BF: Rdest1_EXTRA3
 502             res['1'] = 's:RA'  # RA: Rsrc1_EXTRA3
 503         elif regs == ['RA', '', '', 'RT', '', '']:
 504             res['0'] = 'd:RT'  # RT: Rdest1_EXTRA3
 505             res['1'] = 's:RA'  # RA: Rsrc1_EXTRA3
 506         elif regs == ['RA', '', '', 'RT', '', 'CR0']:
 507             res['0'] = 'd:RT;d:CR0'  # RT,CR0: Rdest1_EXTRA3
 508             res['1'] = 's:RA'  # RA: Rsrc1_EXTRA3
 509         elif (regs == ['RS', '', '', 'RA', '', 'CR0'] or
 510               regs == ['', '', 'RS', 'RA', '', 'CR0']):
 511             res['0'] = 'd:RA;d:CR0'  # RA,CR0: Rdest1_EXTRA3
 512             res['1'] = 's:RS'  # RS: Rsrc1_EXTRA3
 513         elif regs == ['RS', '', '', 'RA', '', '']:
 514             res['0'] = 'd:RA'  # RA: Rdest1_EXTRA3
 515             res['1'] = 's:RS'  # RS: Rsrc1_EXTRA3
 516         elif regs == ['', 'FRB', '', 'FRT', '0', 'CR1']:
 517             res['0'] = 'd:FRT;d:CR1'  # FRT,CR1: Rdest1_EXTRA3
 518             res['1'] = 's:FRA'  # FRA: Rsrc1_EXTRA3
 519         elif regs == ['', 'FRB', '', '', '', 'CR1']:
 520             res['0'] = 'd:CR1'  # CR1: Rdest1_EXTRA3
 521             res['1'] = 's:FRB'  # FRA: Rsrc1_EXTRA3
 522         elif regs == ['', 'FRB', '', '', '', 'BF']:
 523             res['0'] = 'd:BF'  # BF: Rdest1_EXTRA3
 524             res['1'] = 's:FRB'  # FRA: Rsrc1_EXTRA3
 525         elif regs == ['', 'FRB', '', 'FRT', '', 'CR1']:
 526             res['0'] = 'd:FRT;d:CR1'  # FRT,CR1: Rdest1_EXTRA3
 527             res['1'] = 's:FRB'  # FRB: Rsrc1_EXTRA3
 528         elif regs == ['', 'RB', '', 'FRT', '', 'CR1']:
 529             res['0'] = 'd:FRT;d:CR1'  # FRT,CR1: Rdest1_EXTRA3
 530             res['1'] = 's:RB'  # RB: Rsrc1_EXTRA3
 531         elif regs == ['', 'RB', '', 'FRT', '', '']:
 532             res['0'] = 'd:FRT'  # FRT: Rdest1_EXTRA3
 533             res['1'] = 's:RB'  # RB: Rsrc1_EXTRA3
 534         elif regs == ['', 'FRB', '', 'RT', '', 'CR0']:
 535             res['0'] = 'd:RT;d:CR0'  # RT,CR0: Rdest1_EXTRA3
 536             res['1'] = 's:FRB'  # FRB: Rsrc1_EXTRA3
 537         elif insn_name == 'fishmv':
 538             # an overwrite instruction
 539             res['0'] = 'd:FRS'  # FRS: Rdest1_EXTRA3
 540             res['1'] = 's:FRS'  # FRS: Rsrc1_EXTRA3
 541         elif insn_name == 'setvl':
 542             res['0'] = 'd:RT'  # RT: Rdest1_EXTRA3
 543             res['1'] = 's:RA'  # RS: Rsrc1_EXTRA3
 544         else:
 545             raise NotImplementedError(insn_name)
 546
 547     elif value == 'RM-1P-2S1D':
 548         res['Etype'] = 'EXTRA3'  # RM EXTRA3 type
 549         if insn_name in ['crbinlog', 'crternlogi']:
 550             res['0'] = 'd:BF'  # BF: Rdest1_EXTRA3
 551             res['1'] = 's:BFA'  # BFA: Rsrc1_EXTRA3
 552             res['2'] = 's:BFB'  # BFB: Rsrc2_EXTRA3
 553         elif insn_name.startswith('cr'):
 554             res['0'] = 'd:BT'  # BT: Rdest1_EXTRA3
 555             res['1'] = 's:BA'  # BA: Rsrc1_EXTRA3
 556             res['2'] = 's:BB'  # BB: Rsrc2_EXTRA3
 557         elif regs == ['FRA', '', 'FRC', 'FRT', '', 'CR1']:
 558             res['0'] = 'd:FRT;d:CR1'  # FRT,CR1: Rdest1_EXTRA3
 559             res['1'] = 's:FRA'  # FRA: Rsrc1_EXTRA3
 560             res['2'] = 's:FRC'  # FRC: Rsrc1_EXTRA3
 561         # should be for fcmp
 562         elif regs == ['FRA', 'FRB', '', '', '', 'BF']:
 563             res['0'] = 'd:BF'  # BF: Rdest1_EXTRA3
 564             res['1'] = 's:FRA'  # FRA: Rsrc1_EXTRA3
 565             res['2'] = 's:FRB'  # FRB: Rsrc1_EXTRA3
 566         elif regs == ['FRA', 'FRB', '', 'FRT', '', '']:
 567             res['0'] = 'd:FRT'  # FRT: Rdest1_EXTRA3
 568             res['1'] = 's:FRA'  # FRA: Rsrc1_EXTRA3
 569             res['2'] = 's:FRB'  # FRB: Rsrc1_EXTRA3
 570         elif regs == ['FRA', 'FRB', '', 'FRT', '', 'CR1']:
 571             res['0'] = 'd:FRT;d:CR1'  # FRT,CR1: Rdest1_EXTRA3
 572             res['1'] = 's:FRA'  # FRA: Rsrc1_EXTRA3
 573             res['2'] = 's:FRB'  # FRB: Rsrc1_EXTRA3
 574         elif regs == ['FRA', 'RB', '', 'FRT', '', 'CR1']:
 575             res['0'] = 'd:FRT;d:CR1'  # FRT,CR1: Rdest1_EXTRA3
 576             res['1'] = 's:FRA'  # FRA: Rsrc1_EXTRA3
 577             res['2'] = 's:RB'  # RB: Rsrc1_EXTRA3
 578         elif regs == ['RS', 'RB', '', 'RA', '', '']:
 579             res['0'] = 'd:RA'  # RA: Rdest1_EXTRA3
 580             res['1'] = 's:RS'  # RS: Rsrc1_EXTRA3
 581             res['2'] = 's:RB'  # RB: Rsrc1_EXTRA3
 582         elif name == '2R-1W' or insn_name == 'cmpb':  # cmpb
 583             if insn_name in ['bpermd', 'cmpb']:
 584                 res['0'] = 'd:RA'  # RA: Rdest1_EXTRA3
 585                 res['1'] = 's:RS'  # RS: Rsrc1_EXTRA3
 586             else:
 587                 res['0'] = 'd:RT'  # RT: Rdest1_EXTRA3
 588                 res['1'] = 's:RA'  # RA: Rsrc1_EXTRA3
 589             res['2'] = 's:RB'  # RB: Rsrc1_EXTRA3
 590         elif insn_name.startswith('cmp'):  # cmp
 591             res['0'] = 'd:BF'  # BF: Rdest1_EXTRA3
 592             res['1'] = 's:RA'  # RA: Rsrc1_EXTRA3
 593             res['2'] = 's:RB'  # RB: Rsrc1_EXTRA3
 594         elif (regs == ['', 'RB', 'RS', 'RA', '', 'CR0'] or
 595               regs == ['RS', 'RB', '', 'RA', '', 'CR0']):
 596             res['0'] = 'd:RA;d:CR0'  # RA,CR0: Rdest1_EXTRA3
 597             res['1'] = 's:RB'  # RB: Rsrc1_EXTRA3
 598             res['2'] = 's:RS'  # RS: Rsrc1_EXTRA3
 599         elif regs == ['RA', 'RB', '', 'RT', '', 'CR0']:
 600             res['0'] = 'd:RT;d:CR0'  # RT,CR0: Rdest1_EXTRA3
 601             res['1'] = 's:RA'  # RA: Rsrc1_EXTRA3
 602             res['2'] = 's:RB'  # RB: Rsrc1_EXTRA3
 603         elif regs == ['RA', '', 'RS', 'RA', '', 'CR0']:
 604             res['0'] = 'd:RA;d:CR0'  # RA,CR0: Rdest1_EXTRA3
 605             res['1'] = 's:RA'  # RA: Rsrc1_EXTRA3
 606             res['2'] = 's:RS'  # RS: Rsrc1_EXTRA3
 607         elif regs == ['RA', '', 'RB', 'RT', '', '']:  # maddsubrs
 608             res['0'] = 's:RT;d:RT'  # RT: Rdest1_EXTRA2
 609             res['1'] = 's:RA'  # RA: Rsrc1_EXTRA2
 610             res['2'] = 's:RB'  # RT: Rsrc2_EXTRA2
 611         else:
 612             raise NotImplementedError(insn_name)
 613
 614     elif value == 'RM-2P-2S1D':
 615         res['Etype'] = 'EXTRA2'  # RM EXTRA2 type
 616         if insn_name.startswith('mt'):  # mtcrf
 617             res['0'] = 'd:CR'  # CR: Rdest1_EXTRA2
 618             res['1'] = 's:RS'  # RS: Rsrc1_EXTRA2
 619             res['2'] = 's:CR'  # CR: Rsrc2_EXTRA2
 620         else:
 621             raise NotImplementedError(insn_name)
 622
 623     elif value == 'RM-1P-3S1D':
 624         res['Etype'] = 'EXTRA2'  # RM EXTRA2 type
 625         if regs == ['FRT', 'FRB', 'FRA', 'FRT', '', 'CR1']:  # ffmadds/fdmadds
 626             res['0'] = 's:FRT;d:FRT;d:CR1'  # FRT,CR1: Rdest1_EXTRA2
 627             res['1'] = 's:FRB'  # FRB: Rsrc1_EXTRA2
 628             res['2'] = 's:FRA'  # FRA: Rsrc2_EXTRA2
 629         elif regs == ['RA', 'RB', 'RC', 'RT', '', '']:  # madd*
 630             res['0'] = 'd:RT'  # RT,CR0: Rdest1_EXTRA2
 631             res['1'] = 's:RA'  # RA: Rsrc1_EXTRA2
 632             res['2'] = 's:RB'  # RT: Rsrc2_EXTRA2
 633             res['3'] = 's:RC'  # RT: Rsrc3_EXTRA2
 634         elif regs == ['RA', 'RB', 'RC', 'RT', '', 'CR0']:  # pcdec
 635             res['0'] = 'd:RT;d:CR0'  # RT,CR0: Rdest1_EXTRA2
 636             res['1'] = 's:RA'  # RA: Rsrc1_EXTRA2
 637             res['2'] = 's:RB'  # RT: Rsrc2_EXTRA2
 638             res['3'] = 's:RC'  # RT: Rsrc3_EXTRA2
 639         elif regs == ['RA', 'RB', 'RT', 'RT', '', 'CR0']:  # overwrite 3-in
 640             res['0'] = 's:RT;d:RT;d:CR0'  # RT,CR0: Rdest1_EXTRA2
 641             res['1'] = 's:RA'  # RA: Rsrc1_EXTRA2
 642             res['2'] = 's:RB'  # RT: Rsrc2_EXTRA2
 643         elif insn_name == 'isel':
 644             res['0'] = 'd:RT'  # RT: Rdest1_EXTRA2
 645             res['1'] = 's:RA'  # RA: Rsrc1_EXTRA2
 646             res['2'] = 's:RB'  # RT: Rsrc2_EXTRA2
 647             res['3'] = 's:BC'  # BC: Rsrc3_EXTRA2
 648         else:  # fmadd*
 649             res['0'] = 'd:FRT;d:CR1'  # FRT, CR1: Rdest1_EXTRA2
 650             res['1'] = 's:FRA'  # FRA: Rsrc1_EXTRA2
 651             res['2'] = 's:FRB'  # FRB: Rsrc2_EXTRA2
 652             res['3'] = 's:FRC'  # FRC: Rsrc3_EXTRA2
 653
 654     elif value == 'RM-1P-1D':
 655         res['Etype'] = 'EXTRA3'  # RM EXTRA3 type
 656         if insn_name == 'svstep':
 657             res['0'] = 'd:RT;d:CR0'  # RT,CR0: Rdest1_EXTRA3
 658         if insn_name == 'fmvis':
 659             res['0'] = 'd:FRS'  # FRS: Rdest1_EXTRA3
 660
 661     # HACK! thos should be RM-1P-1S butvthere is a bug with sv.bc
 662     elif value == 'RM-2P-1S':
 663         res['Etype'] = 'EXTRA3'  # RM EXTRA3 type
 664         if insn_name.startswith('bc'):
 665             res['0'] = 's:BI'  # BI: Rsrc1_EXTRA3
 666
 667     elif value == 'RM-1P-1S':
 668         pass  # FIXME
 669
 670     elif value == 'non-SV':
 671         return
 672
 673     else:
 674         raise NotImplementedError(insn_name)
 675
 676     #if insn_name.startswith("rlw"):
 677     #    print("regs ", value, insn_name, regs, res)
 678
 679
 680
 681 def process_csvs(format):
 682
 683     print("# Draft SVP64 Power ISA register 'profile's")
 684     print('')
 685     print("this page is auto-generated, do not edit")
 686     print("created by http://libre-soc.org/openpower/sv_analysis.py")
 687     print('')
 688
 689     (csvs, csvs_svp64, primarykeys, bykey, insn_to_csv, insns,
 690      dictkeys, immediates) = read_csvs()
 691
 692     # mapping to old SVPrefix "Forms"
 693     mapsto = {'3R-1W-CRo': 'RM-1P-3S1D',
 694               '3R-1W': 'RM-1P-3S1D',
 695               '2R-1W-CRio': 'RM-1P-2S1D',
 696               '2R-1W-CRi': 'RM-1P-3S1D',
 697               '2R-1W-CRo': 'RM-1P-2S1D',
 698               '2R': 'non-SV',
 699               '2R-1W': 'RM-1P-2S1D',
 700               '2R-1W-imm': 'RM-1P-2S1D',
 701               '1R-CRio': 'RM-2P-2S1D',
 702               '2R-CRio': 'RM-1P-2S1D',
 703               '2R-CRo': 'RM-1P-2S1D',
 704               '1R': 'non-SV',
 705               '1R-1W-CRio': 'RM-2P-1S1D',
 706               '1R-1W-CRo': 'RM-2P-1S1D',
 707               '1R-1W': 'RM-2P-1S1D',
 708               '1R-1W-imm': 'RM-2P-1S1D',
 709               '1R-CRo': 'RM-2P-1S1D',
 710               '1R-imm': 'RM-1P-1S',
 711               '1W-CRo': 'RM-1P-1D',
 712               '1W': 'non-SV',
 713               '1W-imm': 'RM-1P-1D',
 714               '1W-CRi': 'RM-2P-1S1D',
 715               'CRio': 'RM-2P-1S1D',
 716               'CR=2R1W': 'RM-1P-2S1D',
 717               'CRi': 'RM-2P-1S',  # HACK, bc here, it should be 1P
 718               'imm': 'non-SV',
 719               '': 'non-SV',
 720               'LDST-2R-imm': 'LDSTRM-2P-2S',
 721               'LDST-2R-1W-imm': 'LDSTRM-2P-2S1D',
 722               'LDST-2R-1W': 'LDSTRM-2P-2S1D',
 723               'LDST-2R-2W': 'LDSTRM-2P-2S1D',
 724               'LDST-1R-1W-imm': 'LDSTRM-2P-1S1D',
 725               'LDST-1R-2W-imm': 'LDSTRM-2P-1S2D',
 726               'LDST-3R': 'LDSTRM-2P-3S',
 727               'LDST-3R-CRo': 'LDSTRM-2P-3S',  # st*x
 728               'LDST-3R-1W': 'LDSTRM-2P-2S1D',  # st*x
 729               'LDST-2R': 'non-SV',  # dcbz -- TODO: any vectorizable?
 730               'CRo': 'non-SV',  # mtfsb1 -- TODO: any vectorizable?
 731               }
 732     print("# map to old SV Prefix")
 733     print('')
 734     print('|internal key | public name |')
 735     print('|-----        | ----------  |')
 736     for key in primarykeys:
 737         name = keyname(dictkeys[key])
 738         value = mapsto.get(name, "-")
 739         print(tformat([name, value + " "]))
 740     print('')
 741     print('')
 742
 743     print("# keys")
 744     print('')
 745     print(tformat(tablecols) + " imms | name |")
 746     print(tformat([" - "] * (len(tablecols)+2)))
 747
 748     # print out the keys and the table from which they're derived
 749     for key in primarykeys:
 750         name = keyname(dictkeys[key])
 751         row = tformat(dictkeys[key].values())
 752         imms = list(immediates.get(key, ""))
 753         imms.sort()
 754         row += " %s | " % ("/".join(imms))
 755         row += " %s |" % name
 756         print(row)
 757     print('')
 758     print('')
 759
 760     # print out, by remap name, all the instructions under that category
 761     for key in primarykeys:
 762         name = keyname(dictkeys[key])
 763         value = mapsto.get(name, "-")
 764         print("## %s (%s)" % (name, value))
 765         print('')
 766         print(tformat(['CSV', 'opcode', 'asm', 'flags', 'form']))
 767         print(tformat(['---', '------', '---', '-----', '----']))
 768         rows = bykey[key]
 769         rows.sort()
 770         for row in rows:
 771             print(tformat(row))
 772         print('')
 773         print('')
 774
 775     # for fname, csv in csvs.items():
 776     #    print (fname)
 777
 778     # for insn, row in insns.items():
 779     #    print (insn, row)
 780
 781     print("# svp64 remaps")
 782     svp64 = OrderedDict()
 783     # create a CSV file, per category, with SV "augmentation" info
 784     # XXX note: 'out2' not added here, needs to be added to CSV files
 785     # KEEP TRACK OF THESE https://bugs.libre-soc.org/show_bug.cgi?id=619
 786     csvcols = ['insn', 'mode', 'CONDITIONS', 'Ptype', 'Etype', 'SM']
 787     csvcols += ['0', '1', '2', '3']
 788     csvcols += ['in1', 'in2', 'in3', 'out', 'CR in', 'CR out']  # temporary
 789     for key in primarykeys:
 790         # get the decoded key containing row-analysis, and name/value
 791         dkey = dictkeys[key]
 792         name = keyname(dkey)
 793         value = mapsto.get(name, "-")
 794         if value == 'non-SV':
 795             continue
 796
 797         # print out svp64 tables by category
 798         print("* **%s**: %s" % (name, value))
 799
 800         # store csv entries by svp64 RM category
 801         if value not in svp64:
 802             svp64[value] = []
 803
 804         rows = bykey[key]
 805         rows.sort()
 806
 807         for row in rows:
 808             # for idx in range(len(row)):
 809             #    if row[idx] == 'NONE':
 810             #        row[idx] = ''
 811             # get the instruction
 812             #print(key, row)
 813             insn_name = row[2]
 814             condition = row[3]
 815             insn = insns[(insn_name, condition)]
 816
 817             #if insn_name == 'rlwinm':
 818             #    print ("upd rlwinm", insn)
 819
 820             # start constructing svp64 CSV row
 821             res = OrderedDict()
 822             res['insn'] = insn_name
 823             res['CONDITIONS'] = condition
 824             res['Ptype'] = value.split('-')[1]  # predication type (RM-xN-xxx)
 825             # get whether R_xxx_EXTRAn fields are 2-bit or 3-bit
 826             res['Etype'] = 'EXTRA2'
 827             # go through each register matching to Rxxxx_EXTRAx
 828             for k in ['0', '1', '2', '3']:
 829                 res[k] = ''
 830             # create "fake" out2 (TODO, needs to be added to CSV files)
 831             # KEEP TRACK HERE https://bugs.libre-soc.org/show_bug.cgi?id=619
 832             res['out2'] = 'NONE'
 833             if insn['upd'] == '1':  # LD/ST with update has RA as out2
 834                 res['out2'] = 'RA'
 835
 836             # set the SVP64 mode to NORMAL, LDST, BRANCH or CR
 837             crops = ['mfcr', 'mfocrf', 'mtcrf', 'mtocrf',
 838                      ]
 839             mode = 'NORMAL'
 840             if value.startswith('LDST'):
 841                 if 'x' in insn_name:  # Indexed detection
 842                     mode = 'LDST_IDX'
 843                 else:
 844                     mode = 'LDST_IMM'
 845             elif insn_name.startswith('bc'):
 846                 mode = 'BRANCH'
 847             elif (insn_name.startswith('cmp') or
 848                   insn_name.startswith('cr') or
 849                   insn_name in crops):
 850                 mode = 'CROP'
 851             res['mode'] = mode
 852
 853             # create a register profile list (update res row as well)
 854             regs = regs_profile(insn, res)
 855
 856             #print("regs", insn_name, regs)
 857             extra_classifier(insn_name, value, name, res, regs)
 858
 859             # source-mask is hard to detect, it's part of RM-nn-nn.
 860             # to make style easier, create a yes/no decision here
 861             # see https://libre-soc.org/openpower/sv/svp64/#extra_remap
 862             # MASK_SRC
 863             vstripped = value.replace("LDST", "")
 864             if vstripped in ['RM-2P-1S1D', 'RM-2P-2S',
 865                              'RM-2P-2S1D', 'RM-2P-1S2D', 'RM-2P-3S',
 866                              ]:
 867                 res['SM'] = 'EN'
 868             else:
 869                 res['SM'] = 'NO'
 870             # add to svp64 csvs
 871             # for k in ['in1', 'in2', 'in3', 'out', 'CR in', 'CR out']:
 872             #    del res[k]
 873             # if res['0'] != 'TODO':
 874             for k in res:
 875                 if k == 'CONDITIONS':
 876                     continue
 877                 if res[k] == 'NONE' or res[k] == '':
 878                     res[k] = '0'
 879             svp64[value].append(res)
 880             # also add to by-CSV version
 881             csv_fname = insn_to_csv[insn_name]
 882             csvs_svp64[csv_fname].append(res)
 883
 884     print('')
 885
 886     # now write out the csv files
 887     for value, csv in svp64.items():
 888         if value == '-':
 889             continue
 890             from time import sleep
 891             print("WARNING, filename '-' should NOT exist. instrs missing")
 892             print("TODO: fix this (and put in the bugreport number here)")
 893             sleep(2)
 894         # print out svp64 tables by category
 895         print("## %s" % value)
 896         print('')
 897         cols = csvcols + ['out2']
 898         print(tformat(cols))
 899         print(tformat([" - "] * (len(cols))))
 900         for d in csv:
 901             row = []
 902             for k in cols:
 903                 row.append(d[k])
 904             print(tformat(row))
 905         print('')
 906
 907         #csvcols = ['insn', 'Ptype', 'Etype', '0', '1', '2', '3']
 908         write_csv("%s.csv" % value, csv, csvcols + ['out2'])
 909
 910     # okaaay, now we re-read them back in for producing microwatt SV
 911
 912     # get SVP64 augmented CSV files
 913     svt = SVP64RM(microwatt_format=True)
 914     # Expand that (all .csv files)
 915     pth = find_wiki_file("*.csv")
 916
 917     # Ignore those containing: valid test sprs
 918     for fname in glob_valid_csvs(pth):
 919         svp64_csv = svt.get_svp64_csv(fname)
 920
 921     csvcols = ['insn', 'mode', 'Ptype', 'Etype', 'SM']
 922     csvcols += ['in1', 'in2', 'in3', 'out', 'out2', 'CR in', 'CR out']
 923
 924     if format is Format.VHDL:
 925         # and a nice microwatt VHDL file
 926         file_path = find_wiki_file("sv_decode.vhdl")
 927     elif format is Format.BINUTILS:
 928         file_path = find_wiki_file("binutils.c")
 929
 930     with open(file_path, 'w') as stream:
 931         output(format, svt, csvcols, insns, csvs_svp64, stream)
 932
 933
 934 def output_autogen_disclaimer(format, stream):
 935     lines = (
 936         "this file is auto-generated, do not edit",
 937         "http://libre-soc.org/openpower/sv_analysis.py",
 938         "part of Libre-SOC, sponsored by NLnet",
 939     )
 940     for line in format.wrap_comment(lines):
 941         stream.write(line)
 942         stream.write("\n")
 943     stream.write("\n")
 944
 945
 946 def output(format, svt, csvcols, insns, csvs_svp64, stream):
 947     lens = {
 948         'major': 63,
 949         'minor_4': 63,
 950         'minor_19': 7,
 951         'minor_30': 15,
 952         'minor_31': 1023,
 953         'minor_58': 63,
 954         'minor_59': 31,
 955         'minor_62': 63,
 956         'minor_63l': 511,
 957         'minor_63h': 16,
 958     }
 959
 960     def svp64_canonicalize(item):
 961         (value, csv) = item
 962         value = value.lower().replace("-", "_")
 963         return (value, csv)
 964
 965     csvs_svp64_canon = dict(map(svp64_canonicalize, csvs_svp64.items()))
 966
 967     # disclaimer
 968     output_autogen_disclaimer(format, stream)
 969
 970     # declarations
 971     for line in format.declarations(csvs_svp64_canon.keys(), lens):
 972         stream.write(f"{line}\n")
 973
 974     # definitions
 975     sv_cols = ['sv_in1', 'sv_in2', 'sv_in3', 'sv_out', 'sv_out2',
 976                'sv_cr_in', 'sv_cr_out']
 977     fullcols = csvcols + sv_cols
 978
 979     entries_svp64 = defaultdict(list)
 980     for (value, csv) in filter(lambda kv: kv[0] in lens,
 981                                csvs_svp64_canon.items()):
 982         for entry in csv:
 983             insn = str(entry['insn'])
 984             condition = str(entry['CONDITIONS'])
 985             mode = str(entry['mode'])
 986             sventry = svt.svp64_instrs.get(insn, None)
 987             if sventry is not None:
 988                 sventry['mode'] = mode
 989             op = insns[(insn, condition)]['opcode']
 990             # binary-to-vhdl-binary
 991             if op.startswith("0b"):
 992                 op = "2#%s#" % op[2:]
 993             row = []
 994             for colname in csvcols[1:]:
 995                 re = entry[colname]
 996                 # zero replace with NONE
 997                 if re == '0':
 998                     re = 'NONE'
 999                 # 1/2 predication
1000                 re = re.replace("1P", "P1")
1001                 re = re.replace("2P", "P2")
1002                 row.append(re)
1003             #print("sventry", sventry)
1004             for colname in sv_cols:
1005                 if sventry is None:
1006                     re = 'NONE'
1007                 else:
1008                     re = sventry[colname]
1009                 row.append(re)
1010             entries_svp64[value].append((op, insn, row))
1011
1012     for line in format.definitions(entries_svp64, fullcols):
1013         stream.write(f"{line}\n")
1014
1015
1016 def main():
1017     import os
1018     os.environ['SILENCELOG'] = '1'
1019     parser = argparse.ArgumentParser()
1020     parser.add_argument("-f", "--format",
1021                         type=Format, choices=Format, default=Format.VHDL,
1022                         help="format to be used (binutils or VHDL)")
1023     args = parser.parse_args()
1024     process_csvs(args.format)
1025
1026
1027 if __name__ == '__main__':
1028     # don't do anything other than call main() here, cuz this code is bypassed
1029     # by the sv_analysis command created by setup.py
1030     main()