1 /*********************************************************************
3 SDRAM Controller Transfer control
5 This file is part of the sdram controller project
6 http://www.opencores.org/cores/sdr_ctrl/
8 Description: SDRAM Controller Transfer control
10 This module takes requests from sdrc_bank_ctl and runs the
11 transfer. The input request is guaranteed to be in a bank that is
12 precharged and activated. This block runs the transfer until a
13 burst boundary is reached, then issues another read/write command
14 to sequentially step thru memory if wrap=0, until the transfer is
17 if a read transfer finishes and the caddr is not at a burst boundary
18 a burst terminate command is issued unless another read/write or
19 precharge to the same bank is pending.
21 if a write transfer finishes and the caddr is not at a burst boundary
22 a burst terminate command is issued unless a read/write is pending.
24 If a refresh request is made, the bank_ctl will be held off until
25 the number of refreshes requested are completed.
27 This block also handles SDRAM initialization.
34 - Dinesh Annayya, dinesha@opencores.org
35 Version : 1.0 - 8th Jan 2012
39 Copyright (C) 2000 Authors and OPENCORES.ORG
41 This source file may be used and distributed without
42 restriction provided that this copyright statement is not
43 removed from the file and that any derivative work contains
44 the original copyright notice and the associated disclaimer.
46 This source file is free software; you can redistribute it
47 and/or modify it under the terms of the GNU Lesser General
48 Public License as published by the Free Software Foundation;
49 either version 2.1 of the License, or (at your option) any
52 This source is distributed in the hope that it will be
53 useful, but WITHOUT ANY WARRANTY; without even the implied
54 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
55 PURPOSE. See the GNU Lesser General Public License for more
58 You should have received a copy of the GNU Lesser General
59 Public License along with this source; if not, download it
60 from http://www.opencores.org/lgpl.shtml
62 *******************************************************************/
66 module sdrc_xfr_ctl (clk,
69 /* Transfer request from bank_ctl */
70 r2x_idle, // Req is idle
71 b2x_idle, // All banks are idle
72 b2x_req, // Req from bank_ctl
73 b2x_start, // first chunk of transfer
74 b2x_last, // last chunk of transfer
75 b2x_id, // Transfer ID
76 b2x_ba, // bank address
77 b2x_addr, // row/col address
78 b2x_len, // transfer length
79 b2x_cmd, // transfer command
80 b2x_wrap, // Wrap mode transfer
81 x2b_ack, // command accepted
83 /* Status to bank_ctl, req_gen */
84 b2x_tras_ok, // Tras for all banks expired
85 x2b_refresh, // We did a refresh
86 x2b_pre_ok, // OK to do a precharge (per bank)
87 x2b_act_ok, // OK to do an activate
88 x2b_rdok, // OK to do a read
89 x2b_wrok, // OK to do a write
104 /* Data Flow to the app */
117 /* SDRAM Parameters */
121 /* output for generate row address of the transfer */
126 trp_delay, // Precharge to refresh delay
127 trcar_delay, // Auto-refresh period
128 twr_delay, // Write recovery delay
129 rfsh_time, // time per row (31.25 or 15.6125 uS)
130 rfsh_rmax); // Number of rows to rfsh at a time (<120uS)
133 `define SDR_REQ_ID_W 4
135 `define SDR_RFSH_TIMER_W 12
136 `define SDR_RFSH_ROW_CNT_W 3
145 // SDRAM Commands (CS_N, RAS_N, CAS_N, WE_N)
147 `define SDR_DESEL 4'b1111
148 `define SDR_NOOP 4'b0111
149 `define SDR_ACTIVATE 4'b0011
150 `define SDR_READ 4'b0101
151 `define SDR_WRITE 4'b0100
152 `define SDR_BT 4'b0110
153 `define SDR_PRECHARGE 4'b0010
154 `define SDR_REFRESH 4'b0001
155 `define SDR_MODE 4'b0000
159 `define TARGET_DESIGN `ASIC
160 // 12 bit subtractor is not feasibile for FPGA, so changed to 6 bits
161 `define REQ_BW (`TARGET_DESIGN == `FPGA) ? 6 : 12 // Request Width
163 parameter SDR_DW = 64; // SDR Data Width
164 parameter SDR_BW = 8; // SDR Byte Width
169 /* Req from bank_ctl */
170 input b2x_req, b2x_start, b2x_last, b2x_tras_ok,
171 b2x_wrap, r2x_idle, b2x_idle;
172 input [`SDR_REQ_ID_W-1:0] b2x_id;
174 input [12:0] b2x_addr;
175 input [`REQ_BW-1:0] b2x_len;
179 /* Status to bank_ctl */
180 output [3:0] x2b_pre_ok;
181 output x2b_refresh, x2b_act_ok, x2b_rdok,
183 /* Data Flow to the app */
184 output x2a_rdstart, x2a_wrstart, x2a_rdlast, x2a_wrlast;
185 output [`SDR_REQ_ID_W-1:0] x2a_id;
187 input [SDR_DW-1:0] a2x_wrdt;
188 input [SDR_BW-1:0] a2x_wren_n;
189 output [SDR_DW-1:0] x2a_rddt;
190 output x2a_wrnext, x2a_rdok, sdr_init_done;
192 /* Interface to SDRAMs */
193 output sdr_cs_n, sdr_cke, sdr_ras_n, sdr_cas_n,
195 output [SDR_BW-1:0] sdr_dqm;
197 output [12:0] sdr_addr;
198 input [SDR_DW-1:0] sdr_din;
199 output [SDR_DW-1:0] sdr_dout;
200 output [SDR_BW-1:0] sdr_den_n;
202 output [1:0] xfr_bank_sel;
205 input [12:0] sdram_mode_reg;
206 input [2:0] cas_latency;
207 input [3:0] trp_delay, trcar_delay, twr_delay;
208 input [`SDR_RFSH_TIMER_W-1 : 0] rfsh_time;
209 input [`SDR_RFSH_ROW_CNT_W-1:0] rfsh_rmax;
211 // vish change mode reg ext
212 //reg [12:0] sdram_mode_ext_reg;
213 reg init_delay_done; // winbond initial delay done flag : vish change
217 /************************************************************************/
220 `define XFR_IDLE 2'b00
221 `define XFR_WRITE 2'b01
222 `define XFR_READ 2'b10
223 `define XFR_RDWT 2'b11
225 reg [1:0] xfr_st, next_xfr_st;
226 reg [12:0] xfr_caddr;
228 wire x2a_rdstart, x2a_wrstart, x2a_rdlast, x2a_wrlast;
229 reg l_start, l_last, l_wrap;
230 wire [`SDR_REQ_ID_W-1:0] x2a_id;
231 reg [`SDR_REQ_ID_W-1:0] l_id;
234 wire [12:0] xfr_addr;
235 wire [`REQ_BW-1:0] xfr_len, next_xfr_len;
236 reg [`REQ_BW-1:0] l_len;
238 reg mgmt_idle, mgmt_req;
240 reg [12:0] mgmt_addr;
243 reg sel_mgmt, sel_b2x;
244 reg cb_pre_ok, rdok, wrok, wr_next,
245 rd_next, sdr_init_done, act_cmd, d_act_cmd;
246 wire [3:0] b2x_sdr_cmd, xfr_cmd;
248 wire mgmt_ack, x2b_ack, b2x_read, b2x_write,
249 b2x_prechg, d_rd_next, dt_next, xfr_end,
250 rd_pipe_mt, ld_xfr, rd_last, d_rd_last,
251 wr_last, l_xfr_end, rd_start, d_rd_start,
252 wr_start, page_hit, burst_bdry, xfr_wrap,
254 reg [6:0] l_rd_next, l_rd_start, l_rd_last;
257 reg[11:0] rg_initial_delay;
260 assign b2x_read = (b2x_cmd == `OP_RD) ? 1'b1 : 1'b0;
262 assign b2x_write = (b2x_cmd == `OP_WR) ? 1'b1 : 1'b0;
264 assign b2x_prechg = (b2x_cmd == `OP_PRE) ? 1'b1 : 1'b0;
266 assign b2x_sdr_cmd = (b2x_cmd == `OP_PRE) ? `SDR_PRECHARGE :
267 (b2x_cmd == `OP_ACT) ? `SDR_ACTIVATE :
268 (b2x_cmd == `OP_RD) ? `SDR_READ :
269 (b2x_cmd == `OP_WR) ? `SDR_WRITE : `SDR_DESEL;
271 assign page_hit = (b2x_ba == l_ba) ? 1'b1 : 1'b0;
273 assign b2x_prechg_hit = b2x_prechg & page_hit;
275 assign xfr_cmd = (sel_mgmt) ? mgmt_cmd :
276 (sel_b2x) ? b2x_sdr_cmd : i_xfr_cmd;
278 assign xfr_addr = (sel_mgmt) ? mgmt_addr :
279 (sel_b2x) ? b2x_addr : xfr_caddr+1;
281 assign mgmt_ack = sel_mgmt;
283 assign x2b_ack = sel_b2x;
285 assign ld_xfr = sel_b2x & (b2x_read | b2x_write);
287 assign xfr_len = (ld_xfr) ? b2x_len : l_len;
289 //assign next_xfr_len = (l_xfr_end && !ld_xfr) ? l_len : xfr_len - 1;
290 assign next_xfr_len = (ld_xfr) ? b2x_len :
291 (l_xfr_end) ? l_len: l_len - 1;
293 assign d_rd_next = (cas_latency == 3'b001) ? l_rd_next[2] :
294 (cas_latency == 3'b010) ? l_rd_next[3] :
295 (cas_latency == 3'b011) ? l_rd_next[4] :
296 (cas_latency == 3'b100) ? l_rd_next[5] :
299 assign d_rd_last = (cas_latency == 3'b001) ? l_rd_last[2] :
300 (cas_latency == 3'b010) ? l_rd_last[3] :
301 (cas_latency == 3'b011) ? l_rd_last[4] :
302 (cas_latency == 3'b100) ? l_rd_last[5] :
305 assign d_rd_start = (cas_latency == 3'b001) ? l_rd_start[2] :
306 (cas_latency == 3'b010) ? l_rd_start[3] :
307 (cas_latency == 3'b011) ? l_rd_start[4] :
308 (cas_latency == 3'b100) ? l_rd_start[5] :
311 assign rd_pipe_mt = (cas_latency == 3'b001) ? ~|l_rd_next[1:0] :
312 (cas_latency == 3'b010) ? ~|l_rd_next[2:0] :
313 (cas_latency == 3'b011) ? ~|l_rd_next[3:0] :
314 (cas_latency == 3'b100) ? ~|l_rd_next[4:0] :
317 assign dt_next = wr_next | d_rd_next;
319 assign xfr_end = ~|xfr_len;
321 assign l_xfr_end = ~|(l_len-1);
323 assign rd_start = ld_xfr & b2x_read & b2x_start;
325 assign wr_start = ld_xfr & b2x_write & b2x_start;
327 assign rd_last = rd_next & last_burst & ~|xfr_len[`REQ_BW-1:1];
329 //assign wr_last = wr_next & last_burst & ~|xfr_len[APP_RW-1:1];
331 assign wr_last = last_burst & ~|xfr_len[`REQ_BW-1:1];
333 //assign xfr_ba = (ld_xfr) ? b2x_ba : l_ba;
334 assign xfr_ba = (sel_mgmt) ? mgmt_ba :
335 (sel_b2x) ? b2x_ba : l_ba;
337 assign xfr_wrap = (ld_xfr) ? b2x_wrap : l_wrap;
339 // assign burst_bdry = ~|xfr_caddr[2:0];
340 wire [1:0] xfr_caddr_lsb = (xfr_caddr[1:0]+1);
341 assign burst_bdry = ~|(xfr_caddr_lsb[1:0]);
343 always @ (posedge clk) begin
361 xfr_caddr <= (ld_xfr) ? b2x_addr :
362 (rd_next | wr_next) ? xfr_caddr + 1 : xfr_caddr;
363 l_start <= (dt_next) ? 1'b0 :
364 (ld_xfr) ? b2x_start : l_start;
365 l_last <= (ld_xfr) ? b2x_last : l_last;
366 l_wrap <= (ld_xfr) ? b2x_wrap : l_wrap;
367 l_id <= (ld_xfr) ? b2x_id : l_id;
368 l_ba <= (ld_xfr) ? b2x_ba : l_ba;
369 l_len <= next_xfr_len;
370 l_rd_next <= {l_rd_next[5:0], rd_next};
371 l_rd_start <= {l_rd_start[5:0], rd_start};
372 l_rd_last <= {l_rd_last[5:0], rd_last};
373 act_cmd <= (xfr_cmd == `SDR_ACTIVATE) ? 1'b1 : 1'b0;
374 d_act_cmd <= act_cmd;
375 xfr_st <= next_xfr_st;
376 end // else: !if(~reset_n)
378 end // always @ (posedge clk)
387 sel_b2x = ~mgmt_req & sdr_init_done & b2x_req;
388 i_xfr_cmd = `SDR_DESEL;
389 rd_next = ~mgmt_req & sdr_init_done & b2x_req & b2x_read;
390 wr_next = ~mgmt_req & sdr_init_done & b2x_req & b2x_write;
394 next_xfr_st = (mgmt_req | ~sdr_init_done) ? `XFR_IDLE :
395 (~b2x_req) ? `XFR_IDLE :
396 (b2x_read) ? `XFR_READ :
397 (b2x_write) ? `XFR_WRITE : `XFR_IDLE;
399 end // case: `XFR_IDLE
402 rd_next = ~l_xfr_end |
403 l_xfr_end & ~mgmt_req & b2x_req & b2x_read;
405 rdok = l_xfr_end & ~mgmt_req;
406 // Break the timing path for FPGA Based Design
407 cb_pre_ok = (`TARGET_DESIGN == `FPGA) ? 1'b0 : l_xfr_end;
411 if (l_xfr_end) begin // end of transfer
414 // Current transfer was not wrap mode, may need BT
415 // If next cmd is a R or W or PRE to same bank allow
417 // This is a little pessimistic since BT is issued
418 // for non-wrap mode transfers even if the transfer
419 // ends on a burst boundary, but is felt to be of
420 // minimal performance impact.
423 sel_b2x = b2x_req & ~mgmt_req & (b2x_read | b2x_prechg_hit);
428 // Wrap mode transfer, by definition is end of burst
431 i_xfr_cmd = `SDR_DESEL;
432 sel_b2x = b2x_req & ~mgmt_req & ~b2x_write;
434 end // else: !if(~l_wrap)
436 next_xfr_st = (sdr_init_done) ? ((b2x_req & ~mgmt_req & b2x_read) ? `XFR_READ : `XFR_RDWT) : `XFR_IDLE;
438 end // if (l_xfr_end)
441 // Not end of transfer
442 // If current transfer was not wrap mode and we are at
443 // the start of a burst boundary issue another R cmd to
444 // step sequemtially thru memory, ELSE,
445 // issue precharge/activate commands from the bank control
447 i_xfr_cmd = (burst_bdry & ~l_wrap) ? `SDR_READ : `SDR_DESEL;
448 sel_b2x = ~(burst_bdry & ~l_wrap) & b2x_req;
449 next_xfr_st = `XFR_READ;
451 end // else: !if(l_xfr_end)
453 end // case: `XFR_READ
456 rd_next = ~mgmt_req & b2x_req & b2x_read;
457 wr_next = rd_pipe_mt & ~mgmt_req & b2x_req & b2x_write;
460 wrok = rd_pipe_mt & ~mgmt_req;
464 sel_b2x = ~mgmt_req & b2x_req;
466 i_xfr_cmd = `SDR_DESEL;
468 next_xfr_st = (~mgmt_req & b2x_req & b2x_read) ? `XFR_READ :
469 (~rd_pipe_mt) ? `XFR_RDWT :
470 (~mgmt_req & b2x_req & b2x_write) ? `XFR_WRITE :
473 end // case: `XFR_RDWT
476 rd_next = l_xfr_end & ~mgmt_req & b2x_req & b2x_read;
477 wr_next = ~l_xfr_end |
478 l_xfr_end & ~mgmt_req & b2x_req & b2x_write;
479 rdok = l_xfr_end & ~mgmt_req;
481 wrok = l_xfr_end & ~mgmt_req;
484 if (l_xfr_end) begin // End of transfer
487 // Current transfer was not wrap mode, may need BT
488 // If next cmd is a R or W allow it else issue BT
489 // This is a little pessimistic since BT is issued
490 // for non-wrap mode transfers even if the transfer
491 // ends on a burst boundary, but is felt to be of
492 // minimal performance impact.
495 sel_b2x = b2x_req & ~mgmt_req & (b2x_read | b2x_write);
500 // Wrap mode transfer, by definition is end of burst
503 sel_b2x = b2x_req & ~mgmt_req & ~b2x_prechg_hit;
504 i_xfr_cmd = `SDR_DESEL;
505 end // else: !if(~l_wrap)
507 next_xfr_st = (~mgmt_req & b2x_req & b2x_read) ? `XFR_READ :
508 (~mgmt_req & b2x_req & b2x_write) ? `XFR_WRITE :
511 end // if (l_xfr_end)
514 // Not end of transfer
515 // If current transfer was not wrap mode and we are at
516 // the start of a burst boundary issue another R cmd to
517 // step sequemtially thru memory, ELSE,
518 // issue precharge/activate commands from the bank control
520 if (burst_bdry & ~l_wrap) begin
522 i_xfr_cmd = `SDR_WRITE;
523 end // if (burst_bdry & ~l_wrap)
526 sel_b2x = b2x_req & ~mgmt_req;
527 i_xfr_cmd = `SDR_DESEL;
528 end // else: !if(burst_bdry & ~l_wrap)
530 next_xfr_st = `XFR_WRITE;
531 end // else: !if(l_xfr_end)
533 end // case: `XFR_WRITE
535 endcase // case(xfr_st)
537 end // always @ (xfr_st or ...)
539 // signals to bank_ctl (x2b_refresh, x2b_act_ok, x2b_rdok, x2b_wrok,
542 assign x2b_refresh = (xfr_cmd == `SDR_REFRESH) ? 1'b1 : 1'b0;
544 assign x2b_act_ok = ~act_cmd & ~d_act_cmd;
546 assign x2b_rdok = rdok;
548 assign x2b_wrok = wrok;
550 //assign x2b_pre_ok[0] = (l_ba == 2'b00) ? cb_pre_ok : 1'b1;
551 //assign x2b_pre_ok[1] = (l_ba == 2'b01) ? cb_pre_ok : 1'b1;
552 //assign x2b_pre_ok[2] = (l_ba == 2'b10) ? cb_pre_ok : 1'b1;
553 //assign x2b_pre_ok[3] = (l_ba == 2'b11) ? cb_pre_ok : 1'b1;
555 assign x2b_pre_ok[0] = cb_pre_ok;
556 assign x2b_pre_ok[1] = cb_pre_ok;
557 assign x2b_pre_ok[2] = cb_pre_ok;
558 assign x2b_pre_ok[3] = cb_pre_ok;
559 assign last_burst = (ld_xfr) ? b2x_last : l_last;
561 /************************************************************************/
564 wire [SDR_DW-1:0] x2a_rddt;
566 //assign x2a_start = (ld_xfr) ? b2x_start : l_start;
567 assign x2a_rdstart = d_rd_start;
568 assign x2a_wrstart = wr_start;
570 assign x2a_rdlast = d_rd_last;
571 assign x2a_wrlast = wr_last;
573 assign x2a_id = (ld_xfr) ? b2x_id : l_id;
575 assign x2a_rddt = sdr_din;
577 assign x2a_wrnext = wr_next;
579 assign x2a_rdok = d_rd_next;
581 /************************************************************************/
584 reg sdr_cs_n, sdr_cke, sdr_ras_n, sdr_cas_n,
586 reg [SDR_BW-1:0] sdr_dqm;
589 reg [SDR_DW-1:0] sdr_dout;
590 reg [SDR_BW-1:0] sdr_den_n;
592 always @ (posedge clk)
599 sdr_dqm <= {SDR_BW{1'b1}};
600 sdr_den_n <= {SDR_BW{1'b1}};
603 sdr_cs_n <= xfr_cmd[3];
604 sdr_ras_n <= xfr_cmd[2];
605 sdr_cas_n <= xfr_cmd[1];
606 sdr_we_n <= xfr_cmd[0];
607 // vish change: cke is kept high after initialization
608 // sdr_cke <= (xfr_st != `XFR_IDLE) ? 1'b1 :
609 // ~(mgmt_idle & b2x_idle & r2x_idle);
611 if(init_delay_done) begin
612 sdr_dqm <= (wr_next) ? a2x_wren_n : {SDR_BW{1'b0}};
615 sdr_den_n <= (wr_next) ? {SDR_BW{1'b0}} : {SDR_BW{1'b1}};
616 end // else: !if(~reset_n)
618 always @ (posedge clk) begin
620 if (~xfr_cmd[3]) begin
621 sdr_addr <= xfr_addr;
623 end // if (~xfr_cmd[3])
625 sdr_dout <= (wr_next) ? a2x_wrdt : sdr_dout;
628 end // always @ (posedge clk)
630 /************************************************************************/
631 // Refresh and Initialization
632 //vish change : increased the MGM size and added one more state
634 `define MGM_INIT_DELAY 4'b0000
635 `define MGM_INIT_NOOP 4'b0001
636 `define MGM_POWERUP 4'b0010
637 `define MGM_PRECHARGE 4'b0011
638 `define MGM_PCHWT 4'b0100
639 `define MGM_REFRESH 4'b0101
640 `define MGM_REFWT 4'b0110
641 `define MGM_MODE_REG 4'b0111
642 `define MGM_MODE_WT 4'b1000
643 `define MGM_MODE_EXT_REG 4'b1001
644 `define MGM_MODE_EXT_WT 4'b1010
645 `define MGM_ACTIVE 4'b1011
647 reg [3:0] mgmt_st, next_mgmt_st;
648 reg [3:0] tmr0, tmr0_d;
649 reg [3:0] cntr1, cntr1_d;
650 wire tmr0_tc, cntr1_tc, rfsh_timer_tc, ref_req, precharge_ok;
651 reg ld_tmr0, ld_cntr1, dec_cntr1, set_sdr_init_done;
652 reg [`SDR_RFSH_TIMER_W-1 : 0] rfsh_timer;
653 reg [`SDR_RFSH_ROW_CNT_W-1:0] rfsh_row_cnt;
655 always @ (posedge clk)
657 mgmt_st <= `MGM_POWERUP;
662 sdr_init_done <= 1'b0;
665 mgmt_st <= next_mgmt_st;
666 tmr0 <= (ld_tmr0) ? tmr0_d :
667 (~tmr0_tc) ? tmr0 - 1 : tmr0;
668 cntr1 <= (ld_cntr1) ? cntr1_d :
669 (dec_cntr1) ? cntr1 - 1 : cntr1;
670 sdr_init_done <= (set_sdr_init_done | sdr_init_done) & sdram_enable;
671 rfsh_timer <= (rfsh_timer_tc) ? 0 : rfsh_timer + 1;
672 rfsh_row_cnt <= (~set_sdr_init_done) ? 0 :
673 (rfsh_timer_tc) ? rfsh_row_cnt + 1 : rfsh_row_cnt;
674 end // else: !if(~reset_n)
676 assign tmr0_tc = ~|tmr0;
678 assign cntr1_tc = ~|cntr1;
680 assign rfsh_timer_tc = (rfsh_timer == rfsh_time) ? 1'b1 : 1'b0;
682 assign ref_req = (rfsh_row_cnt >= rfsh_rmax) ? 1'b1 : 1'b0;
684 assign precharge_ok = cb_pre_ok & b2x_tras_ok;
686 assign xfr_bank_sel = l_ba;
689 always @ (posedge clk) begin
691 rg_initial_delay <= 0;
692 init_delay_done <= 0;
693 //sdram_mode_ext_reg <= 0;
695 else if(rg_initial_delay < 2048) begin
696 rg_initial_delay <= rg_initial_delay + 1;
697 init_delay_done <= 0;
699 // sdr_dqm <= {SDR_BW{1'b1}};
702 init_delay_done <= 1;
706 always@(posedge clk) begin
711 mode_set <= wr_mode_set;
714 always @ (mgmt_st or sdram_enable or mgmt_ack or trp_delay or tmr0_tc or
715 cntr1_tc or trcar_delay or rfsh_row_cnt or ref_req or sdr_init_done
716 or precharge_ok or sdram_mode_reg or mode_set or init_delay_done) begin //added mode_set and sdram_mode_ext_reg in the sensitivity list. deleted sdram_mode_ext_reg
718 // always @ (posedge clk) begin
719 case (mgmt_st) // synopsys full_case parallel_case
725 mgmt_cmd = `SDR_DESEL;
727 mgmt_addr = 13'h400; // A10 = 1 => all banks
732 cntr1_d = 4'hf; // changed for sdrams with higher refresh cycles during initialization
733 set_sdr_init_done = 1'b0;
735 next_mgmt_st = (sdram_enable) ? `MGM_INIT_DELAY : `MGM_POWERUP;
736 end // case: `MGM_POWERUP
738 `MGM_INIT_DELAY : begin // Precharge all banks
740 set_sdr_init_done = 1'b0;
743 mgmt_cmd =`SDR_DESEL;
751 next_mgmt_st = (init_delay_done) ? `MGM_INIT_NOOP : `MGM_INIT_DELAY;
752 end // case: `MGM_INIT_DELAY
754 `MGM_INIT_NOOP : begin // Precharge all banks
757 mgmt_cmd = `SDR_NOOP;
759 mgmt_addr = 13'h400; // A10 = 1 => all banks
766 set_sdr_init_done = 1'b0;
767 next_mgmt_st = (mgmt_ack) ? `MGM_PRECHARGE : `MGM_INIT_NOOP;
768 end // case: `MGM_INIT_DELAY
770 `MGM_PRECHARGE : begin // Precharge all banks
773 mgmt_cmd = (precharge_ok) ? `SDR_PRECHARGE : `SDR_DESEL;
775 mgmt_addr = 13'h400; // A10 = 1 => all banks
782 set_sdr_init_done = 1'b0;
783 next_mgmt_st = (precharge_ok & mgmt_ack) ? `MGM_PCHWT : `MGM_PRECHARGE;
784 end // case: `MGM_PRECHARGE
786 `MGM_PCHWT : begin // Wait for Trp
789 mgmt_cmd = `SDR_DESEL;
791 mgmt_addr = 13'h400; // A10 = 1 => all banks
798 set_sdr_init_done = 1'b0;
799 next_mgmt_st = (tmr0_tc) ? `MGM_REFRESH : `MGM_PCHWT;
800 end // case: `MGM_PRECHARGE
802 `MGM_REFRESH : begin // Refresh
805 mgmt_cmd = `SDR_REFRESH;
807 mgmt_addr = 13'h400; // A10 = 1 => all banks
809 tmr0_d = trcar_delay;
810 dec_cntr1 = mgmt_ack;
813 wr_mode_set = mode_set;
814 set_sdr_init_done = 1'b0;
815 next_mgmt_st = (mgmt_ack) ? `MGM_REFWT : `MGM_REFRESH;
816 end // case: `MGM_REFRESH
818 `MGM_REFWT : begin // Wait for trcar
821 mgmt_cmd = `SDR_DESEL;
823 mgmt_addr = 13'h400; // A10 = 1 => all banks
825 tmr0_d = trcar_delay;
828 wr_mode_set = mode_set;
830 set_sdr_init_done = 1'b0;
831 next_mgmt_st = (~tmr0_tc) ? `MGM_REFWT :
832 (~cntr1_tc) ? `MGM_REFRESH :
833 (sdr_init_done) ? `MGM_ACTIVE : (mode_set) ? `MGM_ACTIVE : `MGM_MODE_REG;
834 end // case: `MGM_REFWT
836 `MGM_MODE_REG : begin // Program mode Register & wait for
839 mgmt_cmd = `SDR_MODE;
840 mgmt_ba = {1'b0, sdram_mode_reg[11]};
841 mgmt_addr = sdram_mode_reg;
848 set_sdr_init_done = 1'b0;
849 next_mgmt_st = (mgmt_ack) ? `MGM_MODE_WT : `MGM_MODE_REG;
850 end // case: `MGM_MODE_REG
852 `MGM_MODE_WT : begin // Wait for tMRD
855 mgmt_cmd = `SDR_DESEL;
864 set_sdr_init_done = 1'b0;
865 next_mgmt_st = (~tmr0_tc) ? `MGM_MODE_WT : `MGM_MODE_EXT_REG;
866 end // case: `MGM_MODE_WT
868 `MGM_MODE_EXT_REG : begin // Program mode Register & wait for
871 mgmt_cmd = `SDR_MODE;
873 mgmt_addr = 0;//sdram_mode_ext_reg;
880 set_sdr_init_done = 1'b0;
881 next_mgmt_st = (mgmt_ack) ? `MGM_MODE_EXT_WT : `MGM_MODE_EXT_REG;
882 end // case: `MGM_MODE_EXT_REG
884 `MGM_MODE_EXT_WT : begin // Wait for tMRD
887 mgmt_cmd = `SDR_DESEL;
896 set_sdr_init_done = 1'b0;
897 next_mgmt_st = (~tmr0_tc) ? `MGM_MODE_EXT_WT : `MGM_REFRESH;
898 end // case: `MGM_MODE_WT
900 `MGM_ACTIVE : begin // Wait for ref_req
901 mgmt_idle = ~ref_req;
903 mgmt_cmd = `SDR_DESEL;
911 cntr1_d = rfsh_row_cnt;
912 set_sdr_init_done = 1'b1;
913 next_mgmt_st = (~sdram_enable) ? `MGM_POWERUP :
914 (ref_req) ? `MGM_PRECHARGE : `MGM_ACTIVE;
915 end // case: `MGM_MODE_WT
919 mgmt_cmd =`SDR_DESEL;
928 set_sdr_init_done = 1'b0;
929 next_mgmt_st = `MGM_POWERUP;
933 endcase // case(mgmt_st)
935 end // always @ (mgmt_st or ....)
939 endmodule // sdr_xfr_ctl