src/peripherals/uart/RS232_modified.bsv

   1 /*
   2 Copyright (c) 2013, IIT Madras
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
   6
   7 *  Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
   8 *  Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
   9 *  Neither the name of IIT Madras  nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
  10
  11 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  12 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  13 */
  14 ////////////////////////////////////////////////////////////////////////////////
  15 // Copyright (c) 2010  Bluespec, Inc.   ALL RIGHTS RESERVED.
  16 ////////////////////////////////////////////////////////////////////////////////
  17 //  Filename      : RS232.bsv
  18 //  Description   : Simple UART BFM   RS232 <-> Bit#(8)
  19 ////////////////////////////////////////////////////////////////////////////////
  20 package RS232_modified;
  21
  22 // Notes :
  23
  24 ////////////////////////////////////////////////////////////////////////////////
  25 /// Imports
  26 ////////////////////////////////////////////////////////////////////////////////
  27 import Clocks            ::*;
  28 import GetPut            ::*;
  29 import Connectable       ::*;
  30 import FIFOLevel         ::*;
  31 import Vector            ::*;
  32 import BUtils            ::*;
  33 import Counter           ::*;
  34
  35 ////////////////////////////////////////////////////////////////////////////////
  36 /// Exports
  37 ////////////////////////////////////////////////////////////////////////////////
  38 export RS232             (..);
  39 export UART              (..);
  40 export BaudGenerator     (..);
  41 export Parity            (..);
  42 export StopBits          (..);
  43 export InputFilter       (..);
  44 export Synchronizer      (..);
  45 export EdgeDetector      (..);
  46 export InputMovingFilter (..);
  47 export mkUART;
  48 export mkBaudGenerator;
  49 export mkInputFilter;
  50 export mkSynchronizer;
  51 export mkEdgeDetector;
  52 export mkInputMovingFilter;
  53
  54 ////////////////////////////////////////////////////////////////////////////////
  55 /// Types
  56 ////////////////////////////////////////////////////////////////////////////////
  57 typedef union tagged {
  58    void Start;
  59    void Center;
  60    void Wait;
  61    void Sample;
  62    void Parity;
  63    void StopFirst;
  64    void StopLast;
  65    } RecvState deriving (Bits, Eq);
  66
  67 typedef union tagged {
  68    void Idle;
  69    void Start;
  70    void Wait;
  71    void Shift;
  72    void Stop;
  73    void Stop5;
  74    void Stop2;
  75    void Parity;
  76    } XmitState deriving (Bits, Eq);
  77
  78 typedef enum {
  79    NONE,
  80    ODD,
  81    EVEN
  82    } Parity deriving (Bits, Eq);
  83
  84 typedef enum {
  85    STOP_1,
  86    STOP_1_5,
  87    STOP_2
  88    } StopBits deriving (Bits, Eq);
  89
  90 ////////////////////////////////////////////////////////////////////////////////
  91 /// Interfaces
  92 ////////////////////////////////////////////////////////////////////////////////
  93 (* always_ready, always_enabled *)
  94 interface RS232;
  95    // Inputs
  96    interface Put#(Bit#(1)) sin;
  97    // Outputs
  98    interface Get#(Bit#(1)) sout;
  99 endinterface
 100
 101 interface BaudGenerator;
 102    method    Action    clock_enable();
 103    method    Action    clear();
 104    method    Bool      baud_tick_16x();
 105    method    Bool      baud_tick_2x();
 106 endinterface
 107
 108 interface InputFilter#(numeric type size, type a);
 109    method    Action    clock_enable();
 110    method    a         _read();
 111 endinterface
 112
 113 (* always_ready, always_enabled *)
 114 interface EdgeDetector#(type a);
 115    method    Bool      rising();
 116    method    Bool      falling();
 117 endinterface
 118
 119 (* always_ready, always_enabled *)
 120 interface Synchronizer#(type a);
 121    method    Action    _write(a x);
 122    method    a         _read();
 123 endinterface
 124
 125 interface InputMovingFilter#(numeric type width, numeric type threshold, type a);
 126    method    Action    sample();
 127    method    Action    clear();
 128    method    a         _read();
 129 endinterface
 130
 131 interface UART#(numeric type depth);
 132    (* prefix = "" *)
 133    interface RS232           rs232;
 134    interface Get#(Bit#(8))   tx;
 135    interface Put#(Bit#(8))   rx;
 136    method Bool transmission_done;
 137    method Bool receiver_not_empty;
 138    method Bool receiver_not_full;
 139    method Bool transmittor_not_empty;
 140 endinterface
 141
 142
 143 ////////////////////////////////////////////////////////////////////////////////
 144 ////////////////////////////////////////////////////////////////////////////////
 145 ///
 146 /// Implementation of Baud Generator
 147 ///
 148 ////////////////////////////////////////////////////////////////////////////////
 149 ////////////////////////////////////////////////////////////////////////////////
 150 module mkBaudGenerator#(Bit#(16) divider)(BaudGenerator);
 151
 152    ////////////////////////////////////////////////////////////////////////////////
 153    /// Design Elements
 154    ////////////////////////////////////////////////////////////////////////////////
 155    Counter#(16)                              rBaudCounter        <- mkCounter(0);
 156    PulseWire                                 pwBaudTick16x       <- mkPulseWire;
 157
 158    Counter#(3)                               rBaudTickCounter    <- mkCounter(0);
 159    PulseWire                                 pwBaudTick2x        <- mkPulseWire;
 160
 161    Wire#(Bit#(16))                           wBaudCount          <- mkWire;
 162    rule baud_count_wire;
 163       wBaudCount <= rBaudCounter.value;
 164    endrule
 165    Wire#(Bit#(3))                            wBaudTickCount      <- mkWire;
 166    rule baud_tick_count_wire;
 167       wBaudTickCount <= rBaudTickCounter.value;
 168    endrule
 169
 170    ////////////////////////////////////////////////////////////////////////////////
 171    /// Rules
 172    ////////////////////////////////////////////////////////////////////////////////
 173    rule count_baudtick_16x(pwBaudTick16x);
 174       rBaudTickCounter.up;
 175    endrule
 176
 177    rule assert_2x_baud_tick(rBaudTickCounter.value() == 0 && pwBaudTick16x);
 178       pwBaudTick2x.send;
 179    endrule
 180
 181    ////////////////////////////////////////////////////////////////////////////////
 182    /// Interface Connections / Methods
 183    ////////////////////////////////////////////////////////////////////////////////
 184    method Action clock_enable();
 185       if (rBaudCounter.value() + 1 >= divider) begin
 186          pwBaudTick16x.send;
 187          rBaudCounter.clear;
 188       end
 189       else begin
 190          rBaudCounter.up;
 191       end
 192    endmethod
 193
 194    method Action clear();
 195       rBaudCounter.clear;
 196    endmethod
 197
 198    method Bool baud_tick_16x();
 199       return pwBaudTick16x;
 200    endmethod
 201
 202    method Bool baud_tick_2x();
 203       return pwBaudTick2x;
 204    endmethod
 205
 206 endmodule: mkBaudGenerator
 207
 208 ////////////////////////////////////////////////////////////////////////////////
 209 ////////////////////////////////////////////////////////////////////////////////
 210 ///
 211 /// Implementation of Input Filter
 212 ///
 213 ////////////////////////////////////////////////////////////////////////////////
 214 ////////////////////////////////////////////////////////////////////////////////
 215 module mkInputFilter#(a initval, a din)(InputFilter#(size, a))
 216    provisos( Bits#(a, sa)
 217            , Eq#(a)
 218            , Add#(0, sa, 1)
 219            , Log#(size, logsize)
 220            , Add#(logsize, 1, csize)
 221            );
 222
 223    ////////////////////////////////////////////////////////////////////////////////
 224    /// Design Elements
 225    ////////////////////////////////////////////////////////////////////////////////
 226    Counter#(csize)                           counter             <- mkCounter(0);
 227    Reg#(a)                                   rOut                <- mkReg(initval);
 228
 229    ////////////////////////////////////////////////////////////////////////////////
 230    /// Rules
 231    ////////////////////////////////////////////////////////////////////////////////
 232
 233    ////////////////////////////////////////////////////////////////////////////////
 234    /// Interface Connections / Methods
 235    ////////////////////////////////////////////////////////////////////////////////
 236    method Action clock_enable();
 237       if (din == unpack(1) && counter.value() != fromInteger(valueof(size)))
 238          counter.up;
 239       else if (din == unpack(0) && counter.value() != 0)
 240          counter.down;
 241
 242       if (counter.value() == fromInteger(valueof(size)))
 243          rOut <= unpack(1);
 244       else if (counter.value() == 0)
 245          rOut <= unpack(0);
 246    endmethod
 247
 248    method a _read;
 249       return rOut;
 250    endmethod
 251
 252 endmodule
 253
 254
 255 ////////////////////////////////////////////////////////////////////////////////
 256 ////////////////////////////////////////////////////////////////////////////////
 257 ///
 258 /// Implementation
 259 ///
 260 ////////////////////////////////////////////////////////////////////////////////
 261 ////////////////////////////////////////////////////////////////////////////////
 262 module mkEdgeDetector#(a initval, a din)(EdgeDetector#(a))
 263    provisos( Bits#(a, sa)
 264            , Eq#(a)
 265            , Add#(0, sa, 1)
 266            );
 267
 268    ////////////////////////////////////////////////////////////////////////////////
 269    /// Design Elements
 270    ////////////////////////////////////////////////////////////////////////////////
 271    Reg#(a)                                   rDinD1              <- mkReg(initval);
 272
 273    ////////////////////////////////////////////////////////////////////////////////
 274    /// Rules
 275    ////////////////////////////////////////////////////////////////////////////////
 276    (* fire_when_enabled *)
 277    (* no_implicit_conditions *)
 278    rule pipeline;
 279       rDinD1 <= din;
 280    endrule
 281
 282    ////////////////////////////////////////////////////////////////////////////////
 283    /// Interface Connections / Methods
 284    ////////////////////////////////////////////////////////////////////////////////
 285    method Bool rising();
 286       return (din == unpack(1) && rDinD1 == unpack(0));
 287    endmethod
 288
 289    method Bool falling();
 290       return (din == unpack(0) && rDinD1 == unpack(1));
 291    endmethod
 292
 293 endmodule: mkEdgeDetector
 294
 295 ////////////////////////////////////////////////////////////////////////////////
 296 ///
 297 ////////////////////////////////////////////////////////////////////////////////
 298 function Bool getRising(EdgeDetector#(a) ifc);
 299    return ifc.rising;
 300 endfunction
 301
 302 function Bool getFalling(EdgeDetector#(a) ifc);
 303    return ifc.falling;
 304 endfunction
 305
 306 ////////////////////////////////////////////////////////////////////////////////
 307 ////////////////////////////////////////////////////////////////////////////////
 308 ///
 309 /// Implementation of Synchronizer
 310 ///
 311 ////////////////////////////////////////////////////////////////////////////////
 312 ////////////////////////////////////////////////////////////////////////////////
 313 module mkSynchronizer#(a initval)(Synchronizer#(a))
 314    provisos( Bits#(a, sa)
 315            , Add#(0, sa, 1)
 316            );
 317
 318    ////////////////////////////////////////////////////////////////////////////////
 319    /// Design Elements
 320    ////////////////////////////////////////////////////////////////////////////////
 321    Reg#(a)                                   d1                  <- mkReg(initval);
 322    Reg#(a)                                   d2                  <- mkReg(initval);
 323
 324    ////////////////////////////////////////////////////////////////////////////////
 325    /// Interface Connections / Methods
 326    ////////////////////////////////////////////////////////////////////////////////
 327    method Action _write(x);
 328       d1 <= x;
 329       d2 <= d1;
 330    endmethod
 331
 332    method a _read();
 333       return d2;
 334    endmethod
 335
 336 endmodule: mkSynchronizer
 337
 338 ////////////////////////////////////////////////////////////////////////////////
 339 ////////////////////////////////////////////////////////////////////////////////
 340 ///
 341 /// Implementation of Input Filter
 342 ///
 343 ////////////////////////////////////////////////////////////////////////////////
 344 ////////////////////////////////////////////////////////////////////////////////
 345 module mkInputMovingFilter#(a din)(InputMovingFilter#(width, threshold, a))
 346    provisos( Bits#(a, sa)
 347            , Eq#(a)
 348            , Add#(0, sa, 1)
 349            );
 350
 351    ////////////////////////////////////////////////////////////////////////////////
 352    /// Design Elements
 353    ////////////////////////////////////////////////////////////////////////////////
 354    Counter#(width)                           counter             <- mkCounter(0);
 355    Reg#(a)                                   rOut                <- mkReg(unpack(0));
 356    PulseWire                                 pwSample            <- mkPulseWire;
 357
 358    ////////////////////////////////////////////////////////////////////////////////
 359    /// Rules
 360    ////////////////////////////////////////////////////////////////////////////////
 361    (* preempts = "threshold_compare, take_sample" *)
 362    rule threshold_compare(counter.value() >= fromInteger(valueof(threshold)));
 363       rOut <= unpack(1);
 364    endrule
 365
 366    rule take_sample(pwSample && din == unpack(1));
 367       counter.up;
 368    endrule
 369
 370    ////////////////////////////////////////////////////////////////////////////////
 371    /// Interface Connections / Methods
 372    ////////////////////////////////////////////////////////////////////////////////
 373    method Action sample();
 374       pwSample.send;
 375    endmethod
 376
 377    method Action clear();
 378       counter.clear();
 379       rOut <= unpack(0);
 380    endmethod
 381
 382    method a _read;
 383       return rOut;
 384    endmethod
 385
 386 endmodule
 387
 388
 389 ////////////////////////////////////////////////////////////////////////////////
 390 ////////////////////////////////////////////////////////////////////////////////
 391 ///
 392 /// Implementation of UART
 393 ///
 394 ////////////////////////////////////////////////////////////////////////////////
 395 ////////////////////////////////////////////////////////////////////////////////
 396 module mkUART( Bit#(4) charsize
 397              , Parity paritysel
 398              , StopBits stopbits
 399              , Bit#(16) divider
 400              , UART#(d) ifc)
 401    provisos(Add#(2, _1, d));
 402
 403    Integer fifodepth = valueof(d);
 404
 405    ////////////////////////////////////////////////////////////////////////////////
 406    /// Design Elements
 407    ////////////////////////////////////////////////////////////////////////////////
 408    let                                       baudGen               <- mkBaudGenerator( divider );
 409
 410    ////////////////////////////////////////////////////////////////////////////////
 411    /// Receive UART
 412    ////////////////////////////////////////////////////////////////////////////////
 413    FIFOLevelIfc#(Bit#(8), d)                 fifoRecv              <- mkGFIFOLevel(True, False, True);
 414
 415    Vector#(8, Reg#(Bit#(1)))                 vrRecvBuffer          <- replicateM(mkRegU);
 416
 417    Reg#(Bit#(1))                             rRecvData             <- mkReg(1);
 418
 419    Reg#(RecvState)                           rRecvState            <- mkRegA(Start);
 420    Reg#(Bit#(4))                             rRecvCellCount        <- mkRegA(0);
 421    Reg#(Bit#(4))                             rRecvBitCount         <- mkRegA(0);
 422    Reg#(Bit#(1))                             rRecvParity           <- mkRegA(0);
 423
 424    PulseWire                                 pwRecvShiftBuffer     <- mkPulseWire;
 425    PulseWire                                 pwRecvCellCountReset  <- mkPulseWire;
 426    PulseWire                                 pwRecvResetBitCount   <- mkPulseWire;
 427    PulseWire                                 pwRecvEnableBitCount  <- mkPulseWire;
 428
 429    ////////////////////////////////////////////////////////////////////////////////
 430    /// Transmit UART
 431    ////////////////////////////////////////////////////////////////////////////////
 432    FIFOLevelIfc#(Bit#(8), d)                 fifoXmit              <- mkGFIFOLevel(False, False, True);
 433
 434    Vector#(8, Reg#(Bit#(1)))                 vrXmitBuffer          <- replicateM(mkRegU);
 435
 436    Reg#(XmitState)                           rXmitState            <- mkRegA(Idle);
 437    Reg#(Bit#(4))                             rXmitCellCount        <- mkRegA(0);
 438    Reg#(Bit#(4))                             rXmitBitCount         <- mkRegA(0);
 439    Reg#(Bit#(1))                             rXmitDataOut          <- mkRegA(1);
 440    Reg#(Bit#(1))                             rXmitParity           <- mkRegA(0);
 441
 442    PulseWire                                 pwXmitCellCountReset  <- mkPulseWire;
 443    PulseWire                                 pwXmitResetBitCount   <- mkPulseWire;
 444    PulseWire                                 pwXmitEnableBitCount  <- mkPulseWire;
 445    PulseWire                                 pwXmitLoadBuffer      <- mkPulseWire;
 446    PulseWire                                 pwXmitShiftBuffer     <- mkPulseWire;
 447
 448    ////////////////////////////////////////////////////////////////////////////////
 449    /// Definitions
 450    ////////////////////////////////////////////////////////////////////////////////
 451    let tick               = baudGen.baud_tick_16x;
 452
 453    ////////////////////////////////////////////////////////////////////////////////
 454    /// Baud Clock Enable
 455    ////////////////////////////////////////////////////////////////////////////////
 456    (* no_implicit_conditions, fire_when_enabled *)
 457    rule baud_generator_clock_enable;
 458       baudGen.clock_enable;
 459    endrule
 460
 461    ////////////////////////////////////////////////////////////////////////////////
 462    /// Receive Rules
 463    ////////////////////////////////////////////////////////////////////////////////
 464    rule receive_bit_cell_time_counter(tick);
 465       if (pwRecvCellCountReset)
 466          rRecvCellCount <= 0;
 467       else
 468          rRecvCellCount <= rRecvCellCount + 1;
 469    endrule
 470
 471    rule receive_buffer_shift(pwRecvShiftBuffer);
 472       let v = shiftInAtN(readVReg(vrRecvBuffer), rRecvData);
 473       writeVReg(vrRecvBuffer, v);
 474    endrule
 475
 476    rule receive_bit_counter;
 477       if (pwRecvResetBitCount)
 478          rRecvBitCount <= 0;
 479       else if (pwRecvEnableBitCount)
 480          rRecvBitCount <= rRecvBitCount + 1;
 481    endrule
 482
 483    rule receive_wait_for_start_bit(rRecvState == Start && tick);
 484       pwRecvCellCountReset.send();
 485       if (rRecvData == 1'b0) begin
 486          rRecvState <= Center;
 487       end
 488       else begin
 489          rRecvState <= Start;
 490          pwRecvResetBitCount.send();
 491       end
 492    endrule
 493
 494    rule receive_find_center_of_bit_cell(rRecvState == Center && tick);
 495       if (rRecvCellCount == 4'h4) begin
 496          pwRecvCellCountReset.send();
 497          if (rRecvData == 1'b0)
 498             rRecvState <= Wait;
 499          else
 500             rRecvState <= Start;
 501       end
 502       else begin
 503          rRecvState <= Center;
 504       end
 505    endrule
 506
 507    rule receive_wait_bit_cell_time_for_sample(rRecvState == Wait && rRecvCellCount == 4'hF && tick);
 508       pwRecvCellCountReset.send;
 509
 510       if (rRecvBitCount == charsize) begin
 511          if (paritysel != NONE)
 512             rRecvState <= Parity;
 513          else if (stopbits != STOP_1)
 514             rRecvState <= StopFirst;
 515          else
 516             rRecvState <= StopLast;
 517       end
 518       else if (rRecvBitCount == charsize + 1) begin
 519          if (paritysel == NONE || stopbits == STOP_1)
 520             rRecvState <= StopLast;
 521          else
 522             rRecvState <= StopFirst;
 523       end
 524       else if (rRecvBitCount == charsize + 2) begin
 525          rRecvState <= StopLast;
 526       end
 527       else begin
 528          rRecvState <= Sample;
 529       end
 530    endrule
 531
 532    rule receive_sample_pin(rRecvState == Sample && tick);
 533       pwRecvShiftBuffer.send;
 534       pwRecvEnableBitCount.send;
 535       pwRecvCellCountReset.send;
 536       rRecvState <= Wait;
 537    endrule
 538
 539    rule receive_parity_bit(rRecvState == Parity && tick);
 540       rRecvParity <= rRecvData;
 541       pwRecvEnableBitCount.send;
 542       pwRecvCellCountReset.send;
 543       rRecvState <= Wait;
 544    endrule
 545
 546    rule receive_stop_first_bit(rRecvState == StopFirst && tick);
 547       pwRecvEnableBitCount.send;
 548       pwRecvCellCountReset.send;
 549       if (rRecvData == 1)
 550          rRecvState <= Wait;
 551       else
 552          rRecvState <= Start;
 553    endrule
 554
 555    rule receive_stop_last_bit(rRecvState == StopLast && tick);
 556       Vector#(8, Bit#(1)) data = take(readVReg(vrRecvBuffer));
 557       Bit#(8)          bitdata = pack(data) >> (8 - charsize);
 558
 559       fifoRecv.enq(bitdata);
 560       rRecvState <= Start;
 561       pwRecvCellCountReset.send;
 562    endrule
 563
 564    ////////////////////////////////////////////////////////////////////////////////
 565    /// Transmit Rules
 566    ////////////////////////////////////////////////////////////////////////////////
 567    rule transmit_bit_cell_time_counter(tick);
 568       if (pwXmitCellCountReset)
 569          rXmitCellCount <= 0;
 570       else
 571          rXmitCellCount <= rXmitCellCount + 1;
 572    endrule
 573
 574    rule transmit_bit_counter;
 575       if (pwXmitResetBitCount)
 576          rXmitBitCount <= 0;
 577       else if (pwXmitEnableBitCount)
 578          rXmitBitCount <= rXmitBitCount + 1;
 579    endrule
 580
 581    rule transmit_buffer_load(pwXmitLoadBuffer);
 582       Bit#(8) data = pack(fifoXmit.first);
 583       fifoXmit.deq;
 584
 585       writeVReg(vrXmitBuffer, unpack(data));
 586       rXmitParity <= parity(data);
 587    endrule
 588
 589    rule transmit_buffer_shift(!pwXmitLoadBuffer && pwXmitShiftBuffer);
 590       let v = shiftInAtN(readVReg(vrXmitBuffer), 1);
 591       writeVReg(vrXmitBuffer, v);
 592    endrule
 593
 594    rule transmit_wait_for_start_command(rXmitState == Idle && tick);
 595       rXmitDataOut <= 1'b1;
 596       pwXmitResetBitCount.send;
 597       if (fifoXmit.notEmpty) begin
 598          pwXmitCellCountReset.send;
 599          pwXmitLoadBuffer.send;
 600          rXmitState <= Start;
 601       end
 602       else begin
 603          rXmitState <= Idle;
 604       end
 605    endrule
 606
 607    rule transmit_send_start_bit(rXmitState == Start && tick);
 608       rXmitDataOut <= 1'b0;
 609       if (rXmitCellCount == 4'hF) begin
 610          rXmitState <= Wait;
 611          pwXmitCellCountReset.send;
 612       end
 613       else begin
 614          rXmitState <= Start;
 615       end
 616    endrule
 617
 618    rule transmit_wait_1_bit_cell_time(rXmitState == Wait && tick);
 619       rXmitDataOut <= head(readVReg(vrXmitBuffer));
 620       if (rXmitCellCount == 4'hF) begin
 621          pwXmitCellCountReset.send;
 622          if (rXmitBitCount == (charsize - 1) && (paritysel == NONE)) begin
 623             rXmitState <= Stop;
 624          end
 625          else if (rXmitBitCount == (charsize - 1) && (paritysel != NONE)) begin
 626             rXmitState <= Parity;
 627          end
 628          else begin
 629             rXmitState <= Shift;
 630             pwXmitEnableBitCount.send;
 631          end
 632       end
 633       else begin
 634          rXmitState <= Wait;
 635       end
 636    endrule
 637
 638    rule transmit_shift_next_bit(rXmitState == Shift && tick);
 639       rXmitDataOut <= head(readVReg(vrXmitBuffer));
 640       rXmitState  <= Wait;
 641       pwXmitShiftBuffer.send;
 642    endrule
 643
 644    rule transmit_send_parity_bit(rXmitState == Parity && tick);
 645       case(paritysel) matches
 646          ODD:        rXmitDataOut <= rXmitParity;
 647          EVEN:       rXmitDataOut <= ~rXmitParity;
 648          default:    rXmitDataOut <= 1'b0;
 649       endcase
 650
 651       if (rXmitCellCount == 4'hF) begin
 652          rXmitState   <= Stop;
 653          pwXmitCellCountReset.send;
 654       end
 655       else begin
 656          rXmitState   <= Parity;
 657       end
 658    endrule
 659
 660    rule transmit_send_stop_bit(rXmitState == Stop && tick);
 661       rXmitDataOut <= 1'b1;
 662       if (rXmitCellCount == 4'hF && (stopbits == STOP_1)) begin
 663          rXmitState <= Idle;
 664          pwXmitCellCountReset.send;
 665       end
 666       else if (rXmitCellCount == 4'hF && (stopbits == STOP_2)) begin
 667          rXmitState <= Stop2;
 668          pwXmitCellCountReset.send;
 669       end
 670       else if (rXmitCellCount == 4'hF && (stopbits == STOP_1_5)) begin
 671          rXmitState <= Stop5;
 672          pwXmitCellCountReset.send;
 673       end
 674       else begin
 675          rXmitState <= Stop;
 676       end
 677    endrule
 678
 679    rule transmit_send_stop_bit1_5(rXmitState == Stop5 && tick);
 680       rXmitDataOut <= 1'b1;
 681       if (rXmitCellCount == 4'h7) begin
 682          rXmitState <= Idle;
 683          pwXmitCellCountReset.send;
 684       end
 685       else begin
 686          rXmitState <= Stop5;
 687       end
 688    endrule
 689
 690    rule transmit_send_stop_bit2(rXmitState == Stop2 && tick);
 691       rXmitDataOut <= 1'b1;
 692       if (rXmitCellCount == 4'hF) begin
 693          rXmitState <= Idle;
 694          pwXmitCellCountReset.send;
 695       end
 696       else begin
 697          rXmitState <= Stop2;
 698       end
 699    endrule
 700
 701    ////////////////////////////////////////////////////////////////////////////////
 702    /// Interface Connections / Methods
 703    ////////////////////////////////////////////////////////////////////////////////
 704    interface RS232 rs232;
 705      interface sin = interface Put
 706       method Action put(Bit#(1) in);
 707         rRecvData._write(in);
 708       endmethod
 709      endinterface;
 710      interface sout = interface Get
 711       method ActionValue#(Bit#(1)) get;
 712         return rXmitDataOut;
 713       endmethod
 714      endinterface;
 715    endinterface
 716
 717    interface Get tx;
 718       method ActionValue#(Bit#(8)) get;
 719          let data = pack(fifoRecv.first);
 720          fifoRecv.deq;
 721          return data;
 722       endmethod
 723    endinterface
 724
 725    interface Put rx;
 726       method Action put(x);
 727          fifoXmit.enq(x);
 728       endmethod
 729    endinterface
 730
 731    method Bool transmission_done;
 732            if(!fifoXmit.notEmpty && rXmitState==Idle)
 733               return True;
 734            else
 735               return False;
 736    endmethod
 737
 738    method Bool receiver_not_empty;
 739       return fifoRecv.notEmpty();
 740    endmethod
 741
 742    method Bool receiver_not_full;
 743           return fifoRecv.notFull();
 744    endmethod
 745
 746    method Bool transmittor_not_empty;
 747           return fifoXmit.notEmpty();
 748    endmethod
 749 endmodule
 750
 751
 752 endpackage
 753