fixed indentation issue while generating wire definitions for TWI
[pinmux.git] / src / pinmux_generator.py
1 # ================================== Steps to add peripherals ============
2 # Step-1: create interface declaration for the peripheral to be added.
3 # Remember these are interfaces defined for the pinmux and hence
4 # will be opposite to those defined at the peripheral.
5 # For eg. the output TX from the UART will be input (method Action)
6 # for the pinmux.
7 # These changes will have to be done in interface_decl.py
8 # Step-2 define the wires that will be required to transfer data from the
9 # peripheral interface to the IO cell and vice-versa. Create a
10 # mkDWire for each input/output between the peripheral and the
11 # pinmux. Also create an implicit wire of GenericIOType for each cell
12 # that can be connected to a each bit from the peripheral.
13 # These changes will have to be done in wire_def.py
14 # Step-3: create the definitions for each of the methods defined above.
15 # These changes will have to be done in interface_decl.py
16 # ========================================================================
17
18 # default module imports
19 import os
20 import sys
21 import time
22 import math
23
24 # project module imports
25 from interface_decl import *
26 from interface_def import *
27 from parse import *
28 from wire_def import *
29 from actual_pinmux import *
30 from bus_transactors import *
31
32 if not os.path.exists("bsv_src"):
33 os.makedirs("bsv_src")
34
35 copyright = '''
36 /*
37 This BSV file has been generated by the PinMux tool available at:
38 https://bitbucket.org/casl/pinmux.
39
40 Authors: Neel Gala, Luke
41 Date of generation: ''' + time.strftime("%c") + '''
42 */
43 '''
44 header = copyright+'''
45 package pinmux;
46
47 typedef struct{
48 Bit#(1) outputval; // output from core to pad bit7
49 Bit#(1) output_en; // output enable from core to pad bit6
50 Bit#(1) input_en; // input enable from core to io_cell bit5
51 Bit#(1) pullup_en; // pullup enable from core to io_cell bit4
52 Bit#(1) pulldown_en; // pulldown enable from core to io_cell bit3
53 Bit#(1) drivestrength; // drivestrength from core to io_cell bit2
54 Bit#(1) pushpull_en; // pushpull enable from core to io_cell bit1
55 Bit#(1) opendrain_en; // opendrain enable form core to io_cell bit0
56 } GenericIOType deriving(Eq,Bits,FShow);
57
58 interface MuxSelectionLines;
59 '''
60 footer = '''
61 endinterface;
62 endmodule
63 endpackage
64 '''
65 # ============================================#
66 # ==== populating the file with the code =====#
67 # ============================================#
68
69 # package and interface declaration followed by the generic io_cell definition
70 with open("./bsv_src/pinmux.bsv", "w") as bsv_file:
71 bsv_file.write(header)
72
73 bsv_file.write('''
74
75 // declare the method which will capture the user pin-mux
76 // selection values.The width of the input is dependent on the number
77 // of muxes happening per IO. For now we have a generalized width
78 // where each IO will have the same number of muxes.''')
79
80 for cell in muxed_cells:
81 bsv_file.write(mux_interface.format(cell[0],
82 int(math.log(len(cell) - 1, 2))))
83
84 bsv_file.write('''
85 endinterface
86
87 interface PeripheralSide;
88 // declare the interface to the IO cells.
89 // Each IO cell will have 8 input field (output from pin mux
90 // and on output field (input to pinmux)''')
91 for i in range(0, N_IO):
92 bsv_file.write('''\n // interface for IO CEll-{0}''')
93 bsv_file.write(io_interface.ifacefmt(i))
94 # ==============================================================
95
96 # == create method definitions for all peripheral interfaces ==#
97 for i in range(0, N_UART):
98 bsv_file.write('''
99 // interface declaration between UART-{0} and pinmux'''.format(i))
100 bsv_file.write(uartinterface_decl.ifacefmt(i))
101
102 for i in range(0, N_SPI):
103 bsv_file.write('''
104 // interface declaration between SPI-{0} and pinmux'''.format(i))
105 bsv_file.write(spiinterface_decl.ifacefmt(i))
106
107 for i in range(0, N_TWI):
108 bsv_file.write('''
109 // interface declaration between TWI-{0} and pinmux'''.format(i))
110 bsv_file.write(twiinterface_decl.ifacefmt(i))
111
112 for i in range(0, N_SD):
113 bsv_file.write('''
114 // interface declaration between SD-{0} and pinmux'''.format(i))
115 bsv_file.write(sdinterface_decl.ifacefmt(i))
116
117 for i in range(0, N_JTAG):
118 bsv_file.write('''
119 // interface declaration between JTAG-{0} and pinmux'''.format(i))
120 bsv_file.write(jtaginterface_decl.ifacefmt(i))
121
122 for i in range(0, N_PWM):
123 bsv_file.write('''
124 // interface declaration between PWM-{0} and pinmux'''.format(i))
125 bsv_file.write(pwminterface_decl.ifacefmt(i))
126 # ==============================================================
127
128 # ===== finish interface definition and start module definition=======
129 bsv_file.write('''
130 endinterface
131
132 interface Ifc_pinmux;
133 interface MuxSelectionLines mux_lines;
134 interface PeripheralSide peripheral_side;
135 endinterface
136 (*synthesize*)
137 module mkpinmux(Ifc_pinmux);
138 ''')
139 # ====================================================================
140
141 # ======================= create wire and registers =================#
142 bsv_file.write('''
143 // the followins wires capture the pin-mux selection
144 // values for each mux assigned to a CELL
145 ''')
146 for cell in muxed_cells:
147 bsv_file.write(muxwire.format(cell[0], int(math.log(len(cell) - 1, 2))))
148
149
150 bsv_file.write(
151 '''\n // following wires capture the values sent to the IO Cell''')
152 for i in range(0, N_IO):
153 bsv_file.write(generic_io.format(i))
154
155 for i in range(0, N_UART):
156 bsv_file.write(
157 '''\n // following wires capture signals to IO CELL if uart-{0} is
158 // allotted to it'''.format(i))
159 bsv_file.write(uartwires.format(i))
160
161 for i in range(0, N_SPI):
162 bsv_file.write(
163 '''\n // following wires capture signals to IO CELL if spi-{0} is
164 // allotted to it'''.format(i))
165 bsv_file.write(spiwires.format(i))
166
167 for i in range(0, N_TWI):
168 bsv_file.write(
169 '''\n // following wires capture signals to IO CELL if twi-{0} is
170 // allotted to it'''.format(i))
171 bsv_file.write(twiwires.format(i))
172
173 for i in range(0, N_SD):
174 bsv_file.write(
175 '''\n // following wires capture signals to IO CELL if sd-{0} is
176 // allotted to it'''.format(i))
177 bsv_file.write(sdwires.format(i))
178
179 for i in range(0, N_JTAG):
180 bsv_file.write(
181 '''\n // following wires capture signals to IO CELL if jtag-{0} is
182 // allotted to it'''.format(i))
183 bsv_file.write(jtagwires.format(i))
184
185 for i in range(0, N_PWM):
186 bsv_file.write(
187 '''\n // following wires capture signals to IO CELL if pwm-{0} is
188 // allotted to it'''.format(i))
189 bsv_file.write(pwmwires.format(i))
190 bsv_file.write("\n")
191 # ====================================================================
192 # ========================= Actual pinmuxing ========================#
193 bsv_file.write('''
194 /*====== This where the muxing starts for each io-cell======*/
195 ''')
196 bsv_file.write(pinmux)
197 bsv_file.write('''
198 /*============================================================*/
199 ''')
200 # ====================================================================
201 # ================= interface definitions for each method =============#
202 bsv_file.write('''
203 interface mux_lines = interface MuxSelectionLines
204 ''')
205 for cell in muxed_cells:
206 bsv_file.write(mux_interface_def.format(cell[0],
207 int(math.log(len(cell) - 1, 2))))
208 bsv_file.write('''
209 endinterface;
210 interface peripheral_side = interface PeripheralSide
211 ''')
212 for i in range(0, N_IO):
213 bsv_file.write(io_interface.ifacedef(i))
214 for i in range(0, N_UART):
215 bsv_file.write(uartinterface_def.format(i))
216 for i in range(0, N_SPI):
217 bsv_file.write(spiinterface_def.format(i))
218 for i in range(0, N_TWI):
219 bsv_file.write(twiinterface_def.format(i))
220 for i in range(0, N_SD):
221 bsv_file.write(sdinterface_def.format(i))
222 for i in range(0, N_JTAG):
223 bsv_file.write(jtaginterface_def.format(i))
224 for i in range(0, N_PWM):
225 bsv_file.write(pwminterface_def.format(i))
226 bsv_file.write(footer)
227 print("BSV file successfully generated: bsv_src/pinmux.bsv")
228 # ======================================================================
229
230 with open('bsv_src/PinTop.bsv', 'w') as bsv_file:
231 bsv_file.write(copyright+'''
232 package PinTop;
233 import pinmux::*;
234 interface Ifc_PintTop;
235 method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
236 method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
237 interface PeripheralSide peripheral_side;
238 endinterface
239
240 module mkPinTop(Ifc_PintTop);
241 // instantiate the pin-mux module here
242 Ifc_pinmux pinmux <-mkpinmux;
243
244 // declare the registers which will be used to mux the IOs
245 '''.format(ADDR_WIDTH, DATA_WIDTH))
246
247 for cell in muxed_cells:
248 bsv_file.write('''
249 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
250 int(math.log(len(cell) - 1, 2)), cell[0]))
251
252 bsv_file.write('''
253 // rule to connect the registers to the selection lines of the
254 // pin-mux module
255 rule connect_selection_registers;''')
256
257 for cell in muxed_cells:
258 bsv_file.write('''
259 pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell[0]))
260
261 bsv_file.write('''
262 endrule
263 // method definitions for the write user interface
264 method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
265 Bool err=False;
266 case (addr[{0}:{1}])'''.format(upper_offset, lower_offset,
267 ADDR_WIDTH, DATA_WIDTH))
268 index = 0
269 for cell in muxed_cells:
270 bsv_file.write('''
271 {0}: rg_muxio_{1}<=truncate(data);'''.format(index, cell[0]))
272 index = index + 1
273
274 bsv_file.write('''
275 default: err=True;
276 endcase
277 return err;
278 endmethod''')
279
280 bsv_file.write('''
281 // method definitions for the read user interface
282 method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
283 Bool err=False;
284 Bit#(32) data=0;
285 case (addr[{0}:{1}])'''.format(upper_offset, lower_offset,
286 ADDR_WIDTH, DATA_WIDTH))
287 index = 0
288 for cell in muxed_cells:
289 bsv_file.write('''
290 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index, cell[0]))
291 index = index + 1
292
293 bsv_file.write('''
294 default:err=True;
295 endcase
296 return tuple2(err,data);
297 endmethod
298 interface peripheral_side=pinmux.peripheral_side;
299 endmodule
300 endpackage
301 ''')
302
303 # ######## Generate bus transactors ################
304 with open('bsv_src/bus.bsv', 'w') as bsv_file:
305 bsv_file.write(axi4_lite.format(ADDR_WIDTH, DATA_WIDTH))
306 # ##################################################
307