indent and functionify pinmux generator
[pinmux.git] / src / pinmux_generator.py
1 # ================================== Steps to add peripherals ============
2 # Step-1: create interface declaration for the peripheral to be added.
3 # Remember these are interfaces defined for the pinmux and hence
4 # will be opposite to those defined at the peripheral.
5 # For eg. the output TX from the UART will be input (method Action)
6 # for the pinmux.
7 # These changes will have to be done in interface_decl.py
8 # Step-2 define the wires that will be required to transfer data from the
9 # peripheral interface to the IO cell and vice-versa. Create a
10 # mkDWire for each input/output between the peripheral and the
11 # pinmux. Also create an implicit wire of GenericIOType for each cell
12 # that can be connected to a each bit from the peripheral.
13 # These changes will have to be done in wire_def.py
14 # Step-3: create the definitions for each of the methods defined above.
15 # These changes will have to be done in interface_decl.py
16 # ========================================================================
17
18 # default module imports
19 import os
20 import sys
21 import time
22 import math
23
24 # project module imports
25 from interface_decl import Interfaces, mux_interface, io_interface
26 from parse import Parse
27 from actual_pinmux import init
28 from bus_transactors import axi4_lite
29
30 p = Parse()
31 init(p)
32 ifaces = Interfaces()
33 ifaces.ifaceadd('io', p.N_IO, io_interface, 0)
34
35 if not os.path.exists("bsv_src"):
36 os.makedirs("bsv_src")
37
38 copyright = '''
39 /*
40 This BSV file has been generated by the PinMux tool available at:
41 https://bitbucket.org/casl/pinmux.
42
43 Authors: Neel Gala, Luke
44 Date of generation: ''' + time.strftime("%c") + '''
45 */
46 '''
47 header = copyright + '''
48 package pinmux;
49
50 typedef struct{
51 Bit#(1) outputval; // output from core to pad bit7
52 Bit#(1) output_en; // output enable from core to pad bit6
53 Bit#(1) input_en; // input enable from core to io_cell bit5
54 Bit#(1) pullup_en; // pullup enable from core to io_cell bit4
55 Bit#(1) pulldown_en; // pulldown enable from core to io_cell bit3
56 Bit#(1) drivestrength; // drivestrength from core to io_cell bit2
57 Bit#(1) pushpull_en; // pushpull enable from core to io_cell bit1
58 Bit#(1) opendrain_en; // opendrain enable form core to io_cell bit0
59 } GenericIOType deriving(Eq,Bits,FShow);
60
61 '''
62 footer = '''
63 endinterface;
64 endmodule
65 endpackage
66 '''
67
68 def pinmuxgen():
69 """ populating the file with the code
70 """
71
72 # package and interface declaration followed by
73 # the generic io_cell definition
74 with open("./bsv_src/pinmux.bsv", "w") as bsv_file:
75 bsv_file.write(header)
76
77 bsv_file.write('''\
78 interface MuxSelectionLines;
79
80 // declare the method which will capture the user pin-mux
81 // selection values.The width of the input is dependent on the number
82 // of muxes happening per IO. For now we have a generalized width
83 // where each IO will have the same number of muxes.''')
84
85 for cell in p.muxed_cells:
86 bsv_file.write(mux_interface.ifacefmt(cell[0],
87 int(math.log(len(cell) - 1, 2))))
88
89 bsv_file.write('''
90 endinterface
91
92 interface PeripheralSide;
93 // declare the interface to the IO cells.
94 // Each IO cell will have 8 input field (output from pin mux
95 // and on output field (input to pinmux)''')
96 # ==============================================================
97
98 # == create method definitions for all peripheral interfaces ==#
99 ifaces.ifacefmt(bsv_file)
100
101 # ==============================================================
102
103 # ===== finish interface definition and start module definition=======
104 bsv_file.write('''
105 endinterface
106
107 interface Ifc_pinmux;
108 interface MuxSelectionLines mux_lines;
109 interface PeripheralSide peripheral_side;
110 endinterface
111 (*synthesize*)
112 module mkpinmux(Ifc_pinmux);
113 ''')
114 # ====================================================================
115
116 # ======================= create wire and registers =================#
117 bsv_file.write('''
118 // the followins wires capture the pin-mux selection
119 // values for each mux assigned to a CELL
120 ''')
121 for cell in p.muxed_cells:
122 bsv_file.write(mux_interface.wirefmt(
123 cell[0], int(math.log(len(cell) - 1, 2))))
124
125 ifaces.wirefmt(bsv_file)
126
127 bsv_file.write("\n")
128 # ====================================================================
129 # ========================= Actual pinmuxing ========================#
130 bsv_file.write('''
131 /*====== This where the muxing starts for each io-cell======*/
132 ''')
133 bsv_file.write(p.pinmux)
134 bsv_file.write('''
135 /*============================================================*/
136 ''')
137 # ====================================================================
138 # ================= interface definitions for each method =============#
139 bsv_file.write('''
140 interface mux_lines = interface MuxSelectionLines
141 ''')
142 for cell in p.muxed_cells:
143 bsv_file.write(mux_interface.ifacedef(cell[0],
144 int(math.log(len(cell) - 1, 2))))
145 bsv_file.write('''
146 endinterface;
147 interface peripheral_side = interface PeripheralSide
148 ''')
149 ifaces.ifacedef(bsv_file)
150 bsv_file.write(footer)
151 print("BSV file successfully generated: bsv_src/pinmux.bsv")
152 # ======================================================================
153
154 with open('bsv_src/PinTop.bsv', 'w') as bsv_file:
155 bsv_file.write(copyright + '''
156 package PinTop;
157 import pinmux::*;
158 interface Ifc_PintTop;
159 method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
160 method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
161 interface PeripheralSide peripheral_side;
162 endinterface
163
164 module mkPinTop(Ifc_PintTop);
165 // instantiate the pin-mux module here
166 Ifc_pinmux pinmux <-mkpinmux;
167
168 // declare the registers which will be used to mux the IOs
169 '''.format(p.ADDR_WIDTH, p.DATA_WIDTH))
170
171 for cell in p.muxed_cells:
172 bsv_file.write('''
173 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
174 int(math.log(len(cell) - 1, 2)), cell[0]))
175
176 bsv_file.write('''
177 // rule to connect the registers to the selection lines of the
178 // pin-mux module
179 rule connect_selection_registers;''')
180
181 for cell in p.muxed_cells:
182 bsv_file.write('''
183 pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell[0]))
184
185 bsv_file.write('''
186 endrule
187 // method definitions for the write user interface
188 method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
189 Bool err=False;
190 case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
191 p.ADDR_WIDTH, p.DATA_WIDTH))
192 index = 0
193 for cell in p.muxed_cells:
194 bsv_file.write('''
195 {0}: rg_muxio_{1}<=truncate(data);'''.format(index, cell[0]))
196 index = index + 1
197
198 bsv_file.write('''
199 default: err=True;
200 endcase
201 return err;
202 endmethod''')
203
204 bsv_file.write('''
205 // method definitions for the read user interface
206 method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
207 Bool err=False;
208 Bit#(32) data=0;
209 case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
210 p.ADDR_WIDTH, p.DATA_WIDTH))
211 index = 0
212 for cell in p.muxed_cells:
213 bsv_file.write('''
214 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index, cell[0]))
215 index = index + 1
216
217 bsv_file.write('''
218 default:err=True;
219 endcase
220 return tuple2(err,data);
221 endmethod
222 interface peripheral_side=pinmux.peripheral_side;
223 endmodule
224 endpackage
225 ''')
226
227 # ######## Generate bus transactors ################
228 with open('bsv_src/bus.bsv', 'w') as bsv_file:
229 bsv_file.write(axi4_lite.format(p.ADDR_WIDTH, p.DATA_WIDTH))
230 # ##################################################
231
232 pinmuxgen()
233