defined the user-interface for the memory mapped registers
[pinmux.git] / src / pinmux_generator.py
1 # ================================== Steps to add peripherals ============
2 # Step-1: create interface declaration for the peripheral to be added.
3 # Remember these are interfaces defined for the pinmux and hence
4 # will be opposite to those defined at the peripheral.
5 # For eg. the output TX from the UART will be input (method Action)
6 # for the pinmux.
7 # These changes will have to be done in interface_decl.py
8 # Step-2 define the wires that will be required to transfer data from the
9 # peripheral interface to the IO cell and vice-versa. Create a
10 # mkDWire for each input/output between the peripheral and the
11 # pinmux. Also create an implicit wire of GenericIOType for each cell
12 # that can be connected to a each bit from the peripheral.
13 # These changes will have to be done in wire_def.py
14 # Step-3: create the definitions for each of the methods defined above.
15 # These changes will have to be done in interface_decl.py
16 # ========================================================================
17
18 # default module imports
19 import os
20 import sys
21 import time
22 import math
23
24 # project module imports
25 from interface_decl import *
26 from interface_def import *
27 from parse import *
28 from wire_def import *
29 from actual_pinmux import *
30
31 if not os.path.exists("bsv_src"):
32 os.makedirs("bsv_src")
33
34 bsv_file = open("./bsv_src/pinmux.bsv", "w")
35
36 copyright = '''
37 /*
38 This BSV file has been generated by the PinMux tool available at:
39 https://bitbucket.org/casl/pinmux.
40
41 Authors: Neel Gala, Luke
42 Date of generation: ''' + time.strftime("%c") + '''
43 */
44 '''
45 header = copyright+'''
46 package pinmux;
47
48 typedef struct{
49 Bit#(1) outputval; // output from core to pad bit7
50 Bit#(1) output_en; // output enable from core to pad bit6
51 Bit#(1) input_en; // input enable from core to io_cell bit5
52 Bit#(1) pullup_en; // pullup enable from core to io_cell bit4
53 Bit#(1) pulldown_en; // pulldown enable from core to io_cell bit3
54 Bit#(1) drivestrength; // drivestrength from core to io_cell bit2
55 Bit#(1) pushpull_en; // pushpull enable from core to io_cell bit1
56 Bit#(1) opendrain_en; // opendrain enable form core to io_cell bit0
57 } GenericIOType deriving(Eq,Bits,FShow);
58
59 interface MuxSelectionLines;
60 '''
61 footer = '''
62 endinterface;
63 endmodule
64 endpackage
65 '''
66 # ============================================#
67 # ==== populating the file with the code =====#
68 # ============================================#
69
70 # package and interface declaration followed by the generic io_cell definition
71 bsv_file.write(header)
72
73 bsv_file.write('''
74
75 // declare the method which will capture the user pin-mux
76 // selection values.The width of the input is dependent on the number
77 // of muxes happening per IO. For now we have a generalized width
78 // where each IO will have the same number of muxes.''')
79
80 for cell in muxed_cells:
81 bsv_file.write(mux_interface.format(cell[0],
82 int(math.log(len(cell) - 1, 2))))
83
84 bsv_file.write('''
85 endinterface
86
87 interface PeripheralSide;
88 // declare the interface to the IO cells.
89 // Each IO cell will have 8 input field (output from pin mux
90 // and on output field (input to pinmux)''')
91 for i in range(0, N_IO):
92 bsv_file.write('''\n // interface for IO CEll-{0}''')
93 bsv_file.write(io_interface.format(i))
94 # ==============================================================
95
96 # == create method definitions for all peripheral interfaces ==#
97 for i in range(0, N_UART):
98 bsv_file.write('''
99 // interface declaration between UART-{0} and pinmux'''.format(i))
100 bsv_file.write(uartinterface_decl.format(i))
101
102 for i in range(0, N_SPI):
103 bsv_file.write('''
104 // interface declaration between SPI-{0} and pinmux'''.format(i))
105 bsv_file.write(spiinterface_decl.format(i))
106
107 for i in range(0, N_TWI):
108 bsv_file.write('''
109 // interface declaration between TWI-{0} and pinmux'''.format(i))
110 bsv_file.write(twiinterface_decl.format(i))
111
112 for i in range(0, N_SD):
113 bsv_file.write('''
114 // interface declaration between SD-{0} and pinmux'''.format(i))
115 bsv_file.write(sdinterface_decl.format(i))
116
117 for i in range(0, N_JTAG):
118 bsv_file.write('''
119 // interface declaration between JTAG-{0} and pinmux'''.format(i))
120 bsv_file.write(jtaginterface_decl.format(i))
121 # ==============================================================
122
123 # ===== finish interface definition and start module definition=======
124 bsv_file.write('''
125 endinterface
126
127 interface Ifc_pinmux;
128 interface MuxSelectionLines mux_lines;
129 interface PeripheralSide peripheral_side;
130 endinterface
131 (*synthesize*)
132 module mkpinmux(Ifc_pinmux);
133 ''')
134 # ====================================================================
135
136 # ======================= create wire and registers =================#
137 bsv_file.write('''
138 // the followins wires capture the pin-mux selection
139 // values for each mux assigned to a CELL
140 ''')
141 for cell in muxed_cells:
142 bsv_file.write(muxwire.format(cell[0], int(math.log(len(cell) - 1, 2))))
143
144
145 bsv_file.write(
146 '''\n // following wires capture the values sent to the IO Cell''')
147 for i in range(0, N_IO):
148 bsv_file.write(generic_io.format(i))
149
150 for i in range(0, N_UART):
151 bsv_file.write(
152 '''\n // following wires capture signals to IO CELL if uart-{0} is
153 // allotted to it'''.format(i))
154 bsv_file.write(uartwires.format(i))
155
156 for i in range(0, N_SPI):
157 bsv_file.write(
158 '''\n // following wires capture signals to IO CELL if spi-{0} is
159 // allotted to it'''.format(i))
160 bsv_file.write(spiwires.format(i))
161
162 for i in range(0, N_TWI):
163 bsv_file.write(
164 '''\n // following wires capture signals to IO CELL if twi-{0} is
165 // allotted to it'''.format(i))
166 bsv_file.write(twiwires.format(i))
167
168 for i in range(0, N_SD):
169 bsv_file.write(
170 '''\n // following wires capture signals to IO CELL if sd-{0} is
171 // allotted to it'''.format(i))
172 bsv_file.write(sdwires.format(i))
173
174 for i in range(0, N_JTAG):
175 bsv_file.write(
176 '''\n // following wires capture signals to IO CELL if jtag-{0} is
177 // allotted to it'''.format(i))
178 bsv_file.write(jtagwires.format(i))
179 bsv_file.write("\n")
180 # ====================================================================
181 # ========================= Actual pinmuxing ========================#
182 bsv_file.write('''
183 /*====== This where the muxing starts for each io-cell======*/
184 ''')
185 bsv_file.write(pinmux)
186 bsv_file.write('''
187 /*============================================================*/
188 ''')
189 # ====================================================================
190 # ================= interface definitions for each method =============#
191 bsv_file.write('''
192 interface mux_lines = interface MuxSelectionLines
193 ''')
194 for cell in muxed_cells:
195 bsv_file.write(mux_interface_def.format(cell[0],
196 int(math.log(len(cell) - 1, 2))))
197 bsv_file.write('''
198 endinterface;
199 interface peripheral_side = interface PeripheralSide
200 ''')
201 for i in range(0, N_IO):
202 bsv_file.write(io_interface_def.format(i))
203 for i in range(0, N_UART):
204 bsv_file.write(uartinterface_def.format(i))
205 for i in range(0, N_SPI):
206 bsv_file.write(spiinterface_def.format(i))
207 for i in range(0, N_TWI):
208 bsv_file.write(twiinterface_def.format(i))
209 for i in range(0, N_SD):
210 bsv_file.write(sdinterface_def.format(i))
211 for i in range(0, N_JTAG):
212 bsv_file.write(jtaginterface_def.format(i))
213 bsv_file.write(footer)
214 print("BSV file successfully generated: bsv_src/pinmux.bsv")
215 # ======================================================================
216 bsv_file.close()
217
218 bsv_file = open('bsv_src/PinTop.bsv', 'w')
219 bsv_file.write(copyright+'''
220 package PinTop;
221 import pinmux::*;
222 interface Ifc_PintTop;
223 method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
224 method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
225 interface PeripheralSide peripheral_side;
226 endinterface
227
228 module mkPinTop(Ifc_PintTop);
229 // instantiate the pin-mux module here
230 Ifc_pinmux pinmux <-mkpinmux;
231
232 // declare the registers which will be used to mux the IOs
233 '''.format(ADDR_WIDTH, DATA_WIDTH))
234
235 for cell in muxed_cells:
236 bsv_file.write('''
237 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
238 int(math.log(len(cell) - 1, 2)), cell[0]))
239
240 bsv_file.write('''
241 // rule to connect the registers to the selection lines of the
242 // pin-mux module
243 rule connect_selection_registers;''')
244
245 for cell in muxed_cells:
246 bsv_file.write('''
247 pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell[0]))
248
249 bsv_file.write('''
250 endrule
251 // method definitions for the write user interface
252 method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
253 Bool err=False;
254 case (addr[{0}:{1}])'''.format(upper_offset, lower_offset,
255 ADDR_WIDTH, DATA_WIDTH))
256 index = 0
257 for cell in muxed_cells:
258 bsv_file.write('''
259 {0}: rg_muxio_{1}<=truncate(data);'''.format(index, cell[0]))
260 index = index + 1
261
262 bsv_file.write('''
263 default: err=True;
264 endcase
265 return err;
266 endmethod''')
267
268 bsv_file.write('''
269 // method definitions for the read user interface
270 method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
271 Bool err=False;
272 Bit#(32) data=0;
273 case (addr[{0}:{1}])'''.format(upper_offset, lower_offset,
274 ADDR_WIDTH, DATA_WIDTH))
275 index = 0
276 for cell in muxed_cells:
277 bsv_file.write('''
278 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index, cell[0]))
279 index = index + 1
280
281 bsv_file.write('''
282 default:err=True;
283 endcase
284 return tuple2(err,data);
285 endmethod
286 interface peripheral_side=pinmux.peripheral_side;
287 endmodule
288 endpackage
289 ''')
290 bsv_file.close