adding AXI4Lite transactor for now.
[pinmux.git] / src / pinmux_generator.py
1 # ================================== Steps to add peripherals ============
2 # Step-1: create interface declaration for the peripheral to be added.
3 # Remember these are interfaces defined for the pinmux and hence
4 # will be opposite to those defined at the peripheral.
5 # For eg. the output TX from the UART will be input (method Action)
6 # for the pinmux.
7 # These changes will have to be done in interface_decl.py
8 # Step-2 define the wires that will be required to transfer data from the
9 # peripheral interface to the IO cell and vice-versa. Create a
10 # mkDWire for each input/output between the peripheral and the
11 # pinmux. Also create an implicit wire of GenericIOType for each cell
12 # that can be connected to a each bit from the peripheral.
13 # These changes will have to be done in wire_def.py
14 # Step-3: create the definitions for each of the methods defined above.
15 # These changes will have to be done in interface_decl.py
16 # ========================================================================
17
18 # default module imports
19 import os
20 import sys
21 import time
22 import math
23
24 # project module imports
25 from interface_decl import *
26 from interface_def import *
27 from parse import *
28 from wire_def import *
29 from actual_pinmux import *
30 from bus_transactors import *
31
32 if not os.path.exists("bsv_src"):
33 os.makedirs("bsv_src")
34
35 bsv_file = open("./bsv_src/pinmux.bsv", "w")
36
37 copyright = '''
38 /*
39 This BSV file has been generated by the PinMux tool available at:
40 https://bitbucket.org/casl/pinmux.
41
42 Authors: Neel Gala, Luke
43 Date of generation: ''' + time.strftime("%c") + '''
44 */
45 '''
46 header = copyright+'''
47 package pinmux;
48
49 typedef struct{
50 Bit#(1) outputval; // output from core to pad bit7
51 Bit#(1) output_en; // output enable from core to pad bit6
52 Bit#(1) input_en; // input enable from core to io_cell bit5
53 Bit#(1) pullup_en; // pullup enable from core to io_cell bit4
54 Bit#(1) pulldown_en; // pulldown enable from core to io_cell bit3
55 Bit#(1) drivestrength; // drivestrength from core to io_cell bit2
56 Bit#(1) pushpull_en; // pushpull enable from core to io_cell bit1
57 Bit#(1) opendrain_en; // opendrain enable form core to io_cell bit0
58 } GenericIOType deriving(Eq,Bits,FShow);
59
60 interface MuxSelectionLines;
61 '''
62 footer = '''
63 endinterface;
64 endmodule
65 endpackage
66 '''
67 # ============================================#
68 # ==== populating the file with the code =====#
69 # ============================================#
70
71 # package and interface declaration followed by the generic io_cell definition
72 bsv_file.write(header)
73
74 bsv_file.write('''
75
76 // declare the method which will capture the user pin-mux
77 // selection values.The width of the input is dependent on the number
78 // of muxes happening per IO. For now we have a generalized width
79 // where each IO will have the same number of muxes.''')
80
81 for cell in muxed_cells:
82 bsv_file.write(mux_interface.format(cell[0],
83 int(math.log(len(cell) - 1, 2))))
84
85 bsv_file.write('''
86 endinterface
87
88 interface PeripheralSide;
89 // declare the interface to the IO cells.
90 // Each IO cell will have 8 input field (output from pin mux
91 // and on output field (input to pinmux)''')
92 for i in range(0, N_IO):
93 bsv_file.write('''\n // interface for IO CEll-{0}''')
94 bsv_file.write(io_interface.format(i))
95 # ==============================================================
96
97 # == create method definitions for all peripheral interfaces ==#
98 for i in range(0, N_UART):
99 bsv_file.write('''
100 // interface declaration between UART-{0} and pinmux'''.format(i))
101 bsv_file.write(uartinterface_decl.format(i))
102
103 for i in range(0, N_SPI):
104 bsv_file.write('''
105 // interface declaration between SPI-{0} and pinmux'''.format(i))
106 bsv_file.write(spiinterface_decl.format(i))
107
108 for i in range(0, N_TWI):
109 bsv_file.write('''
110 // interface declaration between TWI-{0} and pinmux'''.format(i))
111 bsv_file.write(twiinterface_decl.format(i))
112
113 for i in range(0, N_SD):
114 bsv_file.write('''
115 // interface declaration between SD-{0} and pinmux'''.format(i))
116 bsv_file.write(sdinterface_decl.format(i))
117
118 for i in range(0, N_JTAG):
119 bsv_file.write('''
120 // interface declaration between JTAG-{0} and pinmux'''.format(i))
121 bsv_file.write(jtaginterface_decl.format(i))
122
123 for i in range(0, N_PWM):
124 bsv_file.write('''
125 // interface declaration between PWM-{0} and pinmux'''.format(i))
126 bsv_file.write(pwminterface_decl.format(i))
127 # ==============================================================
128
129 # ===== finish interface definition and start module definition=======
130 bsv_file.write('''
131 endinterface
132
133 interface Ifc_pinmux;
134 interface MuxSelectionLines mux_lines;
135 interface PeripheralSide peripheral_side;
136 endinterface
137 (*synthesize*)
138 module mkpinmux(Ifc_pinmux);
139 ''')
140 # ====================================================================
141
142 # ======================= create wire and registers =================#
143 bsv_file.write('''
144 // the followins wires capture the pin-mux selection
145 // values for each mux assigned to a CELL
146 ''')
147 for cell in muxed_cells:
148 bsv_file.write(muxwire.format(cell[0], int(math.log(len(cell) - 1, 2))))
149
150
151 bsv_file.write(
152 '''\n // following wires capture the values sent to the IO Cell''')
153 for i in range(0, N_IO):
154 bsv_file.write(generic_io.format(i))
155
156 for i in range(0, N_UART):
157 bsv_file.write(
158 '''\n // following wires capture signals to IO CELL if uart-{0} is
159 // allotted to it'''.format(i))
160 bsv_file.write(uartwires.format(i))
161
162 for i in range(0, N_SPI):
163 bsv_file.write(
164 '''\n // following wires capture signals to IO CELL if spi-{0} is
165 // allotted to it'''.format(i))
166 bsv_file.write(spiwires.format(i))
167
168 for i in range(0, N_TWI):
169 bsv_file.write(
170 '''\n // following wires capture signals to IO CELL if twi-{0} is
171 // allotted to it'''.format(i))
172 bsv_file.write(twiwires.format(i))
173
174 for i in range(0, N_SD):
175 bsv_file.write(
176 '''\n // following wires capture signals to IO CELL if sd-{0} is
177 // allotted to it'''.format(i))
178 bsv_file.write(sdwires.format(i))
179
180 for i in range(0, N_JTAG):
181 bsv_file.write(
182 '''\n // following wires capture signals to IO CELL if jtag-{0} is
183 // allotted to it'''.format(i))
184 bsv_file.write(jtagwires.format(i))
185
186 for i in range(0, N_PWM):
187 bsv_file.write(
188 '''\n // following wires capture signals to IO CELL if pwm-{0} is
189 // allotted to it'''.format(i))
190 bsv_file.write(pwmwires.format(i))
191 bsv_file.write("\n")
192 # ====================================================================
193 # ========================= Actual pinmuxing ========================#
194 bsv_file.write('''
195 /*====== This where the muxing starts for each io-cell======*/
196 ''')
197 bsv_file.write(pinmux)
198 bsv_file.write('''
199 /*============================================================*/
200 ''')
201 # ====================================================================
202 # ================= interface definitions for each method =============#
203 bsv_file.write('''
204 interface mux_lines = interface MuxSelectionLines
205 ''')
206 for cell in muxed_cells:
207 bsv_file.write(mux_interface_def.format(cell[0],
208 int(math.log(len(cell) - 1, 2))))
209 bsv_file.write('''
210 endinterface;
211 interface peripheral_side = interface PeripheralSide
212 ''')
213 for i in range(0, N_IO):
214 bsv_file.write(io_interface_def.format(i))
215 for i in range(0, N_UART):
216 bsv_file.write(uartinterface_def.format(i))
217 for i in range(0, N_SPI):
218 bsv_file.write(spiinterface_def.format(i))
219 for i in range(0, N_TWI):
220 bsv_file.write(twiinterface_def.format(i))
221 for i in range(0, N_SD):
222 bsv_file.write(sdinterface_def.format(i))
223 for i in range(0, N_JTAG):
224 bsv_file.write(jtaginterface_def.format(i))
225 for i in range(0, N_PWM):
226 bsv_file.write(pwminterface_def.format(i))
227 bsv_file.write(footer)
228 print("BSV file successfully generated: bsv_src/pinmux.bsv")
229 # ======================================================================
230 bsv_file.close()
231
232 bsv_file = open('bsv_src/PinTop.bsv', 'w')
233 bsv_file.write(copyright+'''
234 package PinTop;
235 import pinmux::*;
236 interface Ifc_PintTop;
237 method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
238 method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
239 interface PeripheralSide peripheral_side;
240 endinterface
241
242 module mkPinTop(Ifc_PintTop);
243 // instantiate the pin-mux module here
244 Ifc_pinmux pinmux <-mkpinmux;
245
246 // declare the registers which will be used to mux the IOs
247 '''.format(ADDR_WIDTH, DATA_WIDTH))
248
249 for cell in muxed_cells:
250 bsv_file.write('''
251 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
252 int(math.log(len(cell) - 1, 2)), cell[0]))
253
254 bsv_file.write('''
255 // rule to connect the registers to the selection lines of the
256 // pin-mux module
257 rule connect_selection_registers;''')
258
259 for cell in muxed_cells:
260 bsv_file.write('''
261 pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell[0]))
262
263 bsv_file.write('''
264 endrule
265 // method definitions for the write user interface
266 method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
267 Bool err=False;
268 case (addr[{0}:{1}])'''.format(upper_offset, lower_offset,
269 ADDR_WIDTH, DATA_WIDTH))
270 index = 0
271 for cell in muxed_cells:
272 bsv_file.write('''
273 {0}: rg_muxio_{1}<=truncate(data);'''.format(index, cell[0]))
274 index = index + 1
275
276 bsv_file.write('''
277 default: err=True;
278 endcase
279 return err;
280 endmethod''')
281
282 bsv_file.write('''
283 // method definitions for the read user interface
284 method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
285 Bool err=False;
286 Bit#(32) data=0;
287 case (addr[{0}:{1}])'''.format(upper_offset, lower_offset,
288 ADDR_WIDTH, DATA_WIDTH))
289 index = 0
290 for cell in muxed_cells:
291 bsv_file.write('''
292 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index, cell[0]))
293 index = index + 1
294
295 bsv_file.write('''
296 default:err=True;
297 endcase
298 return tuple2(err,data);
299 endmethod
300 interface peripheral_side=pinmux.peripheral_side;
301 endmodule
302 endpackage
303 ''')
304 bsv_file.close
305 # ######## Generate bus transactors ################
306 bsv_file = open('bsv_src/bus.bsv', 'w')
307 bsv_file.write(axi4_lite.format(ADDR_WIDTH, DATA_WIDTH))
308 bsv_file.close
309 # ##################################################